Patent application number | Description | Published |
20080309396 | Hacking Detector Circuit For Semiconductor Integrated Circuit and Detecting Method Thereof - Disclosed is a semiconductor integrated circuit which includes a pre-charge capacitor connected to a check node pre-charged. A sense capacitor is configured to discharge the check node. A detector is configured to detect whether the sense capacitor is exposed, based upon a voltage of the check node after a predetermined length of time has elapses. | 12-18-2008 |
20090010071 | NONVOLATILE MEMORY DEVICE AND ERASING METHOD - Disclosed is an erasing method for a nonvolatile memory device that includes erasing selected memory cells and erase-verifying the selected memory cells after increasing their threshold voltage by application of a negative bulk bias voltage. | 01-08-2009 |
20100124123 | Nonvolatile Memory Device with Incremental Step Pulse Programming - A nonvolatile memory device includes a sense amplifier circuit sensing first data from a memory cell via a bit line and outputting the sensed first data, in response to a read command. A write driver circuit programs the memory cell and stores second data indicating a programming state of the memory cell, in response to a program command. A verification block outputs a result of a comparison between the first and second data in response to a first read command. The second data is updated based on the determination on the programming of the memory cell in response to a second read command applied following the first read command. | 05-20-2010 |
20100232227 | NON-VOLATILE MEMORY DEVICE AND PROGRAM METHOD THEREOF - A non-volatile memory device including a memory cell array; a read/write circuit configured to drive bit lines of the memory cell array with a negative bit line voltage according to data to be programmed; a bit line setup-time measuring circuit configured to measure the bit line setup-time, which may be a function of the amount of data to be programmed, at each ISPP program loop; and a control logic configured to control the program voltage and/or the applied time of a program voltage applied to the selected wordline of the memory cell array based on the measured bit line setup-times measured at each ISPP program loop. | 09-16-2010 |
20100241877 | IC CARD WITH PARALLEL ACCESSED MEMORY BLOCKS - Disclosed is an integrated circuit card which includes a central processing unit (CPU); a first memory block and a second memory block configured to operate responsive to a control of the CPU; and a high voltage generator block configured to generate a high voltage to be supplied to the first and second memory blocks. When bit lines of the first memory block are set by the high voltage, the CPU controls the high voltage generator block to supply the second memory block with the high voltage for a program operation of the second memory block during the program operation of the first memory block. | 09-23-2010 |
20100323799 | SERVICE PROVIDING METHOD USING ON-LINE GAME, AND RECORDING MEDIA RECORDING PROGRAM FOR IMPLEMENTING THE METHOD - An approach is provided for providing a service using an on-line game capable of, maximizing effects of services associated with the on-line game, and recording media recording a program for implementing the service providing method. The service providing method may include, for example, storing, in a rendering region, game object drawing information of a game screen for the on-line game in response to a request for reproducing the game screen; hooking the rendering region to change the game object drawing information so that service object information provided from a game server is included in the game object drawing information; storing the changed game object drawing information in the rendering region; and providing the game screen by rendering the game object drawing information including the service object information stored in the rendering region. | 12-23-2010 |
20110101114 | Memory System and Data Reading Method Thereof - A memory system includes a memory and a memory controller operating to control the memory. The memory includes a random accessible memory including a memory cell array operable in a random access mode, a NAND flash memory, and a selection circuit making the memory controller operate either one of the random accessible memory or the NAND flash memory. | 05-05-2011 |
20110225351 | MEMORY CARD AND MEMORY SYSTEM HAVING THE SAME - A memory card includes: a first memory chip responding to all commands input externally; and a second memory chip responding to commands, among the commands input externally, relevant to reading, programming, and erasing operations with data. Card identification information stored in the first memory chip includes capacity information corresponding to a sum of sizes of the first and second memory chips. The plurality of memory chips of the memory card are useful in designing the memory card with storage capacity in various forms. | 09-15-2011 |
20120300548 | MEMORY SYSTEM AND DATA READING METHOD THEREOF - A memory system includes a memory and a memory controller operating to control the memory. The memory includes a random accessible memory including a memory cell array operable in a random access mode, a NAND flash memory, and a selection circuit making the memory controller operate either one of the random accessible memory or the NAND flash memory. | 11-29-2012 |
20130316825 | SERVICE PROVIDING METHOD USING ON-LINE GAME, AND RECORDING MEDIA RECORDING PROGRAM FOR IMPLEMENTING THE METHOD - An approach is provided for providing a service using an on-line game capable of, maximizing effects of services associated with the on-line game, and recording media recording a program for implementing the service providing method. The service providing method may include, for example, storing, in a rendering region, game object drawing information of a game screen for the on-line game in response to a request for reproducing the game screen; hooking the rendering region to change the game object drawing information so that service object information provided from a game server is included in the game object drawing information; storing the changed game object drawing information in the rendering region; and providing the game screen by rendering the game object drawing information including the service object information stored in the rendering region. | 11-28-2013 |
Patent application number | Description | Published |
20100312919 | MOBILE TERMINAL AND METHOD FOR CONTROLLING THE MOBILE TERMINAL TO BE USED THROUGH HOST - A mobile terminal and a method for controlling the mobile terminal to be used through a host device are disclosed. The method for controlling the mobile terminal to be used through the host device includes transmitting a virtualization engine and driver programs of user modes of the mobile terminal to the host device; selecting one of the user modes; and transmitting information of the selected one user mode to the host device, wherein the transmitted virtualization engine is recognized as a part of an operating system (OS) of the host device, and is programmed to drive a driver program corresponding to each of the user modes within the host device. | 12-09-2010 |
20110042610 | METHOD FOR PREPARING CATHODE ACTIVE MATERIAL FOR LITHIUM SECONDARY BATTERY - Disclosed is a method for preparing a cathode active material for a lithium secondary battery, and the preparing method includes: adding a phosphorus compound to a transition metal oxide dispersion liquid to prepare a coating liquid; drying the coating liquid to prepare a powder including phosphorus oxide coated on the surface of the transition metal oxide; and dry-mixing the powder coated with the phosphorus oxide with a lithium intercalation compound, and then firing the mixture to form a solid solution compound of Li-M | 02-24-2011 |
20130151895 | APPARATUS AND METHOD OF MANAGING DATABASES OF ACTIVE NODE AND STANDBY NODE OF MAIN MEMORY DATABASE MANAGEMENT SYSTEM - Databases of an active node and a standby node of a main memory database management system (MMDBMS) are managed so as to prevent loss of a transaction caused by failure of any one of the active node or the standby node. The MMDBMS is configured to prevent data mismatch between the active node and the standby node when failure of any one of the active node and the standby node occurs. In case of failure of one of the nodes, log information from the other node is obtained to recover the failed node. | 06-13-2013 |
20130198133 | PARALLEL PROCESSING APPARATUS AND METHOD IN DATABASE MANAGEMENT SYSTEM FOR SYNCHRONOUS REPLICATION - A parallel-processing apparatus and method provide for synchronous replication in a database management system (DBMS). During synchronous replication into the active node and the standby node in the DBMS, replications of transactions are parallelized in units of transactions, thereby improving a performance of the DBMS, guaranteeing atomicity and consistency of the transaction, and solving the deadlock state which may occur in parallel-processing. | 08-01-2013 |
20150029312 | APPARATUS AND METHOD FOR DETECTING OBJECT AUTOMATICALLY AND ESTIMATING DEPTH INFORMATION OF IMAGE CAPTURED BY IMAGING DEVICE HAVING MULTIPLE COLOR-FILTER APERTURE - Disclosed are an apparatus and a method for detecting an object automatically and estimating depth information of an image captured by an imaging device having a multiple color-filter aperture. A background generation unit detects a movement from a current image frame among a plurality of continuous image frames captured by an MCA camera to generate a background image frame corresponding to the current image frame. An object detection unit detects an object region included in the current image frame based on differentiation between a plurality of color channels of the current image frame and a plurality of color channels of the background image frame. According to an embodiment of the present invention, it is possible to automatically detect an object by a repetitively updated background image frame and to accurately estimate object information by separately detecting an object for each color channel by considering a property of the MCA camera. | 01-29-2015 |
Patent application number | Description | Published |
20090190109 | SUBSTRATE TRANSFER APPARTUS - A substrate transfer apparatus that is designo provide an inclined transfer function that improves liquid saving efficiency of a process solution (developing solution) during the transfer of the substrate. The substrate transfer apparatus includes a first transfer unit for transferring a substrate, a second transfer unit spaced apart from an end of the first transfer unit, a third transfer unit disposed between the first and second transfer units and providing an inclined transfer that is capable of saving a developing solution adhered to the substrate during transfer of the substrate, and a transfer controller for controlling an inclined transfer angle and a connection state of the third transfer unit. | 07-30-2009 |
20100002371 | DOCKING STATION AND PORTABLE COMPUTER HAVING THE SAME AND A METHOD OF CONNECTING THE DOCKING STATION AND PORTABLE COMPUTER - A docking station which is electrically connected to a computer main body unit of a portable computer, the docking station includes a docking main body which supports a rear area of the computer main body unit against an installation surface and is electrically connected with the computer main body unit, and an angle adjusting unit which is rotatably coupled to the docking main body to adjust an installation angle of the docking main body with respect to the installation surface. | 01-07-2010 |
20110316673 | RFID TAG AND METHOD RECEIVING RFID TAG SIGNAL - Provided are a Radio Frequency IDentification (RFID) tag with a signal reception method. The RFID tag includes a demodulator that receives a read signal containing read data. The demodulator includes; a voltage generating circuit that provides a first voltage signal and a second voltage signal derived from the received read signal, an inverter that provides a data pulse signal indicative of the read data by inverting the second voltage signal using an inverting voltage defined in relation to the first voltage signal, and a buffer that recovers the read data by buffering the data pulse signal. | 12-29-2011 |
20120086282 | Smart Cards - A smart card includes an internal voltage generator, a clock generator, and an internal circuit. The internal voltage generator generates a first internal voltage and a second internal voltage based on an input voltage received through an antenna. A level of the second internal voltage is lower than a level of the first internal voltage. The clock generator receives the first internal voltage and the second internal voltage to generate a clock signal. A frequency of the clock signal is changed according to the level of the first internal voltage. The internal circuit operates based on the clock signal and the second internal voltage. | 04-12-2012 |
20120113740 | ROW DECODER CIRCUIT - A row decoder circuit includes a decoding unit and first and second wordline driving units. The decoding unit generates a first driving signal and a second driving signal based on a selection signal and wordline voltages. A voltage level of the first driving signal and a voltage level of the second driving signal depend on an operation mode. The first wordline driving unit is connected to a first wordline and outputs one of the first driving signal and the second driving signal as a first wordline driving signal based on first driving control signals. The second wordline driving unit is connected to a second wordline and outputs one of the first driving signal and the second driving signal as a second wordline driving signal based on second driving control signals. | 05-10-2012 |
20120155208 | NEGATIVE HIGH VOLTAGE GENERATOR AND NON-VOLATILE MEMORY DEVICE INCLUDING NEGATIVE HIGH VOLTAGE GENERATOR - A negative high voltage generator includes a charge providing unit and a voltage conversion unit. The charge providing unit is configured to periodically output a predetermined amount of positive charges received from a supply voltage. The voltage conversion unit is configured to store the positive charges and to discharge the stored positive charges to a ground voltage to generate a negative high voltage having a magnitude larger than a magnitude of the supply voltage. | 06-21-2012 |
20130170126 | MOBILE APPARATUS - A mobile apparatus includes a first body, a second body, a rotary adaptor including an accommodation portion to accommodate the second body, rotatably installed on the first body, and to move the second body to a position where the second body is stacked on the first body and a position where the second body is unfolded, first magnets disposed on the accommodation portion, and second magnets disposed on the second body so as to face the first magnets and having different polarity from the first magnets. | 07-04-2013 |
Patent application number | Description | Published |
20120113737 | ELECTRONIC DEVICE AND MEMORY DEVICE OF CURRENT COMPENSATION - An electronic device includes a functional unit and a current compensation unit. The functional unit operates based on a power supplied by an external host through power supply lines and generates a control signal based on an amount of power consumption of the functional unit. The current compensation unit compensates a change in a power supply current based on the control signal, where the power supply current is a current flowing through the power supply lines. | 05-10-2012 |
20120151502 | APPARATUS AND METHOD FOR DYNAMICALLY RECONFIGURING STATE OF APPLICATION PROGRAM IN A MANY-CORE SYSTEM - An apparatus and method for dynamically reconfiguring a state of an application program in a many-core system is described. The apparatus may receive registration information from an application program, in response to a state change of the application program, and may process the state change of the application program based on the received registration information. | 06-14-2012 |
20120159501 | SYNCHRONIZATION SCHEDULING APPARATUS AND METHOD IN REAL-TIME MULT-CORE SYSTEM - A synchronization scheduling apparatus and method in a real-time multi-core system are described. The synchronization scheduling apparatus may include a plurality of cores, each having at least one wait queue, a storage unit to store information regarding a first core receiving a wake-up signal in a previous cycle among the plurality of cores, and a scheduling processor to schedule tasks stored in the at least one wait queue, based on the information regarding the first core. | 06-21-2012 |
20130006183 | CYLINDER PUMP - The present invention relates to a simple and small cylinder pump, which can stably supply a medical fluid regardless of the installed height of a liquid container or a blood bag. The cylinder pump includes an upper casing, and a lower casing coupled to the upper casing. An upper rotation member is rotatably inserted in the upper casing. A lower rotation member slidingly contacting the upper rotation member is rotatably inserted in the lower casing. An inner wall of the upper casing, a lower outer surface of the upper rotation member, an inner wall of the lower casing, and an upper outer surface of the rotation member constitute a cylinder having a single-tube shape. Plungers are installed on the upper rotation member and on the lower rotation member, respectively, and rotate in the cylinder, the ends of which are closed. | 01-03-2013 |