Patent application number | Description | Published |
20080282229 | Apparatus and method of detecting errors in embedded software - A method and apparatus for detecting errors in an application software of an embedded system are provided. The method of detecting errors in an application software includes determining a development language of the application software and an operating system on which the application software is executed; replacing an error detection syntax inserted in order to examine an error in a predetermined function of the application software, with an error detection syntax according to the result of the determination; and performing exception handling for an error occurring in the function according to the result of the replacement, and logging error information according to the exception handling. According to the method and apparatus, an error can be automatically detected and logged irrespective of a development language and an operating system. | 11-13-2008 |
20090187912 | Method and apparatus for migrating task in multi-processor system - A method and apparatus for migrating a task in a multi-processor system. The method includes examining whether a second process has been allocated to a second processor, the second process having a same instruction to execute as a first process and having different data to process in response to the instruction from the first process, the instruction being to execute the task; selecting a method of migrating the first process or a method of migrating a thread included in the first process based on the examining and migrating the task from a first processor to the second processor using the selected method. Therefore, cost and power required for task migration can be minimized. Consequently, power consumption can be maintained in a low-power environment, such as an embedded system, which, in turn, optimizes the performance of the multi-processor system and prevents physical damage to the circuit of the multi-processor system. | 07-23-2009 |
20100036641 | System and method of estimating multi-tasking performance - A method and system of estimating multi-tasking performance performed in multi-processor are described. The method includes dividing a plurality of tasks into a plurality of sub tasks in accordance with predefined operation types, arranging the plurality of sub tasks in accordance with a predecessor-successor structure based on the operation types of the plurality of sub tasks, and estimating multi-tasking performance of the plurality of tasks using the arranged plurality of sub tasks. | 02-11-2010 |
20100146168 | System and method of inter-connection between components using software bus - A method for inter-connection between components using a software bus, which may analyze whether a port in which at least one component is connected with each other is a data transmission port or a function interface calling port in accordance with an application of the port, determine an execution attribute of the port based on an analyzed result, and control the port in accordance with the execution attribute of the port. The function interface calling port may be divided into any one of a thread generation-connection port for each request using an attribute of an on-demand function calling port, or a recursive server connection port using an attribute of an on load function calling port in accordance with a type of the called port. | 06-10-2010 |
20100281489 | Method and system for dynamically parallelizing application program - Provided is a method and system for dynamically parallelizing an application program. Specifically, provided is a method and system having multi-core control that may verify a number of available threads according to an application program and dynamically parallelize data based on the verified number of available threads. The method and system for dynamically parallelizing the application program may divide a data block to be processed according to the application program based on a relevant data characteristic and dynamically map the threads to division blocks, and thereby enhance a system performance. | 11-04-2010 |
20100312977 | Method of managing memory in multiprocessor system on chip - Provided is a method of managing memory in a multiprocessor system on chip (MPSoC). According to an aspect of the present invention, locality of memory can be reflected and restricted memory resources can be efficiently used by determining a storage location of a variable or a function which corresponds to a symbol with reference to a symbol table based on memory access frequency of the variable or the function, comparing the determined storage location and a previous storage location, and copying the variable or the function stored in the previous storage location to the determined storage location if the determined storage location is different from the previous storage location. | 12-09-2010 |
20110016285 | Apparatus and method for scratch pad memory management - Disclosed is a scratch pad memory management device and a method thereof. The scratch pad memory management device divides a scratch pad memory into a plurality of unit blocks, maintains a memory allocation table corresponding to indices of the plurality of unit blocks in a main memory, and manages the scratch pad memory. | 01-20-2011 |
20110072231 | Device, method and computer-readable medium relocating remote procedure call data in heterogeneous multiprocessor system on chip - Disclosed is a device, method and computer-readable medium relocating Remote Procedure Call (RPC) data in a heterogeneous multiprocessor System-on-Chip (MPSoC). The method, for example, includes determining a memory where data is to be stored based on a use of a parameter of a function, and data access patterns of a function caller and a function callee, and storing the data in the determined memory. | 03-24-2011 |
20110119463 | COMPUTING SYSTEM AND METHOD CONTROLLING MEMORY OF COMPUTING SYSTEM - Provided is a computing system having a hierarchical memory structure. When a data structure is allocated with respect to a task processed in the computing system, the data structure is divided and a portion of the data structure is allocated to a high speed memory of the hierarchical memory structure and a remaining data structure is allocated to a low speed memory of the hierarchical memory. | 05-19-2011 |
20110119656 | Computing system, method and computer-readable medium processing debug information in computing system - Disclosed are a system, method and computer-readable medium related to processing debug information from an embedded system. Source code of an application program to be used in an embedded system may be compiled by a computing system. The application program may include a debug code line. A minimum amount of debug information is stored in an embedded system, reducing memory overhead and waste of clock cycles of a processor. | 05-19-2011 |
20110167427 | COMPUTING SYSTEM, METHOD AND COMPUTER-READABLE MEDIUM PREVENTING STARVATION - A computing system, method and computer-readable medium is provided. To prevent a starvation phenomenon from occurring in a priority-based task scheduling, a plurality of tasks may be divided into a priority-based group and other groups. The groups to which the tasks belong may be changed. | 07-07-2011 |
20110173622 | System and method for dynamic task migration on multiprocessor system - A multiprocessor system and a migration method of the multiprocessor system are provided. The multiprocessor system may process dynamic data and static data of a task to be operated in another memory or another processor without converting pointers, in a distributed memory environment and in a multiprocessor environment having a local memory, so that dynamic task migration may be realized. | 07-14-2011 |
20110173633 | Task migration system and method thereof - A task migration system is provided which transmits a migration request signal for a plurality of first tasks to a migration manager using a resource manager, transmits information used in response to the migration request signal from a migration initiation handler to the migration manager when a first task, of which a migration point is in a capture ready state, among the plurality of first tasks is received from a processor, and captures, using the migration manager, the migration point of the first task in the capture ready state, in response to a migration request signal for the first task in the capture ready state, so that the first task with the captured migration point migrates to a second task. | 07-14-2011 |
20110231856 | System and method for dynamically managing tasks for data parallel processing on multi-core system - A dynamic task management system and method for data parallel processing on a multi-core system are provided. The dynamic task management system may generate a registration signal for a task to be parallel processed, may generate a dynamic management signal used to dynamically manage at least one task, in response to the generated registration signal, and may control the at least one task to be created or cancelled in at least one core in response to the generated dynamic management signal. | 09-22-2011 |
20110252258 | HARDWARE ACCELERATION APPARATUS, METHOD AND COMPUTER-READABLE MEDIUM EFFICIENTLY PROCESSING MULTI-CORE SYNCHRONIZATION - Provided is a hardware acceleration apparatus, method and computer-readable medium efficiently processing multi-core synchronization. A processor core that fails to acquire a lock variable may be switched to a low power sleep mode and a waste of power may be reduced. Additionally, when a lock variable is returned, a wakeup signal may be transmitted to a processor core operated in the low power sleep mode, and the processor core may be activated. | 10-13-2011 |
20120005679 | APPARATUS AND METHOD FOR THREAD PROGRESS TRACKING USING DETERMINISTIC PROGRESS INDEX - Provided is a method and apparatus for measuring a performance or a progress state of an application program to perform data processing and execute particular functions in a computing environment using a micro architecture. A thread progress tracking apparatus may include a selector to select at least one thread constituting an application program; a determination unit to determine, based on a predetermined criterion, whether an instruction execution scheme corresponds to a deterministic execution scheme having a regular cycle or a nondeterministic execution scheme having an irregular delay cycle with respect to each of at least one instruction constituting a corresponding thread; and a deterministic progress counter to generate a deterministic progress index with respect to an instruction that is executed by the deterministic execution scheme, excluding an instruction that is executed by the nondeterministic execution scheme. | 01-05-2012 |
20120023505 | APPARATUS AND METHOD FOR THREAD SCHEDULING AND LOCK ACQUISITION ORDER CONTROL BASED ON DETERMINISTIC PROGRESS INDEX - Provided is a method and apparatus for ensuring a deterministic execution characteristic of an application program to perform data processing and execute particular functions in a computing environment using a micro architecture. A lock controlling apparatus based on a deterministic progress index (DPI) may include a loading unit to load a DPI of a first core and a DPI of a second core among DPIs of a plurality of cores at a lock acquisition point in time of each thread, a comparison unit to compare the DPI of the first core and the DPI of the second core, and a controller to assign a lock to a thread of the first core when the DPI of the first core is less than the DPI of the second core and when the second core corresponds to a last core to be compared among the plurality of cores. | 01-26-2012 |
20120159428 | METHOD OF DETERMINING MULTIMEDIA ARCHITECTURAL PATTERN, AND APPARATUS AND METHOD FOR TRANSFORMING SINGLE-CORE BASED ARCHITECTURE TO MULTI-CORE BASED ARCHITECTURE - A method and apparatus for authoring an architecture for transforming a single-core based embedded software application to a multi-core based embedded software application, and a method of determining an architectural pattern in a multimedia system. It is possible to perform an architecture authoring operation by using an architectural decision supporter, without prior knowledge and accumulated knowledge regarding a software architecture. Additionally, it is possible to prevent an error from occurring during authoring of an architecture, by using a concurrency-related software architectural pattern that is already evaluated. Thus, it is possible to improve overall quality of software, and to reduce a development time. | 06-21-2012 |
20120198206 | APPARATUS AND METHOD FOR PROTECTING MEMORY IN MULTI-PROCESSOR SYSTEM - Memory mapping in small units using a segment and subsegments is described, and thus it is possible to control a memory access even using a small amount of hardware, and it is possible to reduce costs incurred by hardware. Additionally, it is possible to prevent a memory from being destroyed due to a task error in the multi-processor system. | 08-02-2012 |
20130097613 | APPARTUS AND METHOD FOR THREAD PROGRESS TRACKING - Provided is a method and apparatus for measuring a progress or a performance of an application program in a computing environment using a micro-architecture. An apparatus for thread progress tracking may select a thread included in an application program, may determine, based on a predetermined criterion, whether an execution scheme for at least one instruction included in the thread corresponds to an effective execution scheme in which an execution time is uniform or a non-effective execution scheme in which a delayed cycle is included and the execution time is non-uniform, and may generate an effective progress index (EPI) by accumulating an execution time of an instruction executed by the effective execution scheme other than an instruction executed by the non-effective execution scheme. | 04-18-2013 |
20130111472 | VIRTUAL ARCHITECTURE GENERATING APPARATUS AND METHOD, AND RUNTIME SYSTEM, MULTI-CORE SYSTEM AND METHODS OF OPERATING RUNTIME SYSTEM AND MULTI-CORE SYSTEM | 05-02-2013 |
20130179674 | APPARATUS AND METHOD FOR DYNAMICALLY RECONFIGURING OPERATING SYSTEM (OS) FOR MANYCORE SYSTEM - An apparatus and method for dynamically reconfiguring an Operating System (OS) for a manycore system are provided. The apparatus may include an application type determining unit to determine a type of an executed application, and an OS reconfiguring unit to activate only at least one function in an OS, based on the determined type of the application, and to reconfigure the OS. | 07-11-2013 |
20130205298 | APPARATUS AND METHOD FOR MEMORY OVERLAY - A memory overlay apparatus includes an internal memory that includes a dirty bit indicating a changed memory area, a memory management unit that controls an external memory to store only changed data so that only data actually being used by a task during overlay is stored and restored, and a direct memory access (DMA) management unit that confirms the dirty bit when the task is changed and that moves a data area of the task between the internal memory and the external memory. | 08-08-2013 |
20130247065 | APPARATUS AND METHOD FOR EXECUTING MULTI-OPERATING SYSTEMS - An apparatus and method for executing multi-operating systems (OS) are provided. Resources allocated to the respective multi-OSs are managed by management applications of the multi-OSs. A processor executes a plurality of multi-OSs. Each of the plurality of multi-OSs executes the management application. Each of the plurality of multi-OSs regards a resource held by another multi-OS among the plurality of multi-OSs as used by the corresponding management application, thereby preventing the resource from being allocated to another application included in the multi-OS. | 09-19-2013 |
20130312003 | METHOD AND SYSTEM FOR DYNAMICALLY PARALLELIZING APPLICATION PROGRAM - Provided is a method and system for dynamically parallelizing an application program. Specifically, provided is a method and system having multi-core control that may verify a number of available threads according to an application program and dynamically parallelize data based on the verified number of available threads. The method and system for dynamically parallelizing the application program may divide a data block to be processed according to the application program based on a relevant data characteristic and dynamically map the threads to division blocks, and thereby enhance a system performance. | 11-21-2013 |
20140019782 | APPARATUS AND METHOD FOR MANAGING POWER BASED ON DATA - Provided is an apparatus and method for managing power based on data. The apparatus may include a code segment searching unit configured to search for at least one code segment in which a power type is inserted, a block determining unit configured to determine at least one block based on the at least one found code segment, and a power mode control unit configured to control the at least one determined block to operate in a power mode corresponding to the power type. | 01-16-2014 |
20140032976 | APPARATUS AND METHOD FOR DETECTING ERROR - An apparatus and method for detecting an error occurring when an application program is executed in a computer environment is provided. The error detection apparatus may measure a deterministic progress index (DPI) and a program counter (PC) value when an instruction is executed, set, as a verification set, a DPI and a PC value measured when the instruction is executed without causing an error, set, as a measurement set, the DPI and the PC value measured when an instruction is executed, and detect a runtime error of the instruction by comparing the measurement set to the verification set. | 01-30-2014 |
20140104271 | APPARATUS AND METHOD FOR IMAGE PROCESSING - A method for processing a three-dimensional (3D) image of a ray tracing scheme may be performed by an image processing apparatus by verifying whether local index information matching intersection point information of a ray is present within a prefetch table when intersection point information is received, and by transferring, to a shader, rendering information stored in a local memory based on the local index information, when the local index information matching the intersection point information is present. | 04-17-2014 |
20140160125 | APPARATUS AND METHOD FOR RENDERING BEZIER CURVE - An apparatus and method for rendering a tile-binned Bezier curve may include a rendering calculator to determine a rendering scheme for at least one tile, with respect to the tile-binned Bezier curve, and a rendering processor to perform rendering with respect to a Bezier curve for the at least one tile, based on the determined rendering scheme. The rendering calculator may suspend the rendering of the Bezier curve at a boundary point between the at least one tile and an adjacent tile while the rendering is being performed, and determine the rendering scheme for a boundary value in which a position of the boundary point is reflected to be used when the adjacent tile is rendered. | 06-12-2014 |
20140344602 | APPARATUS AND METHOD MANAGING POWER BASED ON DATA - A processing apparatus for managing power based on data is provided. The processing apparatus may obtain, in response to an access request from a processor for particular data stored in a memory, existing power information having a predefined correspondence to the particular data, and control a power mode of the processor based on the existing power information. | 11-20-2014 |