Patent application number | Description | Published |
20090104557 | NEGATIVE IMAGING METHOD FOR PROVIDING A PATTERNED METAL LAYER HAVING HIGH CONDUCTIVITY - Disclosed is a method negative imaging method for making a metal pattern with high conductivity comprising providing a patterned substrate comprising a patterned catalyst layer on a base substrate by a thermal imaging method followed by plating to provide the metal pattern. The metal patterns provided are suitable for electrical devices including electromagnetic interference shielding devices and touchpad sensors. | 04-23-2009 |
20090179198 | THIN FILM TRANSISTOR COMPRISING NOVEL CONDUCTOR AND DIELECTRIC COMPOSITIONS - The invention relates to thin film transistors comprising novel dielectric layers and novel electrodes comprising metal compositions that can be provided by a dry thermal transfer process. | 07-16-2009 |
20100239793 | Thermally imageable dielectric layers, thermal transfer donors and receivers - The invention is related to thermal imageable dielectric layers and thermal transfer donors and receivers comprising dielectric layers. The thermal transfer donors are useful in making electronic devices by thermal transfer of dielectric layers having excellent resistivity, good transfer properties and good adhesion to a variety of receivers. | 09-23-2010 |
20100239794 | Donor elements and processes for thermal transfer of nanoparticle layers - The invention discloses processes for thermal transfer patterning of a nanoparticle layer and a corresponding proximate portion of a carrier layer, and optionally additional transfer layers, together onto a thermal imaging receiver. The invention is useful for dry fabrication of electronic devices. Additional embodiments of the invention include multilayer thermal imaging donors comprising in layered sequence: a base film, a carrier layer and a nanoparticle layer. The carrier layer can be a dielectric or conducting layer. When the carrier layer is a dielectric layer, the base film includes a light attenuating agent in the form of a dye or pigment. | 09-23-2010 |
20120251802 | THERMALLY IMAGEABLE DIELECTRIC LAYERS, THERMAL TRANSFER DONORS AND RECEIVERS - The invention is related to thermal imageable dielectric layers and thermal transfer donors and receivers comprising dielectric layers. The thermal transfer donors are useful in making electronic devices by thermal transfer of dielectric layers having excellent resistivity, good transfer properties and good adhesion to a variety of receivers. | 10-04-2012 |
Patent application number | Description | Published |
20120205478 | RETRACTING LIFELINE SYSTEMS FOR USE IN TIE-BACK ANCHORING - A retracting lifeline system, includes: a housing, a first connector attached to the housing, a lifeline, and a hub to which the lifeline is attached at a first end of the lifeline and around which the lifeline is coiled within the housing. The housing includes an opening through which the lifeline exits the housing. The hub is tensioned to rotate in a first direction to cause retracting of the lifeline and coiling of the lifeline around the hub. The retracting lifeline system further includes a second connector attached to a second end of the lifeline. At least a section of the lifeline has an initial ultimate tensile load of at least 8000 pounds and is abrasion resistant (that is, satisfying the abrasion test requirement set forth in the ANSI/ASSE Z359.13-2009 standard) such that the section of the lifeline is available for tie-back anchoring using the second connector. The section of the lifeline is at least partially retractable within the housing. | 08-16-2012 |
20140060969 | Fall Protection Safety Harness - Apparatus and associated methods relate to a fall-protection safety harness having padding structures located at harness pressure points, including dorsal and shoulder regions, the lumbar region, and leg regions. The padding structures may be constructed to provide air-flow parallel to a wearer's skin. Air may flow through wearer-webbing channels created by displacing a webbing via comfort pads. For example, the padding structures may be made by sandwiching foam pads between mesh fabric materials. The foam pads may be captured by the two mesh fabrics using circumferential stitching, for example. Circumferential stitching may permit the foam to retain its uncompressed form which may facilitate webbing displacement. Separate and symmetric pads may be located on both sides of a wearer's spine, both at the lumbar region and at the dorsal region of the back, permitting airflow between pads and along the wearer's spine. | 03-06-2014 |
Patent application number | Description | Published |
20090230255 | CAB SIGNAL RECEIVER DEMODULATOR EMPLOYING REDUNDANT, DIVERSE FIELD PROGRAMMABLE GATE ARRAYS - A processor includes a first field programmable gate array (FPGA) having a first central processing unit (CPU) core programmed to perform a first function, and first programmable hardware logics (PHLs) programmed to perform a second function. A second FPGA includes a second CPU core programmed to perform a third function, and second PHLs programmed to perform a fourth function. A communication interface is between the first and second CPU cores. The first and second FPGAs are diverse. A portion of the first function communicates first information from the first CPU core to the second CPU core through the interface. A portion of the third function communicates second information from the second CPU core to the first CPU core through the interface, and, otherwise, the first function is substantially the same as the third function. The second function is substantially the same as the fourth function. | 09-17-2009 |
20110090714 | OUTPUT APPARATUS TO OUTPUT A VITAL OUTPUT FROM TWO SOURCES - An output apparatus includes a first source of a first signal having a first state or a different second state; a second source of a second signal having a first state or a different second state; and a circuit structured to output a vital output including a first state when the first state of the first signal corresponds to the first state of the second signal and, otherwise, including a different second state. At least one of the first signal and the second signal is a static signal. The other one of the first signal having the first state and the second signal having the first state is a dynamic signal. When at least one of the first signal has the different second state of the first signal and the second signal has the different second state of the second signal, the vital output includes the different second state. | 04-21-2011 |
20110093767 | SYSTEM AND METHOD TO SERIALLY TRANSMIT VITAL DATA FROM TWO PROCESSORS - A system for serially transmitting vital data includes first and second processors to determine first and second data, a serial communication apparatus to input third data and output serial data based upon the third data, and a memory having first and second ports accessible by the first and second processors, a first memory writable by the first processor and readable by the second processor, and a second memory writable by the second processor and readable by the first processor. The first and second processors store the first and second data in the first and second memories, cooperatively agree that the first data corresponds to the second data, and responsively cause the apparatus to employ: one of the first and second data as the third data, or parts of the first and second data as the third data, and output the serial data based upon the third data. | 04-21-2011 |
20120260046 | PROGRAMMABLE LOGIC APPARATUS EMPLOYING SHARED MEMORY, VITAL PROCESSOR AND NON-VITAL COMMUNICATIONS PROCESSOR, AND SYSTEM INCLUDING THE SAME - A programmable logic apparatus includes a shared memory having a first port, a second port and a third port; a first vital processor interfaced to the first port of the shared memory; and a non-vital communications processor separated from the first vital processor in the programmable logic apparatus and interfaced to the second port of the shared memory. The third port of the shared memory is an external port structured to interface an external second vital processor. | 10-11-2012 |