Patent application number | Description | Published |
20080203400 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device and a method of manufacturing the device using a (000-1)-faced silicon carbide substrate are provided. A SiC semiconductor device having a high blocking voltage and high channel mobility is manufactured by optimizing the heat-treatment method used following the gate oxidation. The method of manufacturing a semiconductor device includes the steps of forming a gate insulation layer on a semiconductor region formed of silicon carbide having a (000-1) face orientation, forming a gate electrode on the gate insulation layer, forming an electrode on the semiconductor region, cleaning the semiconductor region surface. The gate insulation layer is formed in an atmosphere containing 1% or more H | 08-28-2008 |
20110121316 | SILICON CARBIDE SEMICONDUCTOR DEVICE - The area of each body region is minimized, and the gate oxide films at the bottoms of the trenches are more effectively protected by depletion layers extending from the body regions. | 05-26-2011 |
20140113421 | SILICON CARBIDE SEMICONDUCTOR APPARATUS AND METHOD OF MANUFACTURING SAME - A silicon carbide vertical MOSFET having low ON-resistance and high blocking voltage is provided. For this, a first deposition film ( | 04-24-2014 |
20150053998 | SEMICONDUCTOR DEVICE - A base layer is used that has an N-type SiC layer formed in a surface layer on the front surface side of an N-type SiC substrate, and a P-type region is formed on a surface of the N-type SiC layer with an N-type source region selectively formed in a surface layer of the P-type region. A source electrode is formed on a surface of the N-type source region and a drain electrode is formed on the back surface side of the N-type SiC substrate. Additionally, the gate electrode is formed via a gate insulation film only on a surface of the P-type region. In this way, high electric field is no longer applied to the gate insulation film on the surface of the N-type SiC layer due to stoppage of voltage application to the gate electrode. | 02-26-2015 |
20150069415 | SEMICONDUCTOR DEVICE - An n-type SiC layer is formed on a front face of an n | 03-12-2015 |
20150076519 | VERTICAL HIGH VOLTAGE SEMICONDUCTOR APPARATUS AND FABRICATION METHOD OF VERTICAL HIGH VOLTAGE SEMICONDUCTOR APPARATUS - A silicon carbide vertical MOSFET includes an N-counter layer of a first conductivity type formed in a surface layer other than a second semiconductor layer base layer selectively formed in a low concentration layer on a surface of the substrate, a gate electrode layer formed through a gate insulating film in at least a portion of an exposed portion of a surface of a third semiconductor layer of a second conductivity type between a source region of the first conductivity type and the N-counter layer of the first conductivity type, and a source electrode in contact commonly with surfaces of the source region and the third semiconductor layer. Portions of the second conductivity type semiconductor layer are connected with each other in a region beneath the N-counter layer. | 03-19-2015 |
20150076521 | VERTICAL HIGH-VOLTAGE SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - To provide a vertical SIC-MOSFET and IGBT capable of having low ON-resistance without destruction of gate oxide films or degradation of reliability even when a high voltage is applied, and a fabrication method thereof, a vertical mosfet has a semiconductor layer and a base layer joined instead of a well region | 03-19-2015 |
20150102363 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A silicon carbide semiconductor device has a first-conductivity-type semiconductor layer having a lower impurity concentration and formed on a first-conductivity-type semiconductor substrate, a second-conductivity-type semiconductor layer having a higher impurity concentration and selectively formed in the first-conductivity-type semiconductor layer, a second-conductivity-type base layer having a lower impurity concentration formed on a surface of the second-conductivity-type semiconductor layer, a first-conductivity-type source region selectively formed in a surface layer of the base layer, a first-conductivity-type well region formed to penetrate the base layer from a surface to the first-conductivity-type semiconductor layer, and a gate electrode formed via a gate insulation film on a surface of the base layer interposed between the source region and the well region. Portions of the respective second-conductivity-type semiconductor layers of different cells can be connected to each other by a connecting portion in a region under the well region. | 04-16-2015 |