Patent application number | Description | Published |
20080286904 | Method for manufacturing semiconductor package - Provided is a method for manufacturing a semiconductor package. In the method, a wafer for a cap substrate is provided. The wafer for the cap substrate includes a plurality of vias and via electrodes on a lower surface. A wafer for a device substrate is provided. The wafer for the device substrate includes a circuit unit and a connection electrode on an upper surface. The wafer for the cap substrate and the wafer for the device substrate are primarily bonded by a medium of a primary adhesive. A trench is formed to expose the upper surface of the wafer for the device substrate to an outside along an outer edge of the primary adhesive. A secondary bonding operation is performed by a medium of a secondary adhesive to electrically connect the via electrode and the connection electrode. The wafer for the device substrate is diced along a virtual cut line. | 11-20-2008 |
20080299706 | Wafer level package fabrication method - Provided is a wafer level package fabrication method. The method includes providing a device substrate wafer including one or more devices on an upper surface thereof, and a bonding pad electrically connected to the device, providing a bonding seal surrounding the device along the bonding pad, bonding a cap substrate wafer to the device substrate wafer through the bonding seal, the cap substrate wafer having a via formed in a region corresponding to the bonding pad, forming an external terminal on the cap substrate wafer, the external terminal being electrically connected to the bonding pad, and cutting the cap substrate wafer and the device substrate wafer along a cutting line to individually separate a plurality of wafer level packages. The method is conducive to reducing product size for miniaturization, is capable of performing a bonding process without wafer deformation or damage, and increases freedom in wafer material selection. | 12-04-2008 |
20090085134 | Wafer-level image sensor module, method of manufacturing the same, and camera module - Provided is a wafer-level image sensor module including a wafer; an image sensor mounted on the wafer; a transparent member installed above the top surface of the wafer so as to seal the image sensor; a plurality of vias formed in the wafer so as to be positioned outside the transparent member; a plurality of upper pads formed on the upper ends of the respective vias; an encapsulation portion formed on the top surface of the wafer so as to be positioned outside the transparent member; and a plurality of external connection members that are electrically connected to the lower ends of the respective vias. | 04-02-2009 |
20110012220 | Wafer-level image sensor module, method of manufacturing the same and camera module - A wafer-level image sensor module including: a wafer having an image sensor and a plurality of upper pads provided thereon, the wafer having an inclined surface on either side thereof; a transparent member installed above the top surface of the wafer so as to seal the image sensor; a plurality of lead portions having one ends connected to the respective upper pads, the lead portions being formed to extend to the bottom surface of the wafer along the inclined surface of the wafer; an encapsulation portion formed on the top surface of the wafer so as to be positioned outside the transparent member; and a plurality of external connection members that are electrically connected to the other ends of the respective lead portions | 01-20-2011 |
20140029201 | POWER PACKAGE MODULE AND MANUFACTURING METHOD THEREOF - There is provided a power package module, including: a lead frame; at least one first electronic component mounted on the lead frame; and an insulating member disposed on a first surface of the first electronic component and having a via electrode connected to the first electronic component. | 01-30-2014 |
20140035157 | SEMICONDUCTOR PACKAGE, MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR PACKAGE MANUFACTURING MOLD - There is provided a semiconductor package including: at least one internal lead having at least one electronic component mounted on a surface thereof; a molding unit sealing the electronic component and the internal lead; at least one external lead extending from the internal lead and protruding outwardly from ends of the molding unit; and a stopper provided on the external lead. | 02-06-2014 |
20140110833 | POWER MODULE PACKAGE - Disclosed herein is a power module package. The power module package includes a substrate having one surface formed with a circuit pattern including a chip mounting pad and an external connection pad and the other surface; a semiconductor chip mounted on the chip mounting pad; and an external connection terminal having one terminal and the other terminal, the one terminal being connected to the external connection pad and the other terminal protruding to the outside, in which the external connection pad and the external connection terminal are bonded to each other by welding. | 04-24-2014 |
20140118956 | ALL-IN-ONE POWER SEMICONDUCTOR MODULE - Disclosed herein is an all-in-one power semiconductor module including a plurality of first semiconductor devices formed on a substrate; a housing molded and formed to include bridges formed across upper portions of the plurality of first semiconductor devices; and a plurality of lead members integrally formed with the housing and electrically connecting the plurality of first semiconductor devices and the substrate. | 05-01-2014 |
20140183717 | SEMICONDUCTOR MODULE PACKAGE - Disclosed herein is a semiconductor module package, including: a first module including a first heat radiation substrate and one or more first semiconductor elements and having a first N terminal and a first P terminal formed at one end thereof; a second module including a second heat radiation substrate and one or more second semiconductor elements, having a second N terminal and a second P terminal formed at one end thereof, and disposed so as to face the first module; and a first output terminal formed by electrically connecting the first module to the second module. | 07-03-2014 |