Sravan Kumar
Sravan Kumar Ambapuram, Hyderabad IN
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20150261583 | SYSTEM AND METHOD FOR PROVIDING DYNAMIC CLOCK AND VOLTAGE SCALING (DCVS) AWARE INTERPROCESSOR COMMUNICATION - Systems and methods that allow for Dynamic Clock and Voltage Scaling (DCVS) aware interprocessor communications among processors such as those used in or with a portable computing device (“PCD”) are presented. During operation of the PCD at least one data packet is received at a first processing component. Additionally, the first processing component also receives workload information about a second processing component operating under dynamic clock and voltage scaling (DCVS). A determination is made, based at least in part on the received workload information, whether to send the at least one data packet from the first processing component to the second processing component or to a buffer, providing a cost effective ability to reduce power consumption and improved battery life in PCDs with multi-cores or multi-CPUs implementing DCVS algorithms or logic. | 09-17-2015 |
20150277536 | Apparatus, System and Method for Dynamic Power Management Across Heterogeneous Processors in a Shared Power Domain - Systems and methods for dynamically adjusting an input parameter to a power domain in a portable computing device are disclosed. The power domain includes two or more processing resources that share a power source. Dynamic use of the two or more processing resources creates an opportunity to adjust the input parameter when a status change associated with a processing resource in the power domain occurs. A controller in the power domain includes logic that responds to a status indicator associated with a respective processing resource in the power domain by generating a control signal that directs a device to adjust one or both of input voltage and clock frequency. | 10-01-2015 |
20150309552 | ENHANCEMENT IN LINUX ONDEMAND GOVERNOR FOR PERIODIC LOADS - An enhanced OnDemand Governor is disclosed that computes a steady-state frequency based on prior recommended CPU frequencies and applies a steady-state frequency when available. When not available, a turbo frequency or a computed lower frequency is applied. For increased loads, the steady-state frequency can be applied for one or more cycles until it becomes apparent that gradual frequency increases are not sufficient to meet a large CPU load, at which point the turbo frequency is applied and the history of CPU frequencies can be flushed. The enhanced OnDemand Governor can be turned on where periodic loads are detected while the traditional OnDemand Governor can be used in all other use cases. | 10-29-2015 |
20150323975 | SYNCHRONIZATION OF ACTIVITY OF MULTIPLE SUBSYSTEMS IN A SoC TO SAVE STATIC POWER - The present disclosure relates to synchronization and parallel operation of two or more cores within a multi-core computing system so as to reduce an amount of time that all cores are operating during a processing period and thereby increase an amount of idle time per processing period. In this way deeper sleep and/or idle states for the cores and the system can be entered. | 11-12-2015 |
20160062438 | SYSTEM AND METHOD FOR PROVIDING DYNAMIC QUALITY OF SERVICE LEVELS BASED ON COPROCESSOR OPERATION - Systems and methods that allow for dynamic quality of service (QoS) levels for an application processor in a multi-core on-chip system (SoC) in a portable computing device (PCD) are presented. During operation of the PCD an operational load of a co-processor of the SoC is determined, where the co-processor is in communication with an application processor of the SoC. Based on the determined load, the co-processor determines a QoS level required from the application processor. The QoS level is communicated to the application processor. The application processor determines whether it can implement power optimization measures, such as entering into a low power mode (LPM), based at least in part on the dynamically communicated QoS level from the co-processor. The present disclosure provides a cost effective ability to reduce power consumption in PCDs implementing one or more cores or CPUs that are dependent upon the application processor. | 03-03-2016 |
20160119874 | DETECTION OF SPURIOUS TCP CONTROL PACKETS - Systems and methods for managing communications on a communication device are disclosed. A method may include receiving a communication packet at the communication device via a network connection and determining, at the communication device, whether the communication packet is an unsolicited control packet. Dormancy of the network connection is triggered after a first time period if the communication packet is not an unsolicited control packet, and dormancy of the network connection is triggered after a second time period if the communication packet is an unsolicited control packet wherein the second time period is less than the first time period. | 04-28-2016 |
20160124778 | SYSTEM AND METHOD FOR PROVIDING DYNAMIC CLOCK AND VOLTAGE SCALING (DCVS) AWARE INTERPROCESSOR COMMUNICATION - Systems and methods that allow for Dynamic Clock and Voltage Scaling (DCVS) aware interprocessor communications among processors such as those used in or with a portable computing device (“PCD”) are presented. During operation of the PCD at least one data packet is received at a first processing component. Additionally, the first processing component also receives workload information about a second processing component operating under dynamic clock and voltage scaling (DCVS). A determination is made, based at least in part on the received workload information, whether to send the at least one data packet from the first processing component to the second processing component or to a buffer, providing a cost effective ability to reduce power consumption and improved battery life in PCDs with multi-cores or multi-CPUs implementing DCVS algorithms or logic. | 05-05-2016 |
Sravan Kumar Ambapuram, Hyderabad, IN US
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20150370316 | APPARATUS, SYSTEM AND METHOD FOR DYNAMIC POWER MANAGEMENT ACROSS HETEROGENEOUS PROCESSORS IN A SHARED POWER DOMAIN - Systems and methods for dynamically adjusting an input parameter, such as power supply level, to a shared power domain in a portable computing device are disclosed. The power domain includes a plurality of processing resources that share the power source. The power supply level is reduced based on a critical core vote pool derived from votes from the plurality of processing resources. The critical core vote pool is narrowed from all the votes by disqualifying votes based on the operating status of the associated processing resources. For example, because inactive processing resources may be unaffected by a change in the voltage level to the shared domain, and because certain active processing resources are in a position to adjust to a power change dictated by another processing resource, such processing resources may be considered noncritical and their votes disqualified from consideration. | 12-24-2015 |
Sravan Kumar Andavarapu, Jeypore IN
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20140201240 | SYSTEM AND METHOD TO RETRIEVE RELEVANT MULTIMEDIA CONTENT FOR A TRENDING TOPIC - A system for identifying one or more multimedia content relevant to a trending topic is provided. The system includes a display unit, a memory unit that stores a set of modules and a database, and a processor that executes the set of modules. The set of modules include a query processing module, a content extracting module, a context extracting module, and a multimedia content identifying module. The query processing module processes a user input including a search query. The content extracting module extracts content which corresponds to the search query from a social medium. The context extracting module includes a) a keyword generating module obtains one or more generated keywords from the content, and b) a keyword qualifying module obtains one or more keywords from the one or more generated keywords. The multimedia content identifying module identifies the one or more multimedia content based on the one or more keywords. | 07-17-2014 |
Sravan Kumar Bhaskarani, Bhadravathi IN
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20110234253 | INTEGRATED CIRCUIT DIE TESTING APPARATUS AND METHODS - A wafer is disclosed that includes a plurality of pipeline interconnected integrated circuit dies that form a plurality of pipelines. A plurality of dies in each pipeline is connected to receive scanned output test data from a neighboring die in a pipeline. A wafer level test access mechanism (TAM) transceiver circuitry, located outside the plurality of pipeline interconnected IC dies, is connected in common to each of the pipelines to provide input test data in a parallel fashion to the plurality of pipelines. The wafer level test access mechanism transceiver circuitry also provides output test results from each of the pipelines for evaluation by a computerized test system. In one embodiment, the wafer level test access mechanism transceiver circuitry is wireless so that it wirelessly receives test data to be passed through the multiple pipelines on a wafer and also includes wireless transmit circuitry to transmit test results from each of the pipelines. When on the wafer, the dies in a pipeline are interconnected with pipeline die test interconnection paths that provide pipeline test information interconnection among the plurality of dies in the pipeline. | 09-29-2011 |
Sravan Kumar Bhaskarani, Kamataka IN
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20120198291 | LOCALLY SYNCHRONOUS SHARED BIST ARCHITECTURE FOR TESTING EMBEDDED MEMORIES WITH ASYNCHRONOUS INTERFACES - A system and method of sharing testing components for multiple embedded memories and the memory system incorporating the same. The memory system includes multiple test controllers, multiple interface devices, a main controller, and a serial interface. The main controller is used for initializing testing of each of the dissimilar memory groups using a serial interface and local test controllers. The memory system results in reduced routing congestion and faster testing of plurality of dissimilar memories. The present disclosure further provides a programmable shared built in self testing (BIST) architecture utilizing globally asynchronous and locally synchronous (GALS) methodology for testing multiple memories. The built in self test (BIST) architecture includes a programmable master controller, multiple memory wrappers, and an interface. The interface can be a globally asynchronous and locally synchronous (GALS) interface. | 08-02-2012 |
Sravan Kumar Elineni, Tampa, FL US
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20130085632 | Hands-free user interface devices - In one embodiment, a hands-free user interface device includes a first plate, a second plate spaced from the first plate, a sensor associated with the plates adapted to detect when the first plate pivots relative to the second plate, and a controller adapted to receive signals from the sensor and output control signals to another component based upon the received signals. | 04-04-2013 |
Sravan Kumar Elpula, Santa Clara, CA US
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20160140003 | NON-DISRUPTIVE CONTROLLER REPLACEMENT IN A CROSS-CLUSTER REDUNDANCY CONFIGURATION - During a storage redundancy giveback from a first node to a second node following a storage redundancy takeover from the second node by the first node, the second node is initialized in part by receiving a node identification indicator from the second node. The node identification indicator is included in a node advertisement message sent by the second node during a giveback wait phase of the storage redundancy giveback. The node identification indicator includes an intra-cluster node connectivity identifier that is used by the first node to determine whether the second node is an intra-cluster takeover partner. In response to determining that the second node is an intra-cluster takeover partner, the first node completes the giveback of storage resources to the second node. | 05-19-2016 |
Sravan Kumar Rondla, Hyderabad IN
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20130305321 | METHODS FOR CONFIRMING USER INTERACTION IN RESPONSE TO A REQUEST FOR A COMPUTER PROVIDED SERVICE AND DEVICES THEREOF - A method, non-transitory computer readable medium, and access manager device includes providing an initial challenge to a client computing device requesting access to a service. The initial challenge includes one or more of one or more objects, one or more indicative answers, and one or more questions based on the one or more objects. At least one challenge response to the initial challenge is received from the client computing device. A determination is when there is a match between the at least one challenge response to the initial challenge and corresponding response data associated with the initial challenge. One or more actions with respect to the request to access the service are performed based on the determination. | 11-14-2013 |
20150180835 | SYSTEM AND METHOD FOR VERIFYING INTEGRITY OF CLOUD DATA USING UNCONNECTED TRUSTED DEVICE - The present invention provides a method and system for verifying integrity of cloud data using unconnected trusted device. The method involves requesting encrypted data though a terminal from a metadata offsite location on a cloud storage then entering encrypted data into an unconnected trusted device thereafter obtaining sentinel data from one or more predefined sentinel locations in encrypted data then requesting original data from the cloud storage through the terminal from the unconnected trusted device thereafter comparing sentinel data and original data for integrity and finally displaying the results. | 06-25-2015 |