Steigerwald, US
Charles D. Steigerwald, Apple Valley, MN US
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20080281969 | Controlling access to versions of application software by a server, based on site ID - A plurality of versions of software application programs can be handled by a single server serving multiple user-clients who each need access to specific ones of the plurality of versions. Thus such different versions can run simultaneously without requiring upgrading of early versions and no interference between versions. A particular version is given a SiteID that a user request calls, and a table in the server is consulted to keep track of which SiteID corresponds to which version and to assign each request to the appropriate version. A directory or registry must be set up to accommodate the table which must be consulted for each request. No significant change need be made in any version of the software application program since the table is created at installation time on the server and the SiteID's are assigned to the users when they get rights to the particular version of interest by an administrator. In a preferred embodiment, a SiteID identifies (and the “site” embodies) a collection of databases that the user may need access to. One and only one application software version is associated with a SiteID. Accessing a table that maps the SiteID to a particular version can be monitored and additional programs run responsive to information about such access. | 11-13-2008 |
Dan Steigerwald, Cupertino, CA US
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20150229107 | MANUFACTURABLE LASER DIODE - A method for manufacturing a laser diode device includes providing a substrate having a surface region and forming epitaxial material overlying the surface region, the epitaxial material comprising an n-type cladding region, an active region comprising at least one active layer overlying the n-type cladding region, and a p-type cladding region overlying the active layer region. The epitaxial material is patterned to form a plurality of dice, each of the dice corresponding to at least one laser device, characterized by a first pitch between a pair of dice, the first pitch being less than a design width. Each of the plurality of dice are transferred to a carrier wafer such that each pair of dice is configured with a second pitch between each pair of dice, the second pitch being larger than the first pitch. | 08-13-2015 |
20150229108 | MANUFACTURABLE MULTI-EMITTER LASER DIODE - A method for manufacturing a multi-emitter laser diode device includes providing a substrate having a surface region and forming epitaxial material overlying the surface region, the epitaxial material comprising an n-type cladding region, an active region comprising at least one active layer overlying the n-type cladding region, and a p-type cladding region overlying the active layer region. The epitaxial material is patterned to form a plurality of dice, each of the dice corresponding to at least one laser device, characterized by a first pitch between a pair of dice, the first pitch being less than a design width. Each of the plurality of dice are transferred to a carrier wafer such that each pair of dice is configured with a second pitch between each pair of dice, the second pitch being larger than the first pitch. | 08-13-2015 |
Daniel A. Steigerwald, Cupertino, CA US
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20090250713 | Reflective Contact for a Semiconductor Light Emitting Device - A light emitting device includes a semiconductor structure comprising a light emitting layer disposed between an n-type region and a p-type region. A contact is formed on the semiconductor structure, the contact comprising a reflective metal in direct contact with the semiconductor structure and an additional metal or semi-metal disposed within the reflective metal. In some embodiments, the additional metal or semi-metal is a material with higher electronegativity than the reflective metal. The presence of the high electronegativity material in the contact may increase the overall electronegativity of the contact, which may reduce the forward voltage of the device. In some embodiments, an oxygen-gathering material is included in the contact. | 10-08-2009 |
20100006864 | IMPLANTED CONNECTORS IN LED SUBMOUNT FOR PEC ETCHING BIAS - A sapphire growth substrate wafer has epitaxially grown over it N-type layers, an active layer, and P-type layers to form GaN LEDs. Each LED is a flip-chip with its cathode contact and anode contact formed on the same side. The wafer is then diced to separate out the LEDs. A P-type silicon submount wafer has N-type doped interconnect regions for interconnecting all the cathode contacts together after the LEDs are mounted on the submount wafer. The sapphire substrate is then removed by a laser lift-off process. A bias voltage is then applied to the cathode contacts via the interconnect regions to bias the N-type layers for a photo-electrochemical etching process that roughens the exposed layer for increased light extraction. The submount wafer is then diced, cutting through the doped interconnect regions. | 01-14-2010 |
20100109030 | SERIES CONNECTED FLIP CHIP LEDS WITH GROWTH SUBSTRATE REMOVED - LED layers are grown over a sapphire substrate. Individual flip chip LEDs are formed by trenching or masked ion implantation. Modules containing a plurality of LEDs are diced and mounted on a submount wafer. A submount metal pattern or a metal pattern formed on the LEDs connects the LEDs in a module in series. The growth substrate is then removed, such as by laser lift-off. A semi-insulating layer is formed, prior to or after mounting, that mechanically connects the LEDs together. The semi-insulating layer may be formed by ion implantation of a layer between the substrate and the LED layers. PEC etching of the semi-insulating layer, exposed after substrate removal, may be performed by biasing the semi-insulating layer. The submount is then diced to create LED modules containing series-connected LEDs. | 05-06-2010 |
20100207157 | LED ASSEMBLY HAVING MAXIMUM METAL SUPPORT FOR LASER LIFT-OFF OF GROWTH SUBSTRATE - Described is a process for forming an LED structure using a laser lift-off process to remove the growth substrate (e.g., sapphire) after the LED die is bonded to a submount. The underside of the LED die has formed on it anode and cathode electrodes that are substantially in the same plane, where the electrodes cover at least 85% of the back surface of the LED structure. The submount has a corresponding layout of anode and cathode electrodes substantially in the same plane. The LED die electrodes and submount electrodes are ultrasonically welded together such that virtually the entire surface of the LED die is supported by the electrodes and submount. Other bonding techniques may also be used. No underfill is used. The growth substrate, forming the top of the LED structure, is then removed from the LED layers using a laser lift-off process. The extremely high pressures created during the laser lift-off process do not damage the LED layers due to the large area support of the LED layers by the electrodes and submount. | 08-19-2010 |
20110057569 | ZENER DIODE PROTECTION NETWORK IN SUBMOUNT FOR LEDS CONNECTED IN SERIES - A transient voltage suppressor circuit is disclosed for a plurality (N) of LEDs connected in series. Only one zener diode is created for connection to each node between LEDs, and a pair of zener diodes (the “end” zener diodes) are connected to the two pins (anode and cathode pads) of the series string. Therefore, only N+1 zener diodes are used. The end zener diodes (Q | 03-10-2011 |
20110136273 | REFLECTIVE CONTACT FOR A SEMICONDUCTOR LIGHT EMITTING DEVICE - A light emitting device includes a semiconductor structure comprising a light emitting layer disposed between an n-type region and a p-type region. A contact is formed on the semiconductor structure, the contact comprising a reflective metal in direct contact with the semiconductor structure and an additional metal or semi-metal disposed within the reflective metal. In some embodiments, the additional metal or semi-metal is a material with higher electronegativity than the reflective metal. The presence of the high electronegativity material in the contact may increase the overall electronegativity of the contact, which may reduce the forward voltage of the device. In some embodiments, an oxygen-gathering material is included in the contact. | 06-09-2011 |
20110297979 | PASSIVATION FOR A SEMICONDUCTOR LIGHT EMITTING DEVICE - In embodiments of the invention, a passivation layer is disposed over a side of a semiconductor structure including a light emitting layer disposed between an n-type region and a p-type region. A material configured to adhere to an underfill is disposed over an etched surface of the semiconductor structure. | 12-08-2011 |
20120025231 | SERIES CONNECTED FLIP CHIP LEDS WITH GROWTH SUBSTRATE REMOVED - LED layers are grown over a sapphire substrate. Individual flip chip LEDs are formed by trenching or masked ion implantation. Modules containing a plurality of LEDs are diced and mounted on a submount wafer. A submount metal pattern or a metal pattern formed on the LEDs connects the LEDs in a module in series. The growth substrate is then removed, such as by laser lift-off. A semi-insulating layer is formed, prior to or after mounting, that mechanically connects the LEDs together. The semi-insulating layer may be formed by ion implantation of a layer between the substrate and the LED layers. PEC etching of the semi-insulating layer, exposed after substrate removal, may be performed by biasing the semi-insulating layer. The submount is then diced to create LED modules containing series-connected LEDs. | 02-02-2012 |
20130252358 | PASSIVATION FOR A SEMICONDUCTOR LIGHT EMITTING DEVICE - In embodiments of the invention, a passivation layer is disposed over a side of a semiconductor structure including a light emitting layer disposed between an n-type region and a p-type region. A material configured to adhere to an underfill is disposed over an etched surface of the semiconductor structure. | 09-26-2013 |
Daniel Alexander Steigerwald, San Jose, CA US
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20160126408 | LED HAVING VERTICAL CONTACTS REDISTRIBUTED FOR FLIP CHIP MOUNTING - A light emitting diode (LED) structure has semiconductor layers, including a p-type layer, an active layer, and an n-type layer. The p-type layer has a bottom surface, and the n-type layer has a top surface though which light is emitted. A copper layer has a first portion electrically connected to and opposing the bottom surface of the p-type layer. A dielectric wall extends through the copper layer to isolate a second portion of the copper layer from the first portion. A metal shunt electrically connects the second portion of the copper layer to the top surface of the n-type layer. P-metal electrodes electrically connect to the first portion, and n-metal electrodes electrically connect to the second portion, wherein the LED structure forms a flip chip. Other embodiments of the methods and structures are also described. | 05-05-2016 |
20160126436 | P-N SEPARATION METAL FILL FOR FLIP CHIP LEDS - A light emitting diode (LED) structure has semiconductor layers, including a p-type layer, an active layer, and an n-type layer. The p-type layer has a bottom surface, and the n-type layer has a top surface through which light is emitted. Portions of the p-type layer and active layer are etched away to expose the n-type layer. The surface of the LED is patterned with a photoresist, and copper is plated over the exposed surfaces to form p and n electrodes electrically contacting their respective semiconductor layers. There is a gap between the n and p electrodes. To provide mechanical support of the semiconductor layers between the gap, a dielectric layer is formed in the gap followed by filling the gap with a metal. The metal is patterned to form stud bumps that substantially cover the bottom surface of the LED die, but do not short the electrodes. The substantially uniform coverage supports the semiconductor layer during subsequent process steps. | 05-05-2016 |
Daniel Alexander Steigerwald, Cupertino, CA US
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20140179029 | METHOD OF PROCESSING A SEMICONDUCTOR STRUCTURE - A method according to embodiments of the invention includes providing a wafer including a semiconductor structure grown on a growth substrate, the semiconductor structure comprising a III-nitride light emitting layer sandwiched between an n-type region and a p-type region. The wafer is bonded to a second substrate. The growth substrate is removed. After bonding the wafer to the second substrate, the wafer is processed into multiple light emitting devices. | 06-26-2014 |
Daniel Alexandria Steigerwald, Cupertino, CA US
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20140220716 | METHOD OF ATTACHING A LIGHT EMITTING DEVICE TO A SUPPORT SUBSTRATE - A method according to embodiments of the invention includes providing a wafer of semiconductor light emitting devices, each semiconductor light emitting device including a light emitting layer sandwiched between an n-type region and a p-type region. A wafer of support substrates is provided, each support substrate including a body. The wafer of semiconductor light emitting devices is bonded to the wafer of support substrates. Vias are formed extending through the entire thickness of the body of each support substrate. | 08-07-2014 |
James J. Steigerwald, Colorado Springs, CO US
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20110301424 | Vaginal Cuff Closure Systems, And Related Method For Knot-Free Laparoscopic Hysterectomy - A vaginal cuff closure system includes a speculum having a closed rear aspect, a secure suture ring and a fastener for removably attaching the secure suture ring with a blade of the speculum. A related method of using the closure system in knot-free laparoscopic hysterectomy is also disclosed. | 12-08-2011 |
Joseph Steigerwald, Forest Grove, OR US
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20140159159 | WRAP-AROUND TRENCH CONTACT STRUCTURE AND METHODS OF FABRICATION - A wrap-around source/drain trench contact structure is described. A plurality of semiconductor fins extend from a semiconductor substrate. A channel region is disposed in each fin between a pair of source/drain regions. An epitaxial semiconductor layer covers the top surface and sidewall surfaces of each fin over the source/drain regions, defining high aspect ratio gaps between adjacent fins. A pair of source/drain trench contacts are electrically coupled to the epitaxial semiconductor layers. The source/drain trench contacts comprise a conformal metal layer and a fill metal. The conformal metal layer conforms to the epitaxial semiconductor layers. The fill metal comprises a plug and a barrier layer, wherein the plug fills a contact trench formed above the fins and the conformal metal layer, and the barrier layer lines the plug to prevent interdiffusion of the conformal metal layer material and plug material. | 06-12-2014 |
Joseph M. Steigerwald, Forest Grove, OR US
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20110147812 | POLISH TO REMOVE TOPOGRAPHY IN SACRIFICIAL GATE LAYER PRIOR TO GATE PATTERNING - Techniques are disclosed for fabricating FinFET transistors (e.g., double-gate, trigate, etc). A sacrificial gate material (such as polysilicon or other suitable material) is deposited on fin structure, and polished to remove topography in the sacrificial gate material layer prior to gate patterning. A flat, topography-free surface (e.g., flatness of 50 nm or better, depending on size of minimum feature being formed) enables subsequent gate patterning and sacrificial gate material opening (via polishing) in a FinFET process flow. Use of the techniques described herein may manifest in structural ways. For instance, a top gate surface is relatively flat (e.g., flatness of 5 to 50 nm, depending on minimum gate height or other minimum feature size) as the gate travels over the fin. Also, a top down inspection of gate lines will generally show no or minimal line edge deviation or perturbation as the line runs over a fin. | 06-23-2011 |
20110147831 | METHOD FOR REPLACEMENT METAL GATE FILL - An exemplary embodiment of a method for forming a gate for a planar-type or a finFET-type transistor comprises forming a gate trench that includes an interior surface. A first work-function metal is formed on the interior surface of the gate trench, and a low-resistivity material is deposited on the first work-function metal using a chemical vapor deposition (CVD) technique, or an atomic layer deposition (ALD) technique, or combinations thereof. Another exemplary embodiment provides that a second work-function metal is formed on the first work-function metal, and then the low-resistivity material is deposited on the first work-function metal using a chemical vapor deposition (CVD) technique, or an atomic layer deposition (ALD) technique, or combinations thereof. | 06-23-2011 |
20110147851 | Method For Depositing Gate Metal For CMOS Devices - A semiconductor device comprises a substrate, a channel region, and a gate formed in association with the channel region. In one exemplary embodiment, the gate comprises a first material that is formed void free on an interior surface of a gate trench of the gate. A width of the gate trench comprises between about 8 nm and about 65 nm. The gate comprises a transition metal alloyed with carbon, aluminum or nitrogen, or combinations thereof, to form a carbide, a nitride, or a carbo-nitride, or combinations thereof, of the transition metal. In another exemplary embodiment, the gate further comprises a second material formed void free on an interior surface of the first material and comprises a transition metal alloyed with carbon, aluminum or nitrogen, or combinations thereof, to form a carbide, a nitride, or a carbo-nitride, or combinations thereof, of the transition metal. | 06-23-2011 |
20110147888 | METHODS TO FORM MEMORY DEVICES HAVING A CAPACITOR WITH A RECESSED ELECTRODE - Methods to form memory devices having a MIM capacitor with a recessed electrode are described. In one embodiment, a method of forming a MIM capacitor with a recessed electrode includes forming an excavated feature defined by a lower portion that forms a bottom and an upper portion that forms sidewalls of the excavated feature. The method includes depositing a lower electrode layer in the feature, depositing an electrically insulating layer on the lower electrode layer, and depositing an upper electrode layer on the electrically insulating layer to form the MIM capacitor. The method includes removing an upper portion of the MIM capacitor to expose an upper surface of the electrode layers and then selectively etching one of the electrode layers to recess one of the electrode layers. This recess isolates the electrodes from each other and reduces the likelihood of a current leakage path between the electrodes. | 06-23-2011 |
20110156107 | Self-aligned contacts - A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations. | 06-30-2011 |
20130178033 | SELF-ALIGNED CONTACTS - A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations. | 07-11-2013 |
20130271938 | FORMATION OF DRAM CAPACITOR AMONG METAL INTERCONNECT - Techniques are disclosed for integrating capacitors among the metal interconnect for embedded DRAM applications. In some embodiments, the technique uses a wet etch to completely remove the interconnect metal (e.g., copper) that is exposed prior to the capacitor formation. This interconnect metal removal precludes that metal from contaminating the hi-k dielectric of the capacitor. Another benefit is increased height (surface area) of the capacitor, which allows for increased charge storage. In one example embodiment, an integrated circuit device is provided that includes a substrate having at least a portion of a DRAM bit cell circuitry, an interconnect layer on the substrate and including one or more metal-containing interconnect features, and a capacitor at least partly in the interconnect layer and occupying space from which a metal-containing interconnect feature was removed. The integrated circuit device can be, for example, a processor or a communications device. | 10-17-2013 |
20140001598 | ATOMIC LAYER DEPOSITION (ALD) OF TAALC FOR CAPACITOR INTEGRATION | 01-02-2014 |
20140002976 | RECESSED BOTTOM-ELECTRODE CAPACITORS AND METHODS OF ASSEMBLING SAME | 01-02-2014 |
20140151817 | SELF-ALIGNED CONTACTS - A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations. | 06-05-2014 |
20140264668 | LOGIC CHIP INCLUDING EMBEDDED MAGNETIC TUNNEL JUNCTIONS - An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-MRAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) that has an upper MTJ layer, a lower MTJ layer, and a tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. Other embodiments are described herein. | 09-18-2014 |
20140264679 | LOGIC CHIP INCLUDING EMBEDDED MAGNETIC TUNNEL JUNCTIONS - An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-MRAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) with an upper MTJ layer, lower MTJ layer, and tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. In an embodiment the first and second ILDs directly contact one another. Other embodiments are described herein. | 09-18-2014 |
20150270216 | SELF-ALIGNED CONTACTS - A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations. | 09-24-2015 |
Mark Steigerwald, Lacrosse, WI US
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20140096416 | LIGHTED CHILD'S SNOWSHOE - A snowshoe including a unitary molded polymer deck having a bottom surface defining a toe portion and a heel portion. The toe portion is divided from the heel portion. A toe panel together with the toe portion defines a generally enclosed space into which a lighting module including a battery, a switch; electrical leads and at least one electrically illuminated light source. The light module is substantially contained in the enclosed space and the at least one electrically illuminated light source is located in at least one light source pocket that passes through a portion of the unitary molded polymer deck such that the electrically illuminated light source is visible from above the deck. The switch selectively completes a circuit between the battery and the electrically illuminated light source upon actuation. | 04-10-2014 |
Mark E. Steigerwald, Sunnyvale, CA US
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20090316460 | METHOD AND APPARATUS FOR MEMORY REDUNDANCY IN A MICROPROCESSOR - An apparatus for redundancy of a memory array includes a primary memory array including a plurality of memory cells, one or more of which are defective. A redundant array includes a CAM array that includes a plurality of memory cells. The CAM array is addressed by the address of a defective memory location within the primary memory array and provides a match identification and a resource identification. The redundant array also includes a translation array wherein an offset to configure an input/output multiplexer is stored. The redundant array also includes a redundant data array including a plurality of memory cells wherein one or more memory cells of the redundant data array are used instead of one or more defective memory cells of the primary array. | 12-24-2009 |
Michael L. Steigerwald, Martinsville, NJ US
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20110062422 | Systems And Methods For Forming Defects On Graphitic Materials And Curing Radiation-Damaged Graphitic Materials - Systems and methods are disclosed herein for forming defects on graphitic materials. The methods for forming defects include applying a radiation reactive material on a graphitic material, irradiating the applied radiation reactive material to produce a reactive species, and permitting the reactive species to react with the graphitic material to form defects. Additionally, disclosed are methods for removing defects on graphitic materials. | 03-17-2011 |
Michael Louis Steigerwald, Martinsville, NJ US
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20160024128 | SOLID-STATE MATERIALS FORMED OF MOLECULAR CLUSTERS AND METHOD OF FORMING SAME - A solid-state material comprising a solid-state compound is provided. The solid-state compound has the formula: [Cluster1][Cluster2] | 01-28-2016 |
Richard Steigerwald, San Luis Obispo, CA US
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20140149259 | CONSUMER CENTRIC ONLINE PRODUCT RESEARCH - Embodiments of the invention relate to providing online product research. Data related to an activity performed by a consumer at a first electronic commerce website is collected. The collected data includes information about a first product, and the information about the first product is stored as product research data. The product research data is associated with the consumer. It is detected that the consumer is accessing a location in a second electronic commerce website that includes information about a second product. The product research data is searched for data related to the information about the second product. The information about the first product is located in response to searching the product research data for data related to the information about the second product, and the consumer is presented with the information about the first product along with the information about the second product. | 05-29-2014 |
Scott Steigerwald, Aurora, CO US
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20150116351 | SYSTEM AND METHOD FOR VISUALIZING THE RELATIONSHIP OF COMPLEX DATA ATTRIBUTES - A mapping module is configured to create a preview layer that depicts attributes of real-world objects located within the boundaries of a map. The mapping module uses search criteria to highlight multiple attributes without separately creating a filtered data set for each attribute. The mapping module may change the boundaries of the map in response to changed search criteria. The mapping module may also change the displayed attributes in response to changed map boundaries. By highlighting the selected attributes, the mapping module helps to visually identify relationships between complex real-world objects. | 04-30-2015 |
Sean Steigerwald, Stamford, CT US
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20090119851 | Novel Hair Dyeing Composition and Method - Hair coloring compositions and methods of coloring hair with such compositions for providing a temporary color to the hair are disclosed, which compositions comprise an inorganic colored pigment preferably selected from the group consisting of iron oxides, ultramarines, and mixtures thereof, a nonvolatile dimethicone copolyol component, and preferably a cationic deposition aid. | 05-14-2009 |
Thomas Steigerwald, Rochester Hills, MI US
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20090033114 | Loading area cover for a motor vehicle - A loading area cover with a flexible flat structure, at a front end region, is connected to a dimensionally stable holding profile. The profile extends transversely to the flat structure's longitudinal direction and is releasably arranged in vehicle-fixed holders. The holding profile has frontal compensating elements in the vicinity of the vehicle-fixed holders, through which the front end region of the flat structure, or the dimensioning of the holding profile, can be displaced to a limited extent in the transverse direction and/or longitudinal direction. | 02-05-2009 |
Todd Steigerwald, Austin, TX US
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20090163147 | Method for assigning control channels - The present invention is a mobile device capable of transmitting or receiving wireless signals and incorporating an FPC shielded RF signal conductor for connecting transmitter and/or receiver circuitry to an associated RF antenna or antennas. In some embodiments FCP may incorporate the antenna in an unshielded section of the FPC. In some embodiments a single FPC may provide for multiple RF carrier conductors each with their own associated shielding. | 06-25-2009 |
Todd W. Steigerwald, Austin, TX US
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20100207641 | System and Method for Evaluating the Electromagnetic Compatibility of Integrated Circuits in an In-Situ Environment - A device is configured to evaluate electromagnetic characteristics of an integrated circuit. The device includes a fluid chamber, a first impeller, a second impeller, and a radio frequency measurement antenna. The fluid chamber is configured to receive the integrated circuit and to cool the integrated circuit. The first impeller is disposed within the fluid chamber and configured to distribute a first electromagnetic field produced by the integrated circuit within the fluid chamber along a first axis. The second impeller is within the fluid chamber and configured to distribute the first electromagnetic field produced by the integrated circuit within the fluid chamber along a second axis. The radio frequency measurement antenna is disposed proximate the fluid chamber and configured to measure an electric field and a magnetic field of the first electromagnetic field. | 08-19-2010 |
20110169503 | Chassis Shielding Effectiveness Evaluation System - A chassis shielding effectiveness evaluation system includes a chassis having a chassis ground. A board is located in the chassis and includes a board ground layer. A signal generator includes at least one ground member coupled to the chassis ground and a signal member coupled to the board ground layer. The signal generator is operable to send a signal through the signal member to the board ground layer. | 07-14-2011 |
20120068730 | System and Method for Evaluating the Electromagnetic Compatibility of Integrated Circuits in an In-Situ Environment - A device is configured to evaluate electromagnetic characteristics of an integrated circuit. The device includes a fluid chamber, a first impeller, a second impeller, and a radio frequency measurement antenna. The fluid chamber is configured to receive the integrated circuit and to cool the integrated circuit. The first impeller is disposed within the fluid chamber and configured to distribute a first electromagnetic field produced by the integrated circuit within the fluid chamber along a first axis. The second impeller is within the fluid chamber and configured to distribute the first electromagnetic field produced by the integrated circuit within the fluid chamber along a second axis. The radio frequency measurement antenna is disposed proximate the fluid chamber and configured to measure an electric field and a magnetic field of the first electromagnetic field. | 03-22-2012 |
20150282392 | COMBINED ELECTROMAGNETIC SHIELD AND THERMAL MANAGEMENT DEVICE - Various EMI shields with thermal management capabilities are disclosed. In one aspect, an EMI shield is provided that includes a thermal spreader plate adapted to be seated on and convey heat from an electromagnetic emissions generating component. The thermal spreader plate has a first material composition and a shield effectiveness that is absorption dominant to electromagnetic waves at a given electromagnetic emissions frequency. The EMI shield also includes a shell to cover and reflect electromagnetic emissions from the electromagnetic emissions generating component. The shell has a second material composition different than the first material composition and a shield effectiveness that is reflection dominant to electromagnetic waves at the given electromagnetic emissions frequency. | 10-01-2015 |