Patent application number | Description | Published |
20080276026 | SELECTIVE DEACTIVATION OF PROCESSOR CORES IN MULTIPLE PROCESSOR CORE SYSTEMS - A method includes applying a voltage to a first processor core of a plurality of processor cores to deactivate the first processor core, the voltage less than a retention voltage of the first processor core. The application of the voltage can be in response to a software setting. The software setting can be configured via a user input, a software application, an operating system, or a BIOS setting. Alternately, the application of the voltage can be in response to a permanent hardware setting, such as the state of a fuse associated with the first processor core. | 11-06-2008 |
20080276236 | DATA PROCESSING DEVICE WITH LOW-POWER CACHE ACCESS MODE - A processor can operate in three different modes. In an active mode, a first voltage is provided to the processor, where the first voltage is sufficient to allow the processor to execute instructions. In a low-power mode, a retention voltage is provided to the processor. The processor consumes less power in the retention mode than in the active mode. In addition, the processor can operate in a third mode, where a voltage is provided to the processor sufficient to allow the processor to process cache messages, such as coherency messages, but not execute other normal operations or perform normal operations at a very low speed relative to their performance in the active mode. | 11-06-2008 |
20080288799 | DYNAMIC PROCESSOR POWER MANAGEMENT DEVICE AND METHOD THEREOF - A processor can operate in different power modes. In an active power mode, the processor executes software. In response to receiving a halt indication from the software, hardware at the processor evaluates bus transactions for the processor. If the bus transactions meet a heuristic, hardware places a processor core in a lower power mode, such as a retention mode. Because the bus transactions are evaluated by hardware, rather than by software, and the software is not required to perform handshakes and other protocols to place the processor in the lower power mode, the processor is able to place the processor core into the lower power mode more quickly, thereby conserving power. | 11-20-2008 |
20140331069 | POWER MANAGEMENT FOR MULTIPLE COMPUTE UNITS - An interface couples a plurality of compute units to a power management controller. The interface conveys a power report for the plurality of compute units to the power management controller. The power management controller receives the power report, determines a power action for the plurality of compute units based at least in part on the power report, and transmits a message specifying the power action through the interface. The power action is performed. | 11-06-2014 |
Patent application number | Description | Published |
20090235260 | Enhanced Control of CPU Parking and Thread Rescheduling for Maximizing the Benefits of Low-Power State - A system may comprise a plurality of processing units and a scheduler configured to maintain a record for each respective processing unit. Each respective record may comprise entries which may indicate 1) how long the respective processing unit has been residing in an idle state, 2) a present power-state in which the respective processing unit resides, and 3) whether the respective processing unit is a designated default (bootstrap) processing unit. The scheduler may select one or more of the plurality of processing units according to their respective records, and assign impending instructions to be executed on the selected one or more processing units. Where additional processing units are required, the scheduler may also insert an instruction to trigger an inter-processor interrupt to transition one or more processing units out of idle-state. The scheduler may then assign some impending instructions to these one or more processing units. | 09-17-2009 |
20100058078 | Protocol for Power State Determination and Demotion - A system may comprise a plurality of processing units, and a control unit and monitoring unit interfacing with the processing units. The control unit may receive requests for transitioning the processing units to respective target power-states, and specify respective target HW power-states corresponding to the respective target power-states. The monitoring unit may monitor operating characteristics of the system, and determine based on operating characteristics whether to allow the processing units to transition to the respective target hardware (HW) power-states. The control unit may be configured to change the respective target HW power-state to a respective updated HW power-state for each processing units for which it is determined that transition to its respective target HW power-state should not be allowed. The control unit may also be configured to infer a common target HW power-state based on the respective target HW power-states of processing units of a subset of the plurality of processing units, when the processing units of the subset of the plurality of processing units share at least one resource domain. | 03-04-2010 |
20100162256 | OPTIMIZATION OF APPLICATION POWER CONSUMPTION AND PERFORMANCE IN AN INTEGRATED SYSTEM ON A CHIP - A method for determining an operating point of a shared resource. The method includes receiving indications of access demand to a shared resource from each of a plurality of functional units and determining a maximum access demand from among the plurality of functional units based on their respective indications. The method further includes determining a required operating point of the shared resource based on the maximum access demand, wherein the shared resource is shared by each of the plurality of functional units, comparing the required operating point to a present operating point of the shared resource, and changing to the required operating point from the present operating point if the required and present operating points are different. | 06-24-2010 |
20100287394 | NORTH-BRIDGE TO SOUTH-BRIDGE PROTOCOL FOR PLACING PROCESSOR IN LOW POWER STATE - A processor integrated circuit has one or more processor cores and a power management controller in a North-Bridge that generates a first power state recommendation for the one or more processor cores. The North-Bridge also receives a second power state recommendation from a South-Bridge integrated circuit. The North-Bridge determines a final power state for the one or more processor cores based on the first and second power state recommendations. | 11-11-2010 |
20110078478 | METHOD AND APPARATUS FOR TRANSITIONING DEVICES BETWEEN POWER STATES BASED ON ACTIVITY REQUEST FREQUENCY - A method for transitioning power states in a device includes designating a first reduced power state as a target power state. A first expected residency for the target power state is determined based on a counting of activity requests associated with the device. The device is transitioned to the target power state responsive to the expected residency satisfying a first predetermined threshold. | 03-31-2011 |
20110112798 | CONTROLLING PERFORMANCE/POWER BY FREQUENCY CONTROL OF THE RESPONDING NODE - A processing node tracks probe activity level associated with its internal caching or memory system. If the probe activity level increases above a threshold probe activity level, the performance state of the processing node is increased above its current performance state to provide enhanced performance capability in responding to the probe requests. After entering the higher performance state in response to the probe activity level being above the threshold probe activity level, the processing nodes returns to a lower performance state in response to a reduction in probe activity. There may be multiple threshold probe activity levels and associated performance states. | 05-12-2011 |
20110113202 | CACHE FLUSH BASED ON IDLE PREDICTION AND PROBE ACTIVITY LEVEL - A processing node tracks probe activity level associated with its cache. The processing node and/or processing system further predicts an idle duration. If the probe activity level increases above a threshold probe activity level, and the idle duration prediction is above a threshold idle duration threshold, the processing node flushes its cache to prevent probes to the cache. If the probe activity level is above the threshold probe activity level but the predicted idle duration is too short, the performance state of the processing node is increased above its current performance state to provide enhanced performance capability in responding to the probe requests. | 05-12-2011 |
20110264934 | METHOD AND APPARATUS FOR MEMORY POWER MANAGEMENT - A method for power management is disclosed. The method may include monitoring requests for access to a memory of a memory subsystem by one or more processor cores; and monitoring requests for access to the memory conveyed by an input/output (I/O) unit. The method may further include determining if at least a first amount of time has elapsed since any one of the processor cores has asserted a memory access request and determining if at least a second amount of time has elapsed since the I/O unit has conveyed a memory access request. A first signal may be asserted if the first and second amounts of time have elapsed. A memory subsystem may be transitioned from operating in a full power state to a first low power state responsive to assertion of the first signal. | 10-27-2011 |
20110283124 | METHOD AND APPARATUS FOR CACHE CONTROL - A method and apparatus for dynamically controlling a cache size is disclosed. In one embodiment, a method includes changing an operating point of a processor from a first operating point to a second operating point, and selectively removing power from one or more ways of a cache memory responsive to changing the operating point. The method further includes processing one or more instructions in the processor subsequent to removing power from the one or more ways of the cache memory, wherein said processing includes accessing one or more ways of the cache memory from which power was not removed. | 11-17-2011 |
20120324258 | POWER STATE MANAGEMENT OF AN INPUT/OUTPUT SERVICING COMPONENT OF A PROCESSOR SYSTEM - A method of regulating power states in a processing system may begin with a processor component reporting a present processor power state to an input-output hub, where the present processor power state corresponds to one of a plurality of different processor power states ranging from an active state to an inactive state. The input-output hub receives data indicative of the present processor power state and, in response to receiving the present processor power state, establishes a lowest allowable hub power state that corresponds to one of a plurality of different hub power states ranging from an active state to an inactive state. The method continues by determining a present hub power state for the input-output hub, wherein depth of the present hub power state is less than or equal to depth of the lowest allowable hub power state. | 12-20-2012 |
20130007494 | MANAGING PROCESSOR-STATE TRANSITIONS - Techniques are disclosed relating to managing power consumption and latencies for entry and exit of idle power states. In one embodiment, a processor includes a processing core configured to operate in a plurality of power states (e.g., C-states) that includes an operating power state and at least one idle power state. The processing core is also configured to operate in a plurality of performance states. The processor further includes a power management unit configured to receive a request from the processing core to enter the at least one idle power state. The power management unit is configured to select a first of the plurality of performance states (e.g., P-states) based on the requested idle power state. In one embodiment, the power management unit is further configured to cause the processing core to transition into the selected first performance state prior to entering the requested idle power state. | 01-03-2013 |
20130151869 | METHOD FOR SOC PERFORMANCE AND POWER OPTIMIZATION - A system and method for efficient management of resources within a semiconductor chip for an optimal combination of power reduction and high performance. An intergrated circuit, such as a system on a chip (SOC), includes at least two processing units. The second processing unit includes a cache. The SOC includes a power management unit (PMU) that determines whether a first activity level for the first processing unit is above a first threshold and a second activity level for the second processing unit is below a second threshold. If this condition is true, then the PMU places a limit on a highest power-performance state (P-state) used by the second processing unit. The PMU sends an indication to flush the at least one cache within the second processing unit. The PMU changes a P-state used by the first processing unit to a higher performance P-state. | 06-13-2013 |
20130159750 | METHOD AND APPARATUS FOR TRANSITIONING A SYSTEM TO AN ACTIVE DISCONNECT STATE - A processor includes a processor core and a power management controller operable to receive a timer event, store the timer event, generate a hardware system sleep command to enter a hardware system sleep state, and restore the timer event upon exiting from the hardware system sleep state. | 06-20-2013 |
20130227321 | METHOD AND APPARATUS FOR CACHE CONTROL - A method and apparatus for dynamically controlling a cache size is disclosed. In one embodiment, a method includes changing an operating point of a processor from a first operating point to a second operating point, and selectively removing power from one or more ways of a cache memory responsive to changing the operating point. The method further includes processing one or more instructions in the processor subsequent to removing power from the one or more ways of the cache memory, wherein said processing includes accessing one or more ways of the cache memory from which power was not removed. | 08-29-2013 |
20130246820 | METHOD FOR ADAPTIVE PERFORMANCE OPTIMIZATION OF THE SOC - An apparatus and method for dynamically adjusting power limits for processing nodes and other components, such as peripheral interfaces, is disclosed. The apparatus includes multiple processing nodes and other components, and further includes a power management unit configured to set a first frequency limit for at least one of the processing nodes responsive to receiving an indication of a first detected temperature greater than a first temperature threshold. Initial power limits are set below guard-band power limits for components that do not have reliable reporting of power consumption or for cost or power saving reasons. The amount of throttling of processing nodes is used to adjust the power limits for the processing nodes and these components. | 09-19-2013 |
20130275778 | PROCESSOR BRIDGE POWER MANAGEMENT - A power controller can set the power state of a processor bridge based on which processor modules are in a communicative state. In addition, for a power state where selected processor modules are expected to be non-communicative, the power controller can set the supplied voltage to have a reduced voltage guard band as compared to other power states. These power management techniques can reduce the power consumed by the processor. | 10-17-2013 |
20130283078 | DYNAMIC PERFORMANCE CONTROL OF PROCESSING NODES - An apparatus and method for performance control of processing nodes is disclosed. In one embodiment, a system includes a processing node and a power management unit configured to, for each of a plurality of time intervals, monitor an activity level of the processing node, cause the processing node to operate at a high operating point during one successive time interval if the activity level in the given interval is greater than a high activity threshold, operate at a low operating point at least one successive time interval if the activity level is less than a low activity threshold, or enable operating system software to cause the processing node to operate at one of one or more predefined intermediate operating points of the plurality of operating points if the activity level is less than the high activity threshold and greater than the low activity threshold. | 10-24-2013 |
20140136869 | ADAPTIVE CONNECTED STANDBY FOR A COMPUTING DEVICE - Various computing devices and methods of managing the power consumption thereby are disclosed. In one aspect, a method of managing power consumption of a computing device that has a battery is provided. The method includes cycling the computing device between a connected standby active state and a connected standby idle state. The duration of the connected standby idle state is set based at least in part on a charge level of the battery. | 05-15-2014 |