Patent application number | Description | Published |
20090094567 | IMMUNITY TO CHARGING DAMAGE IN SILICON-ON-INSULATOR DEVICES - Method embodiments herein determine a connection order in which connections will be made to connect active devices to antennas within a given circuit design. The method also evaluates the possibilities that these connections to the antennas will cause charging damage in the devices that are connected to the antennas. Such possibilities are based on the connection order, the size of the antennas, and the likelihood that charges will flow from the antennas through insulators of the devices. If a significant possibility for damage exists, the method can reduce the size of the antenna. | 04-09-2009 |
20090158230 | DETERMINING ALLOWABLE ANTENNA AREA AS FUNCTION OF TOTAL GATE INSULATOR AREA FOR SOI TECHNOLOGY - A method is disclosed of determining allowable antenna limits for semiconductor-on-insulator (SOI) technology. In one embodiment, the method may include: determining antenna area on a gate; determining antenna area on a source/drain; determining a total gate insulator area between gate and source/drain nets; and calculating allowable antenna area as a function of the total gate insulator area between the nets such that a larger total antenna area is allowed for larger total gate insulator area between the nets. | 06-18-2009 |
20090174008 | METHOD AND STRUCTURE TO PROTECT FETs FROM PLASMA DAMAGE DURING FEOL PROCESSING - Protecting a FET from plasma damage during FEOL processing by forming a FET-like structure in conjunction with and adjacent to an FET, in a same well as the FET, but having a body doped opposite to the well polarity. The FET-like structure is formed with thinner oxide than the gate oxide of the FET, has a gate structure (poly) connected with the gate of the FET, and may be shorted out by the first metal layer (M | 07-09-2009 |
20090258480 | METHOD OF SELECTIVELY ADJUSTING ION IMPLANTATION DOSE ON SEMICONDUCTOR DEVICES - A first semiconductor region and a second semiconductor region separated by a shallow trench isolation region are formed in a semiconductor substrate. A photoresist is applied and patterned so that the first semiconductor region is exposed, while the second semiconductor region is covered. Depending on the setting of parameters for the location of an edge of the patterned photoresist, the slope of sidewalls of the photoresist, the thickness of the photoresist, and the direction of ion implantation, ions may, or may not, be implanted into the entirety of the surface portion of the first semiconductor region by shading or non-shading of the first semiconductor region. The semiconductor substrate may further comprise a third semiconductor region into which the dopants are implanted irrespective of the shading or non-shading of the first semiconductor region. The selection of shading or non-shading may be changed from substrate to substrate in manufacturing. | 10-15-2009 |
20100013026 | INTEGRATED CIRCUITS COMPRISING RESISTORS HAVING DIFFERENT SHEET RESISTANCES AND METHODS OF FABRICATING THE SAME - The fabrication of integrated circuits comprising resistors having the same structure but different sheet resistances is disclosed herein. In one embodiment, a method of fabricating an integrated circuit comprises: concurrently forming a first resistor laterally spaced from a second resistor above or within a semiconductor substrate, the first and second resistors comprising a doped semiconductive material; depositing a dopant receiving material across the first and second resistors and the semiconductor substrate; removing the dopant receiving material from upon the first resistor while retaining the dopant receiving material upon the second resistor; and annealing the first and second resistors to cause a first sheet resistance of the first resistor to be different from a second sheet resistance of the second resistor. | 01-21-2010 |
20100025769 | ISOLATED HIGH PERFORMANCE FET WITH A CONTROLLABLE BODY RESISTANCE - The present invention provides a method of controlling bias in an electrical device including providing semiconductor devices on a bulk semiconductor substrate each including an active body region that is isolated from the active body region of adjacent devices, and providing a body resistor in electrical contact with the active body region of the bulk semiconductor substrate, wherein the body resistor provides for adjustability of the body potential of the semiconductor devices. In another aspect the present invention provides a semiconductor device including a bulk semiconductor substrate, at least one field effect transistor formed on the bulk semiconductor substrate including an isolated active body region, and a resistor in electrical communication with the isolated active body region. | 02-04-2010 |
20120018812 | METHOD AND STRUCTURE FOR BALANCING POWER AND PERFORMANCE USING FLUORINE AND NITROGEN DOPED SUBSTRATES - Methods and systems evaluate an integrated circuit design for power consumption balance and performance balance, using a computerized device. Based on this process of evaluating the integrated circuit, the methods and systems can identify first sets of integrated circuit transistor structures within the integrated circuit design that need reduced power leakage and second sets of integrated circuit transistor structures that need higher performance to achieve the desired power consumption balance and performance balance. With this, the methods and systems alter the integrated circuit design to include implantation of a first dopant into a substrate before a gate insulator formation for the first sets of integrated circuit transistor structures; and alter the integrated circuit design to include implantation of a second dopant into the substrate before a gate insulator formation for the second sets of integrated circuit transistor structures. The method and system then output the altered integrated circuit design from the computerized device and/or manufactures the device according to the altered integrated circuit design. | 01-26-2012 |
20120146147 | Pseudo Butted Junction Structure for Back Plane Connection - Butted p-n junctions interconnecting back gates in an SOI process, methods for making butted p-n junctions, and design structures. The butted junction includes an overlapping region formed in the bulk substrate by overlapping the mask windows of the ion-implantation masks used to form the back gates. A damaged region may be selectively formed to introduce mid-gap energy levels in the semiconductor material of the overlapping region employing one of the implantation masks used to form the back gates. The damage region causes the butted junction to be leaky and conductively couples the overlapped back gates to each other and to the substrate. Other back gates may be formed that are floating and not coupled to the substrate. | 06-14-2012 |
20120168210 | Methods and Structures Involving Terminal Connections - A method for forming a conductive contact includes forming a copper contact region in an intermediary layer, depositing an insulator layer over the copper contact region and the intermediary layer, patterning a photoresist layer on the insulator layer, etching to remove a portion of the insulator layer and expose a portion of the copper contact region, depositing a conductive material layer over the exposed portion of the copper contact region and the photoresist layer, and removing the photoresist layer and the conductive material layer disposed on the photoresist layer. | 07-05-2012 |
20120203532 | Method for Dynamically Switching Analyses and For Dynamically Switching Models in Circuit Simulators - Performing a transient analysis with a compact FET model that is predominantly intended for DC analysis, such as an IDDQ leakage model, to enable toggling logic states in sequential logic circuits that cannot otherwise be examined in a DC analysis. An embodiment enables examining the DC or AC conditions of any logic state of any logic circuit in a DC or AC analysis, and additionally, it eliminates a potentially long execution time of a transient analysis with a DC model. Further solved is the present need to run two simulations and to maintain two netlists in order to overcome being unable to toggle certain logic states in the DC analysis. The invention achieves the aforementioned in a single simulation with a single netlist that calculates the DC operating circuit conditions with a model A on the fly at predetermined times or in certain logic states, during a transient analysis with a model B. | 08-09-2012 |
20120214280 | HEAT SINK FOR INTEGRATED CIRCUIT DEVICES - A resistor with heat sink is provided. The heat sink includes a conductive path having metal or other thermal conductor having a high thermal conductivity. To avoid shorting the electrical resistor to ground with the thermal conductor, a thin layer of high thermal conductivity electrical insulator is interposed between the thermal conductor and the body of the resistor. Accordingly, a resistor can carry large amounts of current because the high conductivity thermal conductor will conduct heat away from the resistor to a heat sink. Various configurations of thermal conductors and heat sinks are provided offering good thermal conductive properties in addition to reduced parasitic capacitances and other parasitic electrical effects, which would reduce the high frequency response of the electrical resistor. | 08-23-2012 |
20120299080 | STRUCTURE FOR CMOS ETSOI WITH MULTIPLE THRESHOLD VOLTAGES AND ACTIVE WELL BIAS CAPABILITY - A structure includes a semiconductor substrate having a first type of conductivity and a top surface; an insulating layer disposed over the top surface; a semiconductor layer disposed over the insulating layer and a plurality of transistor devices disposed upon the semiconductor layer. Each transistor device includes a source, a drain and a gate stack defining a channel between the source and the drain, where some transistor devices have a first type of channel conductivity and the remaining transistor devices have a second type of channel conductivity. The structure further includes a well region formed adjacent to the top surface of the substrate and underlying the plurality of transistor devices, the well region having a second type of conductivity and extending to a first depth within the substrate. The structure further includes first isolation regions between adjacent transistor devices and extending through the semiconductor layer to a depth sufficient for electrically isolating the adjacent transistor devices from one another, and second isolation regions between selected adjacent transistor devices. The second isolation regions extend through the silicon layer, through the insulating layer and into the substrate to a second depth that is greater than the first depth to electrically separate the well region into a first well region and a second well region. The structure further includes at least one back gate region disposed wholly within a well region and underlying one of the plurality of transistor devices, the at least one back gate region has the first type of conductivity and is electrically floating within the well region, where during operation the at least one back gate region having the first type of conductivity is biased by leakage and capacitive coupling by a bias potential applied to the well region within which it is disposed. | 11-29-2012 |
20120326752 | DESIGN METHOD AND STRUCTURE FOR A TRANSISTOR HAVING A RELATIVELY LARGE THRESHOLD VOLTAGE VARIATION RANGE AND FOR A RANDOM NUMBER GENERATOR INCORPORATING MULTIPLE ESSENTIALLY IDENTICAL TRANSISTORS HAVING SUCH A LARGE THRESHOLD VOLTAGE VARIATION RANGE - Disclosed are a design method and structure for a transistor having a relatively large threshold voltage (Vt) variation range due to exacerbated random dopant fluctuation (RDF). Exacerbated RDF and, thereby a relatively large Vt variation range, is achieved through the use of complementary doping in one or more transistor components and/or through lateral dopant non-uniformity between the channel region and any halo regions. Also disclosed are a design method and structure for a random number generator, which incorporates multiple pairs of essentially identical transistors having such a large Vt variation and which relies on Vt mismatch in pairs of those the transistors to generate a multi-bit output (e.g., a unique identifier for a chip or a secret key). By widening the Vt variation range of the transistors in the random number generator, detecting Vt mismatch between transistors becomes more likely and the resulting multi-bit output will be more stable. | 12-27-2012 |
20130015911 | SOLUTIONS FOR CONTROLLING BULK BIAS VOLTAGE IN AN EXTREMELY THIN SILICON-ON-INSULATOR (ETSOI) INTEGRATED CIRCUIT CHIPAANM Cranford, JR.; Hayden C.AACI CaryAAST NCAACO USAAGP Cranford, JR.; Hayden C. Cary NC USAANM Hook; Terence B.AACI JerichoAAST VTAACO USAAGP Hook; Terence B. Jericho VT US - Solutions for optimizing a bulk bias across a substrate of an ETSOI device are disclosed. In one embodiment, an apparatus for optimizing a bulk bias across a substrate of an ETSOI device is disclosed, including: a sensing circuit for sensing at least one predetermined circuit parameter; a charging circuit for applying a bias voltage to the substrate of the ETSOI device; and a processing circuit connected to the sensing circuit and the charging circuit, the processing circuit configured to receive an output of the sensing circuit, and adjust the bias voltage applied to substrate of the ETSOI device in response to determining whether the bias voltage deviates from a target amount. | 01-17-2013 |
20130120055 | SOLUTIONS FOR CONTROLLING BULK BIAS VOLTAGE IN AN EXTREMELY THIN SILICON-ON-INSULATOR (ETSOI) INTEGRATED CIRCUIT CHIP - Solutions for optimizing a bulk bias across a substrate of an ETSOI device are disclosed. In one embodiment, an apparatus for optimizing a bulk bias across a substrate of an ETSOI device is disclosed, including: a sensing circuit for sensing at least one predetermined circuit parameter; a charging circuit for applying a bias voltage to the substrate of the ETSOI device; and a processing circuit connected to the sensing circuit and the charging circuit, the processing circuit configured to receive an output of the sensing circuit, and adjust the bias voltage applied to substrate of the ETSOI device in response to determining whether the bias voltage deviates from a target amount. | 05-16-2013 |
20130134545 | SELF-LIMITING OXYGEN SEAL FOR HIGH-K DIELECTRIC, RELATED METHOD AND DESIGN STRUCTURE - A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate including: a high-K dielectric region; a blocking region disposed against at least one surface of the high-K dielectric region and adapted to form an oxidized layer in response to exposure to oxygen; and an oxygen rich region disposed against the blocking region such that the blocking region is interposed between the oxygen rich region and the high-K dielectric region. | 05-30-2013 |
20130189818 | TRENCH ISOLATION AND METHOD OF FABRICATING TRENCH ISOLATION - Trench isolation structure and method of forming trench isolation structures. The structures includes a trench in a silicon region of a substrate, the trench extending from a top surface of the substrate into the silicon region; an ion implantation stopping layer over sidewalls of the trench; a dielectric fill material filling remaining space in the trench, the dielectric fill material not including any materials found in the stopping layer; an N-type dopant species in a first region of the silicon region on a first side of the trench; the N-type dopant species in a first region of the dielectric material adjacent to the first side of the trench; a P-type dopant species in a second region of the silicon region on a second side of the trench; and the P-type dopant species in a second region of the dielectric material adjacent to the second side of the trench. | 07-25-2013 |
20130221987 | STATIC NOISE MARGIN MONITORING CIRCUIT AND METHOD - A monitoring circuit and method, wherein a voltage waveform having a linear falling edge is applied to a first node of at least one test memory cell (e.g., a plurality of test memory cells connected in parallel). The input voltage at the first node is captured when the output voltage at a second node of the test memory cell(s) rises above a high reference voltage during the falling edge. Then, a difference is determined between the input voltage as captured and either (1) the output voltage at the second node, as captured when the input voltage at the first node falls below the first reference voltage during the falling edge, or (2) a low reference voltage. This difference is proportional to the static noise margin (SNM) of the test memory cell(s) such that any changes in the difference noted with repeated monitoring are indicative of corresponding changes in the SNM. | 08-29-2013 |
20130256748 | PASSIVE DEVICES FOR FINFET INTEGRATED CIRCUIT TECHNOLOGIES - Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A device region is formed in a trench and is coupled with a handle wafer of a semiconductor-on-insulator substrate. The device region extends through a buried insulator layer of the semiconductor-on-insulator substrate toward a top surface of a device layer of the semiconductor-on-insulator substrate. The device region is comprised of lightly-doped semiconductor material. The device structure further includes a doped region formed in the device region and that defines a junction. A portion of the device region is laterally positioned between the doped region and the buried insulator layer of the semiconductor-on-insulator substrate. Another region of the device layer may be patterned to form fins for fin-type field-effect transistors. | 10-03-2013 |
20130270642 | Pseudo Butted Junction Structure for Back Plane Connection - Butted p-n junctions interconnecting back gates in an SOI process, methods for making butted p-n junctions, and design structures. The butted junction includes an overlapping region formed in the bulk substrate by overlapping the mask windows of the ion-implantation masks used to form the back gates. A damaged region may be selectively formed to introduce mid-gap energy levels in the semiconductor material of the overlapping region employing one of the implantation masks used to form the back gates. The damage region causes the butted junction to be leaky and conductively couples the overlapped back gates to each other and to the substrate. Other back gates may be formed that are floating and not coupled to the substrate. | 10-17-2013 |
20140061792 | FIELD EFFECT TRANSISTOR DEVICES WITH RECESSED GATES - A field effect transistor device includes a bulk semiconductor substrate, a fin arranged on the bulk semiconductor substrate, the fin including a source region, a drain region, and a channel region, a first shallow trench isolation (STI) region arranged on a portion of the bulk semiconductor substrate adjacent to the fin, a first recessed region partially defined by the first STI region and the channel region of the fin, and a gate stack arranged over the channel region of the fin, wherein a portion of the gate stack is partially disposed in the first recessed region. | 03-06-2014 |
20140117490 | SEMICONDUCTOR DEVICE INCLUDING ESD PROTECTION DEVICE - A semiconductor device includes a semiconductor-on-insulator (SOI) substrate having a bulk substrate layer, an active semiconductor layer and a buried insulator layer disposed between the bulk substrate layer and the active semiconductor layer. A trench is formed through the SOI substrate to expose the bulk substrate layer. A doped well is formed in an upper region of the bulk substrate layer adjacent trench. The semiconductor device further includes a first doped region different from the doped well that is formed in the trench. | 05-01-2014 |
20140167202 | ELECTROSTATIC DISCHARGE RESISTANT DIODES - A diode and a method for an electrostatic discharge resistant diode. The method includes, for example, receiving a wafer. The wafer includes a silicon layer electrically isolated from a silicon substrate by a buried oxide (BOX) layer. The BOX layer is in physical contact with the silicon layer and the silicon substrate. An N-type well is implanted in the silicon substrate. Furthermore, a vertical column of P+ doped epitaxial silicon and a vertical column of N+ doped epitaxial silicon are formed over the N-type well and extend through the BOX layer and the silicon layer. Both vertical columns may form electrical junctions with the N-type well. | 06-19-2014 |
20140167203 | ELECTROSTATIC DISCHARGE RESISTANT DIODES - A diode and a method for an electrostatic discharge resistant diode. The method includes, for example, receiving a wafer. The wafer includes a silicon layer electrically isolated from a silicon substrate by a buried oxide (BOX) layer. The BOX layer is in physical contact with the silicon layer and the silicon substrate. An N-type well is implanted in the silicon substrate. Furthermore, a vertical column of P+ doped epitaxial silicon and a vertical column of N+ doped epitaxial silicon are formed over the N-type well and extend through the BOX layer and the silicon layer. Both vertical columns may form electrical junctions with the N-type well. | 06-19-2014 |
20140353730 | LOW GATE-TO-DRAIN CAPACITANCE FULLY MERGED FINFET - A low gate-to-drain capacitance merged finFET and methods of manufacture are disclosed. The method includes forming a plurality of fins on a substrate. The method further includes forming at least one dummy gate structure intersecting the plurality of fins. The method further includes forming a gap between sidewalls of the fins and an insulator material, which exposes portions of the substrate. The method further includes merging the fins together with semiconductor material formed within the gaps and over the insulator material. | 12-04-2014 |
20150014773 | Partial FIN On Oxide For Improved Electrical Isolation Of Raised Active Regions - A semiconductor fin suspended above a top surface of a semiconductor layer and supported by a gate structure is formed. An insulator layer is formed between the top surface of the semiconductor layer and the gate structure. A gate spacer is formed, and physically exposed portions of the semiconductor fin are removed by an anisotropic etch. Subsequently, physically exposed portions of the insulator layer can be etched with a taper. Alternately, a disposable spacer can be formed prior to an anisotropic etch of the insulator layer. The lateral distance between two openings in the dielectric layer across the gate structure is greater than the lateral distance between outer sidewalls of the gate spacers. Selective deposition of a semiconductor material can be performed to form raised active regions. | 01-15-2015 |
20150054027 | PASSIVE DEVICES FOR FINFET INTEGRATED CIRCUIT TECHNOLOGIES - Device structures and design structures for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A device region is formed in a trench and is coupled with a handle wafer of a semiconductor-on-insulator substrate. The device region extends through a buried insulator layer of the semiconductor-on-insulator substrate toward a top surface of a device layer of the semiconductor-on-insulator substrate. The device region is comprised of lightly-doped semiconductor material. The device structure further includes a doped region formed in the device region and that defines a junction. A portion of the device region is laterally positioned between the doped region and the buried insulator layer of the semiconductor-on-insulator substrate. Another region of the device layer may be patterned to form fins for fin-type field-effect transistors. | 02-26-2015 |