Patent application number | Description | Published |
20120243599 | Pipelining and Sub-Rate Operation for Memory Links - A system includes a memory hub chip including a Tomlinson-Harashima precoding (THP) equalizer portion operative to perform transmitter equalization at the memory hub chip and send data from to a memory chip. | 09-27-2012 |
20120327995 | Pipelining and Sub-Rate Operation for Memory Links - A method for sending data to a memory chip includes receiving data at a data transmitter disposed on a memory hub chip, applying Tomlinson-Harashima precoding (THP) equalization to the data prior to transmitting the data; and transmitting the data from the transmitter to a memory chip. | 12-27-2012 |
20130135006 | HIGH-SPEED DRIVER CIRCUIT - An inverter-type high speed driver circuit having a first inverter branch and a second inverter branch wherein each of the inverter branches comprising a parallel circuit of a serial connection of a first impedance tuning unit and a respective first clocking transistor and a serial connection of a second impedance tuning unit and a respective second clocking transistor. The impedance tuning units are configured to adapt the conductivity of the respective inverter branch to set the output impedance of the driver circuit and each of the impedance tuning units is controlled in accordance with a data stream. | 05-30-2013 |
20130200934 | DUTY CYCLE ADJUSTMENT CIRCUIT - A duty cycle adjustment circuit includes a clock signal input node; a clock signal output node; a control voltage generation circuit coupled to the clock signal input node; and a first inverter configured to receive an inverter input signal comprising a sum of an input clock signal received at the clock signal input node and a control voltage received from the control voltage generation circuit, and to output an output clock signal at the clock signal output node, wherein variation of the control voltage is configured to vary a duty cycle of the output clock signal. | 08-08-2013 |
20150295736 | CONTINUOUS-TIME LINEAR EQUALIZER FOR HIGH-SPEED RECEIVING UNIT - A continuous-time linear equalizer for use in a receiving unit of a high-speed data transmission system for receiving an input signal includes a signal line configured to provide an equalized output voltage, and an active peaking control unit, including a predetermined first number of active peaking transistors each coupled between the signal line and a power supply rail; a peaking resistor that couples gate terminals of each of the active peaking transistors to the signal line; and a first number of first setting switches each associated with each of the first number of active peaking transistors to activate a predetermined number of the first number of transistors according to first setting signals. | 10-15-2015 |
20150312061 | DECISION-FEEDBACK ANALYZER AND METHODS FOR OPERATING THE SAME - A decision-feedback equalizer for use in a receiving unit of an incoming data stream and for providing a stream of bit data outputs includes a number of comparators configured to perform a comparison related to a number of threshold values and related to a digitalized data sample and to obtain a comparison result; at least one correction block configured to receive the comparison result of a respective one of the comparators and to generate a plurality of intermediate results; and a multiplexer configured to select from the set of intermediate results depending on the output data history to provide the stream of bit data outputs. | 10-29-2015 |
20150312063 | DECISION-FEEDBACK ANALYZER AND METHODS FOR OPERATING THE SAME - A decision-feedback equalizer for use in a receiving unit of an incoming data stream and for providing a stream of bit data outputs includes a number of comparators configured to perform a comparison related to a number of threshold values and related to a digitalized data sample and to obtain a comparison result; at least one correction block configured to receive the comparison result of a respective one of the comparators and to generate a plurality of intermediate results; and a multiplexer configured to select from the set of intermediate results depending on the output data history to provide the stream of bit data outputs. | 10-29-2015 |
20150312064 | CONTINUOUS-TIME LINEAR EQUALIZER FOR HIGH-SPEED RECEIVING UNIT - A continuous-time linear equalizer for use in a receiving unit of a high-speed data transmission system for receiving an input signal includes a signal line configured to provide an equalized output voltage, and an active peaking control unit, including a predetermined first number of active peaking transistors each coupled between the signal line and a power supply rail; a peaking resistor that couples gate terminals of each of the active peaking transistors to the signal line; and a first number of first setting switches each associated with each of the first number of active peaking transistors to activate a predetermined number of the first number of transistors according to first setting signals. | 10-29-2015 |