Patent application number | Description | Published |
20110040932 | Efficient Reduction of Read Disturb Errors in NAND FLASH Memory - Methods and apparatuses for reduction of Read Disturb errors in a NAND FLASH memory system comprise a controller configured to organize FLASH memory devices into blocks, each block having a plurality of pages, and each page defining an individually addressable physical memory location. The controller is further configured to accumulate a Block READ Count corresponding to the number of times any pages in a first block of pages have been read since the first block was last erased. Once the READ count reaches a predetermined number, the controller responds to subsequent READ requests for pages within the first block by moving data associated with a requested page to a page in a second, different block without moving data associated with other pages in the first block, and modifying a logical-to-physical translation table to associate the moved data with the physical address of the page in the second block. | 02-17-2011 |
20120233391 | Efficient Reduction of Read Disturb Errors in NAND FLASH Memory - Methods and apparatuses for reduction of Read Disturb errors in a NAND FLASH memory system comprise a controller configured to organize FLASH memory devices into blocks, each block having a plurality of pages, and each page defining an individually addressable physical memory location. The controller is further configured to accumulate a Block READ Count corresponding to the number of times any pages in a first block of pages have been read since the first block was last erased. Once the READ count reaches a predetermined number, the controller responds to subsequent READ requests for pages within the first block by moving data associated with a requested page to a page in a second, different block without moving data associated with other pages in the first block, and modifying a logical-to-physical translation table to associate the moved data with the physical address of the page in the second block. | 09-13-2012 |
20150113341 | Efficient Reduction of Read Disturb Errors - Methods and apparatuses for reduction of Read Disturb errors in a NAND FLASH memory system comprise a controller configured to organize FLASH memory devices into blocks, each block having a plurality of pages, and each page defining an individually addressable physical memory location. The controller is further configured to accumulate a Block READ Count corresponding to the number of times any pages in a first block of pages have been read since the first block was last erased. Once the READ count reaches a predetermined number, the controller responds to subsequent READ requests for pages within the first block by moving data associated with a requested page to a page in a second, different block without moving data associated with other pages in the first block, and modifying a logical-to-physical translation table to associate the moved data with the physical address of the page in the second block. | 04-23-2015 |
20150127922 | PHYSICAL ADDRESS MANAGEMENT IN SOLID STATE MEMORY - A storage system includes a memory controller connected to a solid state memory device and a read status table that tracks a pending read from the solid state memory device and a physical address of the solid state memory device that is associated with the pending read. The memory controller releases the physical address for reassignment when the read status table indicates that no pending reads are associated with the physical address. In certain embodiments, the read status table may be included within the memory controller. In certain embodiments, subsequent to the release of the physical address, erase operations may erase data at the physical address and the physical address may be reassigned to a new logical address by ensuing host write operations. | 05-07-2015 |
20150161004 | READ BUFFER ARCHITECTURE SUPPORTING INTEGRATED XOR-RECONSTRUCTED AND READ-RETRY FOR NON-VOLATILE RANDOM ACCESS MEMORY (NVRAM) SYSTEMS - According to one embodiment, a system includes a read butter memory configured to store data to support integrated XOR reconstructed data and read-retry data and logic configured to receive data units and read command parameters used to read the data units from a non-volatile random access memory (NVRAM) device, determine which read buffers from the read buffer memory to store the data units, determine an error status for each of the data units, wherein the error status indicates whether each data unit includes errored data or error-free data, store each error-free data unit and the read command parameters to a corresponding read buffer, reject each errored data unit without affecting a corresponding read buffer, and retry to read only errored data units from the NVRAM device until each of the data units is stored in the read buffer memory. | 06-11-2015 |
20150161034 | RECORDING DWELL TIME IN A NON-VOLATILE MEMORY SYSTEM - In at least one embodiment, a data storage system includes a non-volatile memory array, such as a flash memory array, and a controller coupled to the memory array. The controller records, for each of a plurality of valid pages in the memory array, a respective indication of a dwell time of each valid page. | 06-11-2015 |
20150161035 | RETIREMENT OF PHYSICAL MEMORY BASED ON DWELL TIME - In at least one embodiment, a data storage system includes a non-volatile memory array including a plurality of regions of physical memory. The data storage system further includes a controller that controls read and write access to the memory array and retires selected ones of the plurality of regions of physical memory from use. The controller determines whether or to not to retire a particular region among the plurality of regions of physical memory from use based on a dwell time of data stored in the particular region. | 06-11-2015 |
20150161036 | PROGRAMMING NON-VOLATILE MEMORY USING A RELAXED DWELL TIME - In at least one embodiment, a data storage system includes a non-volatile memory array including a plurality of blocks of physical memory, each including multiple pages. The data storage system further includes a controller that maintains a data structure identifying blocks of physical memory in the memory array that currently do not store valid data. The controller, responsive to receipt of a write input/output operation (IOP) specifying an address and write data, selects a particular block from among the blocks identified in the data structure prior to a dwell time threshold for the particular block being satisfied, programs a page within the selected block with the write data, and associates the address with the selected block. | 06-11-2015 |