Patent application number | Description | Published |
20080262818 | Creation of Clock and Data Simulation Vectors with Periodic Jitter - Methods for generating simulation vectors incorporating periodic jitter, or phase-shifted periodic jitter are disclosed. Periodic jitter, such as sinusoidal jitter, is preferably represented by a mathematical equation which defines the amount of jitter experienced at each cycle of a clock or data signal. The calculated periodic jitter for each cycle is used to form a new multi-cycle vector incorporating the jitter. If a particular signal to be simulated additionally needs to travel a particular distance such that it would experience a time delay, that time delay may also be incorporated into the jitter equation as a phase shift. So incorporating the time delay into the jitter equation allows for the easy simulation of circuits receiving the vectors without the need to actually design or “lay out” the circuits that imposing the time delay. This technique is particularly useful in efficient modeling, or optimization of, the clock distribution network and sample circuits used to receive data in a SDRAM integrated circuit. | 10-23-2008 |
20080291063 | Two-bit Tri-Level Forced Transition Encoding - An encoding technique is disclosed for mitigating against the effects of Intersymbol Interference (ISI) and DC creep by forcing data transitions at least every two data bits. Two consecutive bits of data in the original non-return-to-zero (NRZ) data stream are grouped and are converted by an encoding circuit into two new consecutive data bits of the same duration as the original bits. The new encoded bits in each group will necessarily transition between two of three possible data states, and specifically will transition between ‘−1’ and ‘0’ logic states, or ‘+1’ and ‘0’ logic states. Pursuant to this encoding scheme, no more than two consecutive encoded bits will ever be of the same logic state, which prevents any particular data state from predominating and causing DC creep. | 11-27-2008 |
20080304557 | SELF-CALIBRATING CONTINUOUS-TIME EQUALIZATION - Embodiments of the invention comprise a continuous-time equalizer for reducing ISI in data received from a communication channel, and methods and circuitry for tuning or calibrating that equalizer. Selected coefficients for a transfer function of the equalizer circuit are fixed, while other coefficients are tuned by an adaptive algorithm. The adaptive algorithm minimizes errors associated with the tunable coefficients based on one or more training signals sent by the transmitter and received by the equalizer circuit at the receiver. The training signals allow for a variety of error terms to be calculated, from which the tunable coefficients are updated so as to iteratively minimize the error terms and simultaneously tune the equalizer to more accurately compensate for the degrading effects of the channel. | 12-11-2008 |
20090010320 | Fractional-Rate Decision Feedback Equalization Useful in a Data Transmission System - Decision feedback equalization (DFE) circuits are disclosed for use with fractional-rate clocks of lesser frequency than the data signal. For example, a one-half-rate clocked DFE circuit utilizes two input data paths, which are respectively activated on rising and falling edges of an associated half-rate clock. Each of the input data paths has a pair of comparators with differing reference voltage levels. The comparators in each input data path output to a multiplexer, which picks between the two comparator outputs depending on the logic level of the previously received bit. The output of each input data path is sent as a control input to the multiplexer of the other data path. Thus, the results from previously-detected bits affect which comparator's output is passed to the output of the circuit, even though the synchronizing clock is half the frequency of the data. A quarter-rate DFE circuit is also disclosed which operates similarly. | 01-08-2009 |
20090063111 | JITTERY SIGNAL GENERATION WITH DISCRETE-TIME FILTERING - The disclosed computer-implementable method allows for the fast creation of a multi-unit interval data signal suitable for simulation. The created signal represents the output of an otherwise ideal Discrete Time Filter (DTF) circuit, and the quick creation of the signal merely requires a designer to input the number of taps and their weights without the need of laying out or considering the circuitry of the DTF. A matrix is created based on a given data stream, and the number of taps and weights, which matrix is processed to create the multi-unit-interval data signal. Noise and jitter can be added to the created signal such that it now realistically reflects non-idealities common to actual systems. The signal can then be simulated using standard computer-based simulation techniques. For example, the transmission of the created signal can be simulated down a channel having a particular transfer function. If the DTF parameters (number and weight of taps) used to create the signal were designed to counter the channel's transfer function, the simulation can reveal how successful the original DTF parameters were, and hence whether the DTF needs modification. | 03-05-2009 |
20090092180 | EQUALIZER CIRCUITRY FOR MITIGATING PRE-CURSOR AND POST-CURSOR INTERSYMBOL INTERFERENCE - One or more embodiments of the invention comprise a continuous-time equalizer (CTE) for reducing both pre-cursor and post-cursor intersymbol interference (ISI) from data received from a communication channel. One such equalizer comprises two independent stages that process the input signal in parallel. One stage subtracts a scaled version of the derivative of the input signal from a scaled version of the input signal to reduce pre-cursor ISI from the input signal. The other stage adds a scaled version of the derivative of the input signal to a scaled version of the input signal to reduce post-cursor ISI from the input signal. The outputs from the two stages are then multiplied to arrive at an output signal in which both pre- and post-cursor ISI is minimized. Because the scalars used in each of the stages are independent, each can be adjusted for greater manipulation of the ISI-reduced signal. | 04-09-2009 |
20090094302 | Incorporating Noise and/or Jitter into Waveform Generation - One or more embodiments are disclosed that involve computer implementable techniques for generating simulate-able waveforms without the need for repeatedly including and simulating a full channel model or testing the waveforms on a physical channel. Techniques according to such embodiments the invention comprise simulating the sending of a waveform across a channel and recording deviations from a simulated received waveform, which comprise differences between the ideal waveform as sent and the simulated received waveform. These deviations are then used to create simulate-able waveforms, which include the effects of noise and jitter, without the need for additional channel simulation. As an alternative to using channel simulation, deviations may also be collected from sending a waveform across a physical channel. Thus, a received signal sent across the physical channel may be sampled at sample points to record deviations, which are then used to create simulate-able waveforms without sending additional signals across the physical channel. Other embodiments include deriving and recording signal deviations from a simulated or measured system pulse response, and tabulating the deviations in the system pulse response when it occurs within a set of pre-determined bit patterns. | 04-09-2009 |
20090110116 | METHOD AND APPARATUS FOR TRAINING THE REFERENCE VOLTAGE LEVEL AND DATA SAMPLE TIMING IN A RECEIVER - Methods and apparatuses for calculating the location of an optimal sampling point for a receiver system are disclosed. In brief, a first method comprises determining a maximum voltage margin and a maximum timing margin of a received signal, and from these margins, determining an optimal sampling point, which includes a reference voltage level (Vref) and a relative sample phase. The location of the optimal sampling point is based on the locations of the sampling point of the maximum voltage margin and the sampling point of the maximum timing margin. A second method comprises establishing an initial sampling point, and then successively refining each of the voltage and timing components of the sampling point until an optimal sampling point is reached. | 04-30-2009 |
20090112549 | TECHNIQUES FOR GENERATING AND SIMULATING A SIMULATABLE VECTOR HAVING AMPLITUDE NOISE AND/OR TIMING JITTER ADDED THERETO - Methods for generating realistic waveform vectors with controllable amplitude noise and timing jitter, simulatable in a computer-based simulation environment are disclosed. In one implementation, a transition vector is created from a sequence of bits having a rise time and a fall time, in which the transition vector comprises voltage values at timings corresponding to midpoints of transitions in the bit sequence. A jittered transition vector is created from the transition vector, in which the timing of the transitions in the jittered transition vector include timing jitter. An upscaled jittered transition vector is then formed having additional points, in which at least some of the additional points comprise corners of the sequence of bits. The voltages of the additional points are set by the sequence of bits, and the timing of the corners are set in accordance with the rise time and the fall time. Although this resulting vector can be simulated, this vector can also be re-sampled to produce a new simulatable vector in which the voltages are separated by a constant time step. | 04-30-2009 |
20090112551 | MATRIX MODELING OF PARALLEL DATA STRUCTURES TO FACILITATE DATA ENCODING AND/OR JITTERY SIGNAL GENERATION - One or more embodiments of the disclosed computer-implementable method comprise a matrix-based approach to generating in parallel a plurality of realistic simulatable signal vectors, which vectors include the addition of amplitude noise and/or timing jitter and encoding. For example, each channel in a parallel bus can be populated in a matrix, with each row comprising ideal voltage values for the channel, and the columns comprising bits of the sequence of voltage values for that channel. Thereafter, encoding can be employed to modify the data in the matrix. Amplitude noise and/or timing jitter can then be applied to each channel (row) in the matrix. This modifies the time basis from a bit basis as used in the matrix to a time-step basis. With such modification accomplished, each row in the matrix can be transformed into simulatable vector, which vectors can then be simulated in parallel to test, for example, the robustness of the parallel bus of which the channels are part. | 04-30-2009 |
20090157376 | Techniques for Incorporating Timing Jitter and/or Amplitude Noise into Hardware Description Language-based Input Stimuli - Methods for generating waveforms with realistic transitions, controllable timing jitter, and controllable amplitude noise in a computer-based simulation environment are disclosed. A first method includes obtaining signal information for one or more parallel data signals. In one embodiment, signal information for the one or more parallel data signals is mapped from an HDL format to a new time scale, and during this operation, timing jitter is added independently to the parallel data signals. These jittery parallel data signals may then be returned to the original HDL format, or another format, for simulation. In another embodiment, rather than mapping to a single time vector, information from each signal is modified to have a time scale commensurate with noise and jitter to be added. Timing jitter is superimposed onto each transition, rise and fall times are incorporated, and missing voltage and timing information for each data signal is interpolated into vectors representing the signals. Each data signal may additionally be scaled to one or more true voltage values and filtered. Finally, amplitude noise is added to each signal, and one or more final signals are output to a desired format for simulation. | 06-18-2009 |
20090238300 | MULTI-LEVEL SIGNALING FOR LOW POWER, SHORT CHANNEL APPLICATIONS - Apparatus are disclosed, such as those involving a transmitter circuit that is configured to generate multi-level signals based on a plurality of data digits. One such transmitter circuit includes a signal output and an encoder configured to provide control signals based at least partially on the plurality of data digits. The transmitter circuit also includes a first set of switches configured to receive one or more of the control signals, and to selectively conduct a first or second voltage reference to the signal output. The transmitter circuit further includes first and second voltage drop circuits that provide third and fourth voltage references, respectively. The third and fourth voltage references have voltage levels between those of the first and second voltage references. The transmitter circuit also includes a second set of switches configured to receive one or more of the control signals, and selectively conduct the third or fourth voltage reference to the signal output. | 09-24-2009 |
20090239559 | MIXED-MODE SIGNALING - Methods and apparatus are disclosed, such as those involving mixed-mode signaling that includes transmitting a differential signal and a common mode signals over the same pair of interconnect traces. One such apparatus includes a first transmitter configured to transmit a differential signal through a pair of electrically conductive lines in a first direction. The differential signal has a first frequency and carries electronic data. The apparatus further includes a second transmitter configured to transmit a common mode signal through the pair of electrically conductive lines in the first direction. The common mode signal is superimposed onto each of the differential signal. The common mode signal has a second frequency that is lower than the first frequency and carries a control signal. This configuration reduces the number of lines and pins on electronic circuits, thereby saving space thereon. | 09-24-2009 |
20090261859 | RECEIVER CIRCUITRY FOR RECEIVING REDUCED SWING SIGNALS FROM A CHANNEL - A receiver for receiving a reduced swing signal from a transmission channel is disclosed, in which the swing of the reduced swing signal is less than the power supply of the receiver and possibly is less than the power supply of the transmitter. The receiver comprises a level shifter for offsetting the reduced swing signal, and an amplifier which receives both the reduced swing signal and its offset to produce a full swing signal output referenced to the power supply of the receiver. The full swing signal can thereafter be buffered, and eventually can be captured by a clock. Optionally, the disclosed reduced swing receiver also contains calibration circuitry for improving the integrity of the full swing signal output, and in particular for countering the effects of process, and in some embodiments temperature, variations, which alter the characteristics of the transistors which make up the receiver circuitry. More particularly, the calibration circuitry compensates for the unbalanced way in which process and temperature variations impact transistors of differing polarities (e.g., n-type and p-type). | 10-22-2009 |
20090313521 | DATA BUS INVERSION USABLE IN A MEMORY SYSTEM - Implementations of Data Bus Inversion (DBI) techniques within a memory system are disclosed. In one embodiment, a set of random access memory (RAM) integrated circuits (ICs) is separated from a logic system by a bus. The logic system can contain many of the logic functions traditionally performed on conventional RAM ICs, and accordingly the RAM ICs can be modified to not include such logic functions. The logic system, which can be a logic integrated circuit intervening between the modified RAM ICs and a traditional memory controller, additionally contains DBI encoding and decoding circuitry. In such a system, data is DBI encoded and at least one DBI bit issued when writing to the modified RAM ICs. The RAM ICs in turn store the DBI bit(s) with the encoded data. When the encoded data is read from the modified RAM ICs, it is transmitted across the bus in its encoded state along with the DBI bit(s). The logic integrated circuit then decodes the data using the DBI bit(s) to return it to its original state. | 12-17-2009 |
20100001789 | SYSTEMS AND METHODS FOR LOWERING INTERCONNECT CAPACITANCE THROUGH ADJUSTMENT OF RELATIVE SIGNAL LEVELS - Methods and circuitry for lowering the capacitance of interconnects, particularly Through Wafer Interconnects (TWIs), using signal level adjustment are disclosed. Embodiments of the invention seek to bias the midpoint voltage level of the signals on the TWIs towards inversion, where at high frequencies capacitance is at its minimum. In one embodiment, reduced swing signals are used for the data states transmitted across the TWIs, in which the reduced swing signals use a midpoint voltage level tending to bias the TWI capacitance towards inversion. In another embodiment, signals are AC coupled to the TWI where they are referenced to an explicit bias voltage directly connected to the TWI. This allows signals to propagate through the TWI while the TWI is biased towards inversion. In a third embodiment, the potential of the substrate is explicitly lowered with respect to the TWI potential. Regardless of the particular embodiment used, raising the midpoint-voltage level of the signals on the TWIs relative to the substrate decreases capacitance, which increases the frequency of the data which can propagate through the TWIs while potentially reducing the signaling power. | 01-07-2010 |
20100102853 | Circuitry and Methods Minimizing Output Switching Noise Through Split-Level Signaling and Bus Division Enabled by a Third Power Supply - Disclosed herein are circuitry and methods for transmitting data across a parallel bus using both high common mode and low common mode signaling. The transmitter stages are configured to work with two of three possible power supply voltages: a high Vddq voltage, a low Vssq voltage, and an intermediate Vx voltage. In one embodiment, the odd numbered transmitter stages, that drive the odd numbered outputs to the bus, use the Vddq and Vx supplies, such that the odd numbered outputs comprise high common mode signals. The even numbered transmitter stages, that drive the even numbered outputs to the bus, use the Vx and Vssq supplies, such that the even numbered outputs comprise low common mode signals. With the transmitter and power supplies so configured, no one of the three power supplies must source or sink current to or from more than half of the transmitters at any given time, which reduces power supply loading and minimizes switching noise. As a result, use of the technique may dispense with the need to provide power supply isolation at the transmitters. | 04-29-2010 |
20100127758 | APPARATUS FOR BYPASSING FAULTY CONNECTIONS - Apparatus are disclosed, such as those involving a 3-D integrated circuit. One such apparatus includes a first die including a plurality of vertical connectors formed therethrough. The apparatus also includes a first circuit configured to encode multiple data bits into a multi-bit symbol, and provide the multi-bit symbol to two or more of the vertical connectors. The apparatus further includes a second circuit configured to receive the multi-bit symbol from at least one of the two or more vertical connectors, and decode the multi-bit symbol into the multiple data bits. The apparatus provides enhanced repairability with no or less redundant vertical connectors, thus avoiding the need for “on the fly” or field repair of defective vertical connectors. | 05-27-2010 |
20100188058 | Reference Voltage Generation for Single-Ended Communication Channels - An improved reference voltage (Vref) generator useable, for example, in sensing data on single-ended channels is disclosed. The Vref generator can be placed on the integrated circuit containing the receivers, or may be placed off chip. In one embodiment, the Vref generator comprises an adjustable-resistance voltage divider in combination with a current source. The voltage divider is referenced to I/O power supplies Vddq and Vssq, with Vref being generated at a node intervening between the adjustable resistances of the voltage divider. The current source injects a current into the Vref node and into a non-varying Thevenin equivalent resistance formed of the same resistors used in the voltage divider. So constructed, the voltage generated equals the sum of two terms: a first term comprising the slope between Vref and Vddq, and a second term comprising a Vref offset. Each of these terms can be independently adjusted in first and second modes: the slope term via the voltage divider, and the offset term by the magnitude of the injected current. Use of the disclosed Vref generator in one useful implementation allows Vref to be optimized at two different values for Vddq. | 07-29-2010 |
20100198575 | Generation and Manipulation of Realistic Signals for Circuit and System Verification - Methods for generating realistic waveforms with controllable voltage noise and timing jitter in a computer-based simulation environment and the simulation of a subset of those waveforms with system elements along the signal path is disclosed. By deriving a generic, re-useable, parameterized Fourier series, time-domain clock and pseudo-random data signals are generated from a subset of their true harmonic components. Time-domain signal parameters including high, low, and common-mode voltage levels, transition slew-rates, transition timing, period and/or frequency, may be designated by the user, and the computer calculates the harmonic components that will combine through the inverse Fourier transform to provide the required time-domain characteristics. By computing the frequency content of the signal directly it is possible to simulate the interaction of the signal with various system blocks while remaining in the frequency domain, thereby reducing simulation time and memory requirements. By allowing the parameters of the signal model to vary on a cycle-to-cycle basis, signal characteristics such as voltage noise and timing jitter may be modeled with flexibility and precision down to the numerical limitations of the simulator. | 08-05-2010 |
20100199017 | Data Encoding Using Spare Channels in a Memory System - Implementations of encoding techniques are disclosed. The encoding technique, such as a Data bus Inversion (DBI) technique, is implementable in a vertically-stacked memory module, but is not limited thereto. The module can be a plurality of memory integrated circuits which are vertically stacked, and which communicate via a bus formed in one embodiment of channels comprising Through-Wafer Interconnects (TWIs), but again is not limited thereto. One such module includes spare channels that are normally used to reroute a data signal on the bus away from faulty data channels. In one disclosed technique, the status of a spare channel or channels is queried, and if one or more are unused, they can be used to carry a DBI bit, thus allowing at least a portion of the bus to be assessed in accordance with a DBI algorithm. Depending on the location and number of spare channels needed for rerouting, DBI can be apportioned across the bus in various manners. Implementations can also be used with other encoding techniques not comprising DBI. | 08-05-2010 |
20100214138 | Balanced Data Bus Inversion - A method and apparatus for balancing an output load using data bus inversion is disclosed. In brief, one such technique comprises measuring the “balance” of data bits across a data bus (e.g., the number of zero values compared to the number of one values in a set of parallel data bits). If the data bits are unbalanced by a specified amount, a portion of the bits on the data bus are inverted, and the data bits, including the inverted portion, are transmitted. Also, a data bus inversion bit is set to a particular value and transmitted with the data bits to indicate that data bus inversion was used. If the data signal is not unbalanced (i.e., the bits on the data bus do not comprise an unbalanced number of logic values), then the bits on the data bus are transmitted as they are detected, and the data bus inversion bit is set to another particular value to indicate that data bus inversion was not used. | 08-26-2010 |
20100231260 | Receiver Circuitry for Receiving Reduced Swing Signals From a Channel - A receiver for receiving a reduced swing signal from a transmission channel is disclosed, in which the swing of the reduced swing signal is less than the power supply of the receiver and possibly is less than the power supply of the transmitter. The receiver comprises a level shifter for offsetting the reduced swing signal, and an amplifier which receives both the reduced swing signal and its offset to produce a full swing signal output referenced to the power supply of the receiver. The full swing signal can thereafter be buffered, and eventually can be captured by a clock. Optionally, the disclosed reduced swing receiver also contains calibration circuitry for improving the integrity of the full swing signal output, and in particular for countering the effects of process, and in some embodiments temperature, variations, which alter the characteristics of the transistors which make up the receiver circuitry. More particularly, the calibration circuitry compensates for the unbalanced way in which process and temperature variations impact transistors of differing polarities (e.g., n-type and p-type). | 09-16-2010 |
20100283503 | REFERENCE VOLTAGE CIRCUITS AND ON-DIE TERMINATION CIRCUITS, METHODS FOR UPDATING THE SAME, AND METHODS FOR TRACKING SUPPLY, TEMPERATURE, AND/OR PROCESS VARIATION - Devices and methods for operating devices are provided, such as those that include a memory device having a reference voltage (Vref) circuit that has substantially similar paths and impedances as an on-die termination (ODT) circuit. One such Vref circuit tracks supply variations and temperature changes in a manner substantially similar to the ODT circuit. In some embodiments an update scheme is provide for the ODT circuit and the Vref circuit to enable simultaneous update of each circuit through the same digital codes. | 11-11-2010 |
20110012665 | Systems and Methods for Lowering Interconnect Capacitance Through Adjustment of Relative Signal Levels - Methods and circuitry for lowering the capacitance of interconnects, particularly Through Wafer Interconnects (TWIs), using signal level adjustment are disclosed. Embodiments of the invention seek to bias the midpoint voltage level of the signals on the TWIs towards inversion, where at high frequencies capacitance is at its minimum. In one embodiment, reduced swing signals are used for the data states transmitted across the TWIs, in which the reduced swing signals use a midpoint voltage level tending to bias the TWI capacitance towards inversion. In another embodiment, signals are AC coupled to the TWI where they are referenced to an explicit bias voltage directly connected to the TWI. This allows signals to propagate through the TWI while the TWI is biased towards inversion. In a third embodiment, the potential of the substrate is explicitly lowered with respect to the TWI potential. Regardless of the particular embodiment used, raising the midpoint-voltage level of the signals on the TWIs relative to the substrate decreases capacitance, which increases the frequency of the data which can propagate through the TWIs while potentially reducing the signaling power. | 01-20-2011 |
20110096825 | Fractional-Rate Decision Feedback Equalization Useful in a Data Transmission System - Decision feedback equalization (DFE) circuits are disclosed for use with fractional-rate clocks of lesser frequency than the data signal. For example, a one-half-rate clocked DFE circuit utilizes two input data paths, which are respectively activated on rising and falling edges of an associated half-rate clock. Each of the input data paths has a pair of comparators with differing reference voltage levels. The comparators in each input data path output to a multiplexer, which picks between the two comparator outputs depending on the logic level of the previously received bit. The output of each input data path is sent as a control input to the multiplexer of the other data path. Thus, the results from previously-detected bits affect which comparator's output is passed to the output of the circuit, even though the synchronizing clock is half the frequency of the data. A quarter-rate DFE circuit is also disclosed which operates similarly. | 04-28-2011 |
20110193620 | Reference Voltage Generator for Single-Ended Communication Systems - An improved reference voltage (Vref) generator for a single-ended receiver in a communication system is disclosed. The Vref generator in one example comprises a cascoded current source for providing a current, I, to a resistor, Rb, to produce the Vref voltage (I*Rb). Because the current source isolates Vref from a first of two power supplies, Vref will vary only with the second power supply coupled to Rb. As such, the improved Vref generator is useful in systems employing signaling referenced to that second supply but having decoupled first supplies. For example, in a communication system in which the second supply (E.g. Vssq) is common to both devices, but the first supply (Vddq) is not, the disclosed Vref generator produces a value for Vref that tracks Vssq but not the first supply. This improves the sensing of Vssq-referenced signals in such a system. | 08-11-2011 |
20110222623 | Communication Interface With Configurable Encoding Based on Channel Termination - An improved data transmission system is disclosed in which data encoding such as Data Bus Inversion (DBI) in a transmitting device is matched to the termination scheme being used in a receiving device. In the improved system, the transmitting device is able to automatically discover the termination scheme being used in the receiving device, and is thereby able to automatically implement a data-encoding algorithm to best match the termination scheme being used. In one example, Information concerning the termination scheme can be communicated to the transmitting device via a control channel, or another channel otherwise dedicated to data encoding such as a DBI channel. In another example, the transmitting device can infer the termination scheme being used via measurements, or by understanding how the receiving device will modify its termination scheme given current data transmission conditions. Alternatively, the receiving device is able to discover the data encoding scheme used in the transmitting device and is able to configure its termination circuitry accordingly. | 09-15-2011 |
20110224960 | Jittery Signal Generation with Discrete-Time Filtering - The computer-implementable method allows for the fast creation of a multi-unit interval data signal suitable for simulation. The created signal represents the output of an otherwise ideal Discrete Time Filter (DTF) circuit, and the quick creation of the signal merely requires a designer to input the number of taps and their weights without the need of laying out or considering the circuitry of the DTF. A matrix is created based on a given data stream, and the number of taps and weights, which matrix is processed to create the multi-unit-interval data signal. Noise and jitter can be added to the created signal such that it now realistically reflects non-idealities common to actual systems. The signal can then be simulated using standard computer-based simulation techniques. | 09-15-2011 |
20110274215 | Method and Apparatus for Training the Reference Voltage Level and Data Sample Timing in a Receiver - Methods and apparatuses for calculating the location of an optimal sampling point for a receiver system are disclosed. In brief, a first method comprises determining a maximum voltage margin and a maximum timing margin of a received signal, and from these margins, determining an optimal sampling point, which includes a reference voltage level (Vref) and a relative sample phase. The location of the optimal sampling point is based on the locations of the sampling point of the maximum voltage margin and the sampling point of the maximum timing margin. A second method comprises establishing an initial sampling point, and then successively refining each of the voltage and timing components of the sampling point until an optimal sampling point is reached. | 11-10-2011 |
20110316726 | LOW POWER MULTI-LEVEL SIGNALING - Apparatus are disclosed, such as those involving a transmitter circuit that is configured to generate multi-level signals based on a plurality of data digits. One such transmitter circuit includes a signal output and an encoder configured to provide control signals based at least partially on the plurality of data digits. The transmitter circuit also includes a first set of switches configured to receive one or more of the control signals, and to selectively conduct a first or second voltage reference to the signal output. The transmitter circuit further includes first and second voltage drop circuits that provide third and fourth voltage references, respectively. The third and fourth voltage references have voltage levels between those of the first and second voltage references. The transmitter circuit also includes a second set of switches configured to receive one or more of the control signals, and selectively conduct the third or fourth voltage reference to the signal output. | 12-29-2011 |
20120016650 | Simulating the Transmission and Simultaneous Switching Output Noise of Signals in a Computer System - Methods implementable in a computer system for simulating the transmission of signals across a plurality of data channels (bus) are disclosed. The disclosed techniques simulate the effects of Intersymbol Interference (ISI), cross talk, and Simultaneous Switching Output (SSO) noise by generating Probability Distribution Functions (PDFs) for each. The resulting PDFs are convolved to arrive at a total PDF indicative of the reception of data subject to each of these non-idealities. The total PDF, and its underlying terms, can be indexed to particular channels of the bus as well as to particular logic states. Use of the disclosed technique allows bit error rates and sensing margins to be determined with minimal computation and simulation. | 01-19-2012 |
20120016651 | Simulating the Transmission of Asymmetric Signals in a Computer System - Methods implementable in a computer system for simulating the transmission of signals are disclosed. The disclosed techniques simulate the effect of the transmitter as well as the channel on a positive and negative pulse, which assures that asymmetry in the transmitter is captured. The resulting positive and negative pulse responses are then used to generate two separate PDFs: one indicative of received logic ‘1’s and another indicative of received logic ‘0’s at a point in time. Generating a plurality of such PDFs at different times allows the reliability of data reception to be assessed, and appropriate sensing margins to be set at a receiver, without the need to simulate the transmission of a very long random stream of data bits. | 01-19-2012 |
20120176152 | Circuitry and Method Minimizing Output Switching Noise Through Split-Level Signaling and Bus Division Enabled by a Third Power Supply - Disclosed herein are circuitry and methods for transmitting data across a parallel bus using both high common mode and low common mode signaling. The transmitter stages are configured to work with two of three possible power supply voltages: a high Vddq voltage, a low Vssq voltage, and an intermediate Vx voltage. In one embodiment, the odd numbered transmitter stages, that drive the odd numbered outputs to the bus, use the Vddq and Vx supplies, such that the odd numbered outputs comprise high common mode signals. The even numbered transmitter stages, that drive the even numbered outputs to the bus, use the Vx and Vssq supplies, such that the even numbered outputs comprise low common mode signals. | 07-12-2012 |
20120179434 | Recursive Summation Algorithms Useful for Statistical Signal Analysis of Transmission of Signals in a Computer System - Computer-implementable recursive summation algorithms are disclosed that are useful for efficiently performing recursive convolution, such as is often required in Statistical Signal Analysis (SSA) techniques. The disclosed recursive summation algorithms can be more computationally-efficient from both a speed and memory perspective than other recursive convolution techniques known in the prior art, such as the techniques relying on Fast Fourier Transforms (FFTs). | 07-12-2012 |
20120306668 | APPARATUS FOR BYPASSING FAULTY CONNECTIONS - Apparatus are disclosed, such as those involving a 3-D integrated circuit. One such apparatus includes a first die including a plurality of vertical connectors formed therethrough. The apparatus also includes a first circuit configured to encode multiple data bits into a multi-bit symbol, and provide the multi-bit symbol to two or more of the vertical connectors. The apparatus further includes a second circuit configured to receive the multi-bit symbol from at least one of the two or more vertical connectors, and decode the multi-bit symbol into the multiple data bits. The apparatus provides enhanced repairability with no or less redundant vertical connectors, thus avoiding the need for “on the fly” or field repair of defective vertical connectors. | 12-06-2012 |
20130018646 | TIME-DOMAIN SIGNAL GENERATION - Methods and apparatus disclosed herein operate to receive a plurality of cycles characterized by a set of time-domain aspects, to modify at least one of the time-domain aspects of at least some of the plurality of cycles to produce a plurality of modified cycles, to process at least some of the modified cycles to produce time-domain cycles, and to create a time-domain signal based at least in part on concatenating the time-domain cycles. | 01-17-2013 |
20130022137 | ASYMMETRIC CHIP-TO-CHIP INTERCONNECT - Methods and apparatus to transfer data between a first device and a second device, is disclosed. An apparatus according to various embodiments may comprise a first device and a second device. The first device may comprise at least one first non-differential transmitter coupled to a first channel, at least one second non-differential transmitter coupled to a second channel, and at least one differential receiver to receive a data bit and its complement on the first and second channels in parallel. The second device may comprise at least one first non-differential receiver coupled to the first channel, at least one second non-differential receiver coupled to the second channel, and at least one differential transmitter to transmit a data bit and its complement on the first and second channels in parallel. | 01-24-2013 |
20130038346 | APPARATUS AND METHOD FOR SIGNAL TRANSMISSION OVER A CHANNEL - Apparatus and methods related to data transmission are disclosed. One such apparatus includes a transmitter, a receiver, and a channel. The transmitter includes a pair of current sources and a pair of switches. Each of the switches conducts one of the current sources to the channel in response to input data. The receiver includes a first node configured to receive a signal over the channel. The receiver also includes a resistance generating a voltage drop between the first node and a second node. The receiver further includes a first transistor and a second transistor that are together configured to provide a voltage level to the second node based at least partly on the voltage drop. The resistance provides a negative feedback to center the mean signal level, thereby reducing intersymbol interference. | 02-14-2013 |
20130043900 | ADJUSTABLE DATA DRIVERS AND METHODS FOR DRIVING DATA SIGNALS - Apparatuses and methods for driving input data signals onto signal lines as output data signals are disclosed. An example apparatus includes a detection circuit, a driver adjust circuit, and a data driver. The detection circuit is configured to detect a characteristic(s) of a group of input data signals to be driven onto adjacent signal lines. A characteristic could be, for example, a particular combination of logic levels and/or transitions for, the group of input data signals. The driver adjust circuit is configured to provide a driver adjustment signal based at least in part on a detection signal, that is provided by the detection circuit. A data driver is configured to drive a respective one of the group of input data signals as a respective one of the output data signals, wherein the data driver is adjusted based at least in part on the driver adjustment signal. | 02-21-2013 |
20130128994 | MIXED-MODE SIGNALING - Methods and apparatus are disclosed, such as those involving mixed-mode signaling that includes transmitting a differential signal and a common mode signals over the same pair of interconnect traces. One such apparatus includes a first transmitter configured to transmit a differential signal through a pair of electrically conductive lines in a first direction. The differential signal has a first frequency and carries electronic data. The apparatus further includes a second transmitter configured to transmit a common mode signal through the pair of electrically conductive lines in the first direction. The common mode signal is superimposed onto each of the differential signal. The common mode signal has a second frequency that is lower than the first frequency and carries a control signal. This configuration reduces the number of lines and pins on electronic circuits, thereby saving space thereon. | 05-23-2013 |
20130194032 | APPARATUSES AND METHODS FOR PROVIDING CAPACITANCE IN A MULTI-CHIP MODULE - Apparatuses, multi-chip modules, capacitive chips, and methods of providing capacitance to a power supply voltage in a multi-chip module are disclosed. In an example multi-chip module, a signal distribution component may be configured to provide a power supply voltage. A capacitive chip may be coupled to the signal distribution component and include a plurality of capacitive units. The capacitive chip may be configured to provide a capacitance to the power supply voltage. The plurality of capacitive units may be formed from memory cell capacitors. | 08-01-2013 |
20130307708 | METHODS AND APPARATUSES FOR LOW-POWER MULTI-LEVEL ENCODED SIGNALS - Methods and apparatuses for providing multi-level encoded signals are disclosed. An apparatus may include an encoding circuit and a multi-level encoder. The encoding circuit may be configured to receive data and provide encoded data based, at least in part on the data. The multi-level encoder may be coupled to the encoding circuit and configured to receive the encoded data. The multi-level encoder may be further configured to provide the encoded data to a bus as multi-level signal responsive, at least in part, to receipt of the encoded data. | 11-21-2013 |
20140078815 | VOLTAGE RAIL NOISE SENSING CIRCUIT AND METHOD - Apparatus and methods level shift a direct current (DC) component of a voltage rail signal from a first DC level to a second DC level such that voltage rail noise can be determined. The actual voltage rail noise can be compared to an expected amount of noise for analysis and validation of simulation models. Such assessment can be used to validate simulation models used to refine a design of an integrated circuit or as part of built-in self test. | 03-20-2014 |
20140320201 | APPARATUSES AND METHODS FOR PROVIDING CAPACITANCE IN A MULTI-CHIP MODULE - Apparatuses, multi-chip modules, capacitive chips, and methods of providing capacitance to a power supply voltage in a multi-chip module are disclosed. In an example multi-chip module, a signal distribution component may be configured to provide a power supply voltage. A capacitive chip may be coupled to the signal distribution component and include a plurality of capacitive units. The capacitive chip may be configured to provide a capacitance to the power supply voltage. The plurality of capacitive units may be formed from memory cell capacitors. | 10-30-2014 |
20150022383 | METHODS AND APPARATUSES FOR LOW-POWER MULTI-LEVEL ENCODED SIGNALS - Methods and apparatuses for providing multi-level encoded signals are disclosed. An apparatus may include an encoding circuit and a multi-level encoder. The encoding circuit may be configured to receive data and provide encoded data based, at least in part on the data. The multi-level encoder may be coupled to the encoding circuit and configured to receive the encoded data. The multi-level encoder may be further configured to provide the encoded data to a bus as multi-level signal responsive, at least in part, to receipt of the encoded data. | 01-22-2015 |
20150067197 | DATA PATTERN GENERATION FOR I/O TRAINING AND CHARACTERIZATION - A memory structure that can perform characterization of output data paths without accessing the main memory array includes: a plurality of output data paths; a plurality of registers coupled to the output data paths. The registers include: at least a first pattern register and a second pattern register, for respectively storing a first data pattern and a second data pattern; and at least a first mapping register, for storing a plurality of binary values, wherein each binary value indicates whether the first data pattern or the second data pattern should be mapped to a corresponding output data path. | 03-05-2015 |
20150070052 | REFERENCE VOLTAGE GENERATOR FOR SINGLE-ENDED COMMUNICATION SYSTEMS - An improved reference voltage (Vref) generator for a single-ended receiver in a communication system is disclosed. The Vref generator in one example comprises a cascoded current source for providing a current, I, to a resistor, Rb, to produce the Vref voltage (I*Rb). Because the current source isolates Vref from a first of two power supplies, Vref will vary only with the second power supply coupled to Rb. As such, the improved Vref generator is useful in systems employing signaling referenced to that second supply but having decoupled first supplies. For example, in a communication system in which the second supply (E.g. Vssq) is common to both devices, but the first supply (Vddq) is not, the disclosed Vref generator produces a value for Vref that tracks Vssq but not the first supply. This improves the sensing of Vssq-referenced signals in such a system. | 03-12-2015 |