Patent application number | Description | Published |
20110060441 | Clustering for Prediction Models in Process Control and for Optimal Dispatching - A first embodiment is a method for semiconductor process control comprising clustering processing tools of a processing stage into a tool cluster based on processing data and forming a prediction model for processing a semiconductor wafer based on the tool cluster. A second embodiment is a method for semiconductor process control comprising providing cluster routes between first stage tool clusters and second stage tool clusters, assigning a comparative optimization ranking to each cluster route, and scheduling processing of wafers. The comparative optimization ranking identifies comparatively which cluster routes provide for high wafer processing uniformity. Further, wafers that require high wafer processing uniformity are scheduled to be processed along one cluster route that has a high comparative optimization ranking that identifies the one cluster route to have a highest wafer processing uniformity, and wafers that do not require high wafer processing uniformity are scheduled to be processed along another cluster route. | 03-10-2011 |
20110186987 | STRESS BUFFER STRUCTURES IN A MOUNTING STRUCTURE OF A SEMICONDUCTOR DEVICE AND METHODS OF MANUFACTURING THE SAME - A mounting structure for a semiconductor device includes a stepwise stress buffer layer under a likewise stepwise UBM structure. | 08-04-2011 |
20110241201 | Radiate Under-Bump Metallization Structure for Semiconductor Devices - An under-bump metallization (UBM) structure for a semiconductor device is provided. The UBM structure has a center portion and extensions extending out from the center portion. The extensions may have any suitable shape, including a quadrangle, a triangle, a circle, a fan, a fan with extensions, or a modified quadrangle having a curved surface. Adjacent UBM structures may have the respective extensions aligned or rotated relative to each other. Flux may be applied to a portion of the extensions to allow an overlying conductive bump to adhere to a part of the extensions. | 10-06-2011 |
20120305916 | Interposer Test Structures and Methods - An embodiment of the disclosure is a structure comprising an interposer. The interposer has a test structure extending along a periphery of the interposer, and at least a portion of the test structure is in a first redistribution element. The first redistribution element is on a first surface of a substrate of the interposer. The test structure is intermediate and electrically coupled to at least two probe pads. | 12-06-2012 |
20130092935 | Probe Pad Design for 3DIC Package Yield Analysis - An interposer includes a first surface on a first side of the interposer and a second surface on a second side of the interposer, wherein the first and the second sides are opposite sides. A first probe pad is disposed at the first surface. An electrical connector is disposed at the first surface, wherein the electrical connector is configured to be used for bonding. A through-via is disposed in the interposer. Front-side connections are disposed on the first side of the interposer, wherein the front-side connections electrically couple the through-via to the probe pad. | 04-18-2013 |
20130109169 | METHODS OF MANUFACTURING STRESS BUFFER STRUCTURES IN A MOUNTING STRUCTURE OF A SEMICONDUCTOR DEVICE | 05-02-2013 |
20130113070 | Interposers for Semiconductor Devices and Methods of Manufacture Thereof - Interposers for semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, an interposer includes a substrate, a contact pad disposed on the substrate, and a first through-via in the substrate coupled to the contact pad. A first fuse is coupled to the first through-via. A second through-via in the substrate is coupled to the contact pad, and a second fuse is coupled to the second through-via. | 05-09-2013 |
20140027900 | Bump Structure for Yield Improvement - A bump structure for electrically coupling semiconductor components is provided. The bump structure includes a first bump on a first semiconductor component and a second bump on a second semiconductor component. The first bump has a first non-flat portion (e.g., a convex projection) and the second bump has a second non-flat portion (e.g., a concave recess). The bump structure also includes a solder joint formed between the first and second non-flat portions to electrically couple the semiconductor components. | 01-30-2014 |
20140088747 | Near Non-Adaptive Virtual Metrology and Chamber Control - Embodiments of the present invention relate to a method for a near non-adaptive virtual metrology for wafer processing control. In accordance with an embodiment of the present invention, a method for processing control comprises diagnosing a chamber of a processing tool that processes a wafer to identify a key chamber parameter, and controlling the chamber based on the key chamber parameter if the key chamber parameter can be controlled, or compensating a prediction model by changing to a secondary prediction model if the key chamber parameter cannot be sufficiently controlled. | 03-27-2014 |
20140106536 | Cylindrical Embedded Capacitors - A device includes a substrate having a front surface and a back surface opposite the front surface. A capacitor is formed in the substrate and includes a first capacitor plate; a first insulation layer encircling the first capacitor plate; and a second capacitor plate encircling the first insulation layer. Each of the first capacitor plate, the first insulation layer, and the second capacitor plate extends from the front surface to the back surface of the substrate. | 04-17-2014 |