Patent application number | Description | Published |
20110246119 | PROCESS FOR TESTING THE RESISTANCE OF AN INTEGRATED CIRCUIT TO A SIDE CHANNEL ANALYSIS - A process for testing an integrated circuit includes collecting a set of points of a physical property while the integrated circuit is executing a multiplication, dividing the set of points into a plurality subsets of lateral points, calculating an estimation of the value of the physical property for each subset, and applying to the subset of lateral points a step of horizontal transversal statistical processing by using the estimations of the value of the physical property, to verify a hypothesis about the variables manipulated by the integrated circuit. | 10-06-2011 |
20110246789 | INTEGRATED CIRCUIT PROTECTED AGAINST HORIZONTAL SIDE CHANNEL ANALYSIS - An integrated circuit including a multiplication function configured to execute a multiplication operation of two binary words x and y including a plurality of basic multiplication steps of components xi of word x by components yj of word y is described. The multiplication function of the integrated circuit is configured to execute two successive multiplications by modifying, in a random or pseudo-random manner, an order in which the basic multiplication steps of components xi by components yj are executed. | 10-06-2011 |
20120221618 | ENCRYPTION METHOD COMPRISING AN EXPONENTIATION OPERATION - A method and a device protected against hidden channel attacks includes a calculation of the result of the exponentiation of a data m by an exponent d. The method and the device are configured to execute only multiplications of identical large variables, by breaking down any multiplication of different large variables x, y into a combination of multiplications of identical large variables. | 08-30-2012 |
20140129604 | Cryptographic method comprising a modular exponentiation operation - The present invention relates to a method for performing an iterative calculation of exponentiation of a large datum, the method being implemented in an electronic device (DV1) and comprising calculations of squaring and multiplying large variables performed in parallel, by squaring (SB1) and multiplication (SM1) blocks, the method comprising steps of: while a temporary storage buffer memory is not full of unused squares, triggering a calculation by the squaring block for a bit of the exponent, when the squaring block is inactive, storing each square provided by the squaring block in the buffer memory, if the bit of the corresponding exponent is on 1, and while the buffer memory contains an unused square, triggering a calculation by the multiplication block concerning the unused square, when the multiplication block is inactive. | 05-08-2014 |
20150082435 | CYCLIC REDUNDANCY CHECK METHOD WITH PROTECTION FROM SIDE-CHANNEL ATTACKS - The present invention relates to a method for processing a binary data item, comprising a step of calculating a cyclic redundancy check code for the data item by means of a generator polynomial, wherein the step of calculating the cyclic redundancy check code comprises the steps of: masking the data item with a random binary mask that is a multiple of the generator polynomial, and generating the cyclic redundancy check code for the data item from the masked data item. | 03-19-2015 |