Patent application number | Description | Published |
20080203589 | VARIABLE FILL AND CHEESE FOR MITIGATION OF BEOL TOPOGRAPHY - A method of designing features on a semiconductor wafer. A design of active or functional features is provided for chiplets separated by kerf areas on the wafer. The method then includes determining pattern density of the chiplet features, and applying a pattern of spaced dummy features on chiplet area not covered by active or functional features, as well as in the kerf areas. The dummy features are uniformly expanded or reduced in size until a desired dummy feature pattern density is reached. | 08-28-2008 |
20080230907 | INTEGRATED CIRCUIT SYSTEM WITH CARBON ENHANCEMENT - An integrated circuit hard mask processing system is provided including providing a substrate having an integrated circuit; forming an interconnect layer over the integrated circuit; applying a low-K dielectric layer over the interconnect layer; forming a via opening through the low-K dielectric layer to the interconnect layer; and forming a carbon implant region around the via opening, a trench opening, or a combination thereof, for protecting the low-K dielectric layer. | 09-25-2008 |
20080237786 | NON-PLANAR FUSE STRUCTURE INCLUDING ANGULAR BEND AND METHOD FOR FABRICATION THEREOF - A fuse structure includes a non-planar fuse material layer typically located over and replicating a topographic feature within a substrate. The non-planar fuse material layer includes an angular bend that assists in providing a lower severance current within the non-planar fuse material layer. | 10-02-2008 |
20080237868 | METHOD AND STRUCTURE FOR ULTRA NARROW CRACK STOP FOR MULTILEVEL SEMICONDUCTOR DEVICE - An integrated circuit design and a method of fabrication and, more particularly, a semiconductor structure having an ultra narrow crack stop for use in multilevel level devices and a method of making the same. The structure includes a first dielectric layer having a first connection connecting to an underlying interconnect and a second dielectric layer having a second connection connecting to the first connection. A stop gap structure extends through the first dielectric layer and the second dielectric layer, and has a width of about less than 1 um. | 10-02-2008 |
20080303164 | STRUCTURE AND METHOD OF REDUCING ELECTROMIGRATION CRACKING AND EXTRUSION EFFECTS IN SEMICONDUCTOR DEVICES - A structure for reducing electromigration cracking and extrusion effects in semiconductor devices includes a first metal line formed in a first dielectric layer; a cap layer formed over the first metal line and first dielectric layer; a second dielectric layer formed over the cap layer; and a void formed in the second dielectric layer, stopping on the cap layer, wherein the void is located in a manner so as to isolate structural damage due to electromigration effects of the first metal line, the effects including one or more of extrusions of metal material from the first metal line and cracks from delamination of the cap layer with respect to the first dielectric layer. | 12-11-2008 |
20080308900 | ELECTRICAL FUSE WITH SUBLITHOGRAPHIC DIMENSION - A photolithography mask contains at least one sublithographic assist feature (SLAF) such that the image of the fuselink shape on a photoresist contains a constructive interference portion and two neck portions. The width of the constructive interference portion is substantially the same as a critical dimension of the lithography tool and the widths of the two neck portions are sublithographic dimensions. The image on a photoresist is subsequently transferred into an underlying semiconductor layer to form an electrical fuse. The fuselink contains a constructive interference portion having a first width which is substantially the same as the critical dimension of the lithography tool and two neck portions having sublithographic widths. The inventive electrical fuse may be programmed with less voltage bias, current, and energy compared to prior art electrical fuses. | 12-18-2008 |
20080315353 | EMPTY VIAS FOR ELECTROMIGRATION DURING ELECTRONIC-FUSE RE-PROGRAMMING - The disclosure relates generally to integrated circuit (IC) chip fabrication, and more particularly, to an e-fuse device including an opening, a first via and a second via in an interlayer dielectric, wherein the opening, the first via and the second via are connected to an interconnect below the interlayer dielectric; a dielectric layer that encloses the first via and the second via; and a metal layer over the dielectric layer, wherein the metal layer fills the opening with a metal, and wherein the first via and the second via are substantially empty to allow for electromigration of the interconnect during re-programming of the e-fuse device. | 12-25-2008 |
20080316709 | Thermally Conductive Electrical Structure and Method - An electrical structure and method of forming. The electrical structure includes a first substrate comprising a plurality of electrical components, a first thermally conductive film layer formed over and in contact with a first electrical component of the plurality of electrical components, a first thermally conductive structure in mechanical contact with a first portion of the first thermally conductive film layer, and a first thermal energy extraction structure formed over the first thermally conductive structure. The first thermal energy extraction structure is in thermal contact with the first thermally conductive structure. The first thermal energy extraction structure is configured to extract a first portion of thermal energy from the first electrical component through the first thermally conductive film layer and the first thermally conductive structure. | 12-25-2008 |
20090001045 | METHODS OF PATTERNING SELF-ASSEMBLY NANO-STRUCTURE AND FORMING POROUS DIELECTRIC - Methods of patterning a self-assembly nano-structure and forming a porous dielectric are disclosed. In one aspect, the method includes providing a hardmask over an underlying layer; predefining an area with a photoresist on the hardmask that is to be protected during the patterning; forming a layer of the copolymer over the hardmask and the photoresist; forming the self-assembly nano-structure from the copolymer; and etching to pattern the self-assembly nano-structure. | 01-01-2009 |
20090008791 | Circuit Structure with Low Dielectric Constant Regions - A method for manufacturing a circuit includes the step of providing a first wiring level comprising first wiring level conductors separated by a first wiring level dielectric material. A first dielectric layer with a plurality of interconnect openings and a plurality of gap openings is formed above the first wiring level. The interconnect openings and the gap openings are pinched off with a pinching dielectric material to form relatively low dielectric constant (low-k) volumes in the gap openings. Metallic conductors comprising second wiring level conductors and interconnects to the first wiring level conductors are formed at the interconnect openings while maintaining the relatively low-k volumes in the gap openings. The gap openings with the relatively low-k volumes reduce parasitic capacitance between adjacent conductor structures formed by the conductors and interconnects. | 01-08-2009 |
20090021338 | ELECTRICAL FUSE HAVING A CAVITY THEREUPON - An electrical fuse is formed on a semiconductor substrate and a first dielectric layer is formed over the electrical fuse. At least one opening is formed by lithographic methods and a reactive ion etch in the first dielectric layer down to a top surface of the electrical fuse or down to shallow trench isolation. A second dielectric layer is deposited by a non-conformal deposition. Thickness of the second dielectric layer on the sidewalls of the at least one opening increases with height so that at least one cavity encapsulated by the second dielectric layer is formed in the at least one opening. The at least one cavity provides enhanced thermal isolation of the electrical fuse since the cavity provides superior thermal isolation than a dielectric material. | 01-22-2009 |
20090026574 | ELECTRICAL FUSE HAVING SUBLITHOGRAPHIC CAVITIES THEREUPON - An electrical fuse and a first dielectric layer thereupon are formed on a semiconductor substrate. Self-assembling block copolymers containing two or more different polymeric block components are applied into a recessed region surrounded by a dielectric template layer. The self-assembling block copolymers are then annealed to form a pattern of multiple circles having a sublithographic diameter. The pattern of multiple circles is transferred into the first dielectric layer by a reactive ion etch, wherein the portion of the first dielectric layer above the fuselink has a honeycomb pattern comprising multiple circular cylindrical holes. A second dielectric layer is formed over the circular cylindrical holes by a non-conformal chemical vapor deposition and sublithographic cavities are formed on the fuselink. The sublithographic cavities provide enhanced thermal insulation relative to dielectric materials to the fuselink so that the electrical fuse may be programmed with less programming current. | 01-29-2009 |
20090032959 | ELECTRICAL FUSES AND RESISTORS HAVING SUBLITHOGRAPHIC DIMENSIONS - Electrical fuses and resistors having a sublithographic lateral or vertical dimension are provided. A conductive structure comprising a conductor or a semiconductor is formed on a semiconductor substrate. At least one insulator layer is formed on the conductive structure. A recessed area is formed in the at least one insulator layer. Self-assembling block copolymers are applied into the recessed area and annealed to form a first set of polymer blocks and a second set of polymer blocks. The first set of polymer blocks are etched selective to the second set and the at least one insulator layer. Features having sublithographic dimensions are formed in the at least one insulator layer and/or the conductive structure. Various semiconductor structures having sublithographic dimensions are formed including electrical fuses and resistors. | 02-05-2009 |
20090035588 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING SAME - A semiconductor structure and method of manufacturing the semiconductor structure, and more particularly to a semiconductor structure having reduced metal line resistance and a method of manufacturing the same in back end of line (BEOL) processes. The method includes forming a first trench extending to a lower metal layer Mx+1 and forming a second trench remote from the first trench. The method further includes filling the first trench and the second trench with conductive material. The conductive material in the second trench forms a vertical wiring line extending orthogonally and in electrical contact with an upper wiring layer and electrically isolated from lower metal layers including the lower metal layer Mx+1. The vertical wiring line decreases a resistance of a structure. | 02-05-2009 |
20090045484 | METHODS AND SYSTEMS INVOLVING ELECTRICALLY REPROGRAMMABLE FUSES - An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the fuse is operative to form a surface void at the interface between the interconnect and the sensing wire when a first directional electron current is applied from the first programming wire through the interconnect to the second programming wire, and wherein, the fuse is further operative to heal the surface void between the interconnect and the sensing wire when a second directional electron current is applied from the second programming wire through the interconnect to the first programming wire. | 02-19-2009 |
20090072410 | MICROELECTRONIC CIRCUIT STRUCTURE WITH LAYERED LOW DIELECTRIC CONSTANT REGIONS - The circuit structure includes at least two generally parallel conductor structures, and a plurality of substantially horizontal layers of layer dielectric material interspersed with substantially horizontally extending relatively low dielectric constant (low-k) volumes. The substantially horizontal layers and the substantially horizontally extending volumes are generally interposed between the at least two generally parallel conductor structures. Also included are a plurality of substantially vertically extending relatively low-k volumes sealed within the substantially horizontal layers and the substantially horizontally extending volumes between the at least two generally parallel conductor structures. The substantially vertically extending relatively low-k volumes and the substantially horizontally extending relatively low-k volumes reduce parasitic capacitance between the at least two generally parallel conductor structures as compared to an otherwise comparable microelectronic circuit not including the relatively low-k volumes. | 03-19-2009 |
20090085151 | SEMICONDUCTOR FUSE STRUCTURE AND METHOD - An electrical structure and method of forming. The electrical structure includes a semiconductor substrate, an insulator layer formed over and in contact with the semiconductor substrate, and a semiconductor fuse structure formed over the insulator layer. The fuse structure includes a silicon layer and a continuous metallic silicide layer. The continuous metallic silicide layer includes a first section formed over and in contact with a first horizontal section of a top surface of the silicon layer, a second section formed over and in contact with a second horizontal section of the top surface of the silicon layer, and a third section formed within an opening within the top surface of the silicon layer. | 04-02-2009 |
20090090986 | FULLY AND UNIFORMLY SILICIDED GATE STRUCTURE AND METHOD FOR FORMING SAME - Fully and uniformly silicided gate conductors are produced by deeply “perforating” silicide gate conductors with sub-lithographic, sub-critical dimension, nanometer-scale openings. A silicide-forming metal (e.g. cobalt, tungsten, etc.) is then deposited, polysilicon gates, covering them and filling the perforations. An anneal step converts the polysilicon to silicide. Because of the deep perforations, the surface area of polysilicon in contact with the silicide-forming metal is greatly increased over conventional silicidation techniques, causing the polysilicon gate to be fully converted to a uniform silicide composition. A self-assembling diblock copolymer is used to form a regular sub-lithographic nanometer-scale pattern that is used as an etching “template” for forming the perforations. | 04-09-2009 |
20090130590 | PHOTORESIST COMPOSITIONS AND PROCESS FOR MULTIPLE EXPOSURES WITH MULTIPLE LAYER PHOTORESIST SYSTEMS - A photoresist composition and methods using the photoresist composition in multiple exposure/multiple layer processes. The photoresist composition includes a polymer comprising repeat units having a hydroxyl moiety; a photoacid generator; and a solvent. The polymer when formed on a substrate is substantially insoluble to the solvent after heating to a temperature of about 150° C. or greater. One method includes forming a first photoresist layer on a substrate, patternwise exposing the first photoresist layer, forming a second non photoresist layer on the substrate and patterned first photoresist layer. Another method includes forming a first photoresist layer on a substrate, patternwise exposing the first photoresist layer, forming a second photoresist layer on the substrate and patterned first photoresist layer and patternwise exposing the second photoresist layer. | 05-21-2009 |
20090142704 | METHOD FOR REDUCING SIDE LOBE PRINTING USING A BARRIER LAYER - A method suitable for reducing side lobe printing in a photolithography process is enabled by the use of a barrier layer on top of a photoresist on a substrate. The barrier layer is absorbing at the imaging wavelength of the underlying photoresist and thus blocks the light from reaching the photoresist. A first exposure followed by a development in an aqueous base solution selectively removes a portion of the barrier layer to reveal a section of the underlying photoresist layer. At least a portion of the revealed section of the photoresist layer is then exposed and developed to form a patterned structure in the photoresist layer. The barrier layer can also be bleachable upon exposure and bake in the present invention. | 06-04-2009 |
20090148795 | PATTERNING METHOD USING A COMBINATION OF PHOTOLITHOGRAPHY AND COPOLYMER SELF-ASSEMBLYING LITHOGRAPHY TECHNIQUES - Disclosed are embodiments of a lithographic patterning method that incorporates a combination of photolithography and self-assembling copolymer lithography techniques in order to create, on a substrate, a grid-pattern mask having multiple cells, each with at least one sub-50 nm dimension. The combination of different lithographic techniques further allows for precise registration and overlay of the individual grid-pattern cells with corresponding structures within the substrate. The resulting grid-pattern mask can then be used, in conjunction with directional etch and other processes, to extend the cell patterns into the substrate and, thereby form openings, with at least one sub-50 nm dimension, landing on corresponding in-substrate structures. Once the openings are formed, additional structures can be formed within the openings. | 06-11-2009 |
20090155715 | PHOTORESIST COMPOSITIONS AND METHOD FOR MULTIPLE EXPOSURES WITH MULTIPLE LAYER RESIST SYSTEMS - A method and a resist composition. The resist composition includes a polymer having repeating units having a lactone moiety, a thermal base generator capable of generating a base and a photosensitive acid generator. The polymer has the properties of being substantially soluble in a first solvent and becoming substantially insoluble after heating the polymer. The method includes forming a film of a photoresist including a polymer, a thermal base generator capable of releasing a base, a photosensitive acid generator, and a solvent. The film is patternwise imaged. The imaging includes exposing the film to radiation, resulting in producing an acid catalyst. The film is developed in an aqueous base, resulting in removing base-soluble regions and forming a patterned layer. The patterned layer is baked above the temperature, resulting in the thermal base generator releasing a base within the patterned layer and the patterned layer becoming insoluble in the solvent. | 06-18-2009 |
20090155718 | PHOTORESIST COMPOSITIONS AND METHOD FOR MULTIPLE EXPOSURES WITH MULTIPLE LAYER RESIST SYSTEMS - A method and a resist composition. The resist composition includes a polymer having repeating units having a lactone moiety, a thermal base generator capable of generating a base and a photosensitive acid generator. The polymer has the properties of being substantially soluble in a first solvent and becoming substantially insoluble after heating the polymer. The method includes forming a film of a photoresist including a polymer, a thermal base generator capable of releasing a base, a photosensitive acid generator, and a solvent. The film is patternwise imaged. The imaging includes exposing the film to radiation, resulting in producing an acid catalyst. The film is developed in an aqueous base, resulting in removing base-soluble regions and forming a patterned layer. The patterned layer is baked above the temperature, resulting in the thermal base generator releasing a base within the patterned layer and the patterned layer becoming insoluble in the solvent. | 06-18-2009 |
20090160027 | Methods of Manufacturing Semiconductor Devices and Optical Proximity Correction - Methods of manufacturing semiconductor devices and methods of optical proximity correction methods are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes determining an amount of reactive ion etch (RIE) lag of a RIE process for a material layer of the semiconductor device, and adjusting a size of at least one pattern for a feature of the material layer by an adjustment amount to partially compensate for the amount of RIE lag determined. | 06-25-2009 |
20090200636 | SUB-LITHOGRAPHIC DIMENSIONED AIR GAP FORMATION AND RELATED STRUCTURE - Sub-lithographic dimensioned air gap formation and related structure are disclosed. In one embodiment, a method includes forming a dielectric layer including interconnects on a substrate; depositing a cap layer on the dielectric layer; depositing a photoresist over the cap layer; patterning the photoresist to include a first trench pattern at most partially overlying the interconnects; forming a spacer within the first trench pattern to form a second trench pattern having a sub-lithographic dimension; transferring the second trench pattern into the cap layer and into the dielectric layer between the interconnects; and depositing another dielectric layer to form an air gap by pinching off the trench in the dielectric layer. | 08-13-2009 |
20090200674 | STRUCTURE AND METHOD OF FORMING TRANSITIONAL CONTACTS BETWEEN WIDE AND THIN BEOL WIRINGS - A structure and method of forming a conducting via for connecting two back end of the line (BEOL) metal wiring levels is described. The method includes forming a first interconnect structure having a first dimensional width in a first dielectric layer; depositing a second dielectric layer over said first dielectric layer; etching an interconnect trench in the said second dielectric layer; etching a interconnect via using a photo resist mask to form a first portion of the transitional via; reacting the photo resist to expand the photo resist at least in the lateral direction; etching the said dielectric layer using the reacted photo resist to form the second portion of the transitional via; and filling the said interconnect trench and the said interconnect via with metal. | 08-13-2009 |
20090206442 | METHOD AND STRUCTURE FOR RELIEVING TRANSISTOR PERFORMANCE DEGRADATION DUE TO SHALLOW TRENCH ISOLATION INDUCED STRESS - A method of forming shallow trench isolation (STI) regions for semiconductor devices, the method including defining STI trench openings within a semiconductor substrate; filling the STI trench openings with an initial trench fill material; defining a pattern of nano-scale openings over the substrate, at locations corresponding to the STI trench openings; transferring the pattern of nano-scale openings into the trench fill material so as to define a plurality of vertically oriented nano-scale openings in the trench fill material; and plugging upper portions of the nano-scale openings with additional trench fill material, thereby defining porous STI regions in the substrate. | 08-20-2009 |
20090206489 | DUAL DAMASCENE METAL INTERCONNECT STRUCTURE HAVING A SELF-ALIGNED VIA - A recessed region containing a line portion and a bulge portion is formed in a hard mask layer. Self-assembling block copolymers containing two or more different polymeric block components that are immiscible with one another are applied within the recessed region and annealed. A cylindrical polymeric block centered at the bulge portion is removed selective to a polymeric block matrix surrounding the cylindrical polymeric block. A via cavity is formed by transferring the cavity formed by removal of the cylindrical polymeric block into a dielectric layer. The pattern in the hard mask layer is subsequently transferred into the dielectric layer to form a line cavity. A metal via and a metal line are formed by deposition and planarization of metal. The metal via is self-aligned to the metal line. | 08-20-2009 |
20090208865 | PHOTOLITHOGRAPHY FOCUS IMPROVEMENT BY REDUCTION OF AUTOFOCUS RADIATION TRANSMISSION INTO SUBSTRATE - An anti-reflective coating material, a microelectronic structure that includes an anti-reflective coating layer formed from the anti-reflective coating material and a related method for exposing a resist layer located over a substrate while using the anti-reflective coating layer provide for attenuation of secondary reflected vertical alignment beam radiation when aligning the substrate including the resist layer located thereover. Such enhanced vertical alignment provides for improved dimensional integrity of a patterned resist layer formed from the resist layer, as well as additional target layers that may be fabricated while using the resist layer as a mask. | 08-20-2009 |
20090284722 | METHOD FOR MONITORING FOCUS ON AN INTEGRATED WAFER - A method and apparatus are provided for improving the focusing of a substrate such as a wafer during the photolithography imaging procedure of a semiconductor manufacturing process. The invention is particularly useful for step-and-scan system and the CD of two features in each exposure field are measured in fields exposed at varying focus to form at least two Bossung curves. Exposure focus instructions are calculated based on the intersection point of the curves and the wafer is then scanned and imaged based on the calculated exposure focus instructions. In another aspect of the invention, when multiple wafers are being processed operational variances may cause a drift in the focus. The focus drift can be easily corrected by measuring the critical dimension of each of the features and comparing the difference to determine if any focus offset is needed to return the focus to the original calculated focus value. | 11-19-2009 |
20090311491 | MULTI-EXPOSURE LITHOGRAPHY EMPLOYING DIFFERENTIALLY SENSITIVE PHOTORESIST LAYERS - A stack of a second photoresist having a second photosensitivity and a first photoresist having a first photosensitivity, which is greater than second photosensitivity, is formed on a substrate. A first pattern is formed in the first photoresist by a first exposure and a first development, while the second photoresist underneath remains intact. A second pattern comprising an array of lines is formed in the second photoresist. An exposed portion of the second photoresist underneath a remaining portion of the first photoresist forms a narrow portion of a line pattern, while an exposed portion of the second photoresist outside the area of the remaining portions of the photoresist forms a wide portion of the line pattern. Each wide portion of the line pattern forms a bulge in the second pattern, which increases overlay tolerance between the second pattern and the pattern of conductive vias. | 12-17-2009 |
20100005649 | ELECTRICAL FUSE HAVING SUBLITHOGRAPHIC CAVITIES THEREUPON - An electrical fuse and a first dielectric layer thereupon are formed on a semiconductor substrate. Self-assembling block copolymers containing two or more different polymeric block components are applied into a recessed region surrounded by a dielectric template layer. The self-assembling block copolymers are then annealed to form a pattern of multiple circles having a sublithographic diameter. The pattern of multiple circles is transferred into the first dielectric layer by a reactive ion etch, wherein the portion of the first dielectric layer above the fuselink has a honeycomb pattern comprising multiple circular cylindrical holes. A second dielectric layer is formed over the circular cylindrical holes by a non-conformal chemical vapor deposition and sublithographic cavities are formed on the fuselink. The sublithographic cavities provide enhanced thermal insulation relative to dielectric materials to the fuselink so that the electrical fuse may be programmed with less programming current. | 01-14-2010 |
20100009298 | FORMING SUB-LITHOGRAPHIC PATTERNS USING DOUBLE EXPOSURE - Methods are presented of forming sub-lithographic patterns using double exposure. One method may include providing a photoresist layer over a layer to be patterned; exposing the photoresist layer using a first mask having a first opening; developing the photoresist layer to transfer the first opening into the photoresist layer, forming a boundary in the photoresist layer about the transferred first opening that is hardened; exposing the photoresist layer using a second mask having a second opening that overlaps the boundary; and developing the photoresist layer to transfer the second opening into the photoresist layer, leaving the boundary, wherein the boundary has a sub-lithographic dimension. | 01-14-2010 |
20100178615 | METHOD FOR REDUCING TIP-TO-TIP SPACING BETWEEN LINES - This invention provides a method for reducing tip-to-tip spacing between lines using a combination of photolithographic and copolymer self-assembling lithographic techniques. A mask layer is first formed over a substrate with a line structure. A trench opening of a width d is created in the mask layer. A layer of a self-assembling block copolymer is then applied over the mask layer. The block copolymer layer is annealed to form a single unit polymer block of a width or a diameter w which is smaller than d inside the trench opening. The single unit polymer block is selectively removed to form a single opening of a width or a diameter w inside the trench opening. An etch transfer process is performed using the single opening as a mask to form an opening in the line structure in the substrate. | 07-15-2010 |
20100209853 | METHOD FOR SELECTIVELY ADJUSTING LOCAL RESIST PATTERN DIMENSION WITH CHEMICAL TREATMENT - A method forms a first patterned mask (comprising rectangular features and/or rounded openings) on a planar surface and forms a second patterned mask on the first patterned mask and the planar surface. The second patterned mask covers protected portions of the first patterned mask and the second patterned mask reveals exposed portions of the first patterned mask. The method treats the exposed portions of the first patterned mask with a chemical treatment that reduces the size of the exposed portions to create an altered first patterned mask. | 08-19-2010 |
20100248147 | PHOTORESIST COMPOSITIONS AND PROCESS FOR MULTIPLE EXPOSURES WITH MULTIPLE LAYER PHOTORESIST SYSTEMS - A photoresist composition and methods using the photoresist composition in multiple exposure/multiple layer processes. The photoresist composition includes a polymer comprising repeat units having a hydroxyl moiety; a photoacid generator; and a solvent. The polymer when formed on a substrate is substantially insoluble to the solvent after heating to a temperature of about 150° C. or greater. One method includes forming a first photoresist layer on a substrate, patternwise exposing the first photoresist layer, forming a second non photoresist layer on the substrate and patterned first photoresist layer. Another method includes forming a first photoresist layer on a substrate, patternwise exposing the first photoresist layer, forming a second photoresist layer on the substrate and patterned first photoresist layer and patternwise exposing the second photoresist layer. | 09-30-2010 |
20100255428 | METHOD TO MITIGATE RESIST PATTERN CRITICAL DIMENSION VARIATION IN A DOUBLE-EXPOSURE PROCESS - A method to mitigate resist pattern critical dimension (CD) variation in a double-exposure process generally includes forming a photoresist layer over a substrate; exposing the photoresist layer to a first radiation; developing the photoresist layer to form a first pattern in the photoresist layer; forming a topcoat layer over the photoresist layer; exposing the topcoat layer and the photoresist layer to a second radiation; removing the topcoat layer; and developing the photoresist layer to form a second pattern in the photoresist layer. | 10-07-2010 |
20100272967 | METHOD OF FORMING A PATTERN OF AN ARRAY OF SHAPES INCLUDING A BLOCKED REGION - A second photoresist having a second photosensitivity is formed on a substrate. A first photoresist having a first photosensitivity, which is greater than second photosensitivity, is formed on the second photoresist. Preferably, the first photoresist is a gray resist that becomes transparent upon exposure. At least one portion of the first photoresist is lithographically exposed employing a first reticle having a first pattern to form at least one transparent lithographically exposed resist portion, while the second photoresist remains intact. The second photoresist is lithographically exposed employing a second reticle including a second pattern to form a plurality of lithographically exposed shapes in the second photoresist. The plurality of lithographically exposed shapes have a composite pattern which is the derived from the second pattern by limiting the second pattern only within the area of the at least one transparent lithographically exposed resist pattern. | 10-28-2010 |
20100283121 | ELECTRICAL FUSES AND RESISTORS HAVING SUBLITHOGRAPHIC DIMENSIONS - Electrical fuses and resistors having a sublithographic lateral or vertical dimension are provided. A conductive structure comprising a conductor or a semiconductor is formed on a semiconductor substrate. At least one insulator layer is formed on the conductive structure. A recessed area is formed in the at least one insulator layer. Self-assembling block copolymers are applied into the recessed area and annealed to form a fist set of polymer blocks and a second set of polymer blocks. The first set of polymer blocks are etched selective to the second set and the at least one insulator layer. Features having sublithographic dimensions are formed in the at least one insulator layer and/or the conductive structure. Various semiconductor structures having sublithographic dimensions are formed including electrical fuses and resistors. | 11-11-2010 |
20110156282 | Gate Conductor Structure - A gate conductor structure is provided having a barrier region between a N-type device and a P-type device, wherein the barrier region minimizes or eliminates cross-diffusion of dopant species across the barrier region. The barrier region comprises at least one sublithographic gap in the gate conductor structure. The sublithographic gap is formed by using self-assembling copolymers to form a sublithographic patterned mask over the gate conductor structure. According to one embodiment, at least one sublithographic gap is a slit or line that traverses the width of the gate conductor structure. The sublithographic gap is sufficiently deep to minimize or prevent cross-diffusion of the implanted dopant from the upper portion of the gate conductor. According to another embodiment, the sublithographic gaps are of sufficient density that cross-diffusion of dopants is reduced or eliminated during an activation anneal such that changes in Vt are minimized. | 06-30-2011 |
20110183491 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING SAME - A semiconductor structure and method of manufacturing the semiconductor structure, and more particularly to a semiconductor structure having reduced metal line resistance and a method of manufacturing the same in back end of line (BEOL) processes. The method includes forming a first trench extending to a lower metal layer Mx+ | 07-28-2011 |
20110209106 | METHOD FOR DESIGNING OPTICAL LITHOGRAPHY MASKS FOR DIRECTED SELF-ASSEMBLY - A method and a computer system for designing an optical photomask for forming a prepattern opening in a photoresist layer on a substrate wherein the photoresist layer and the prepattern opening are coated with a self-assembly material that undergoes directed self-assembly to form a directed self-assembly pattern. The methods includes: generating a mask design shape from a target design shape; generating a sub-resolution assist feature design shape based on the mask design shape; using a computer to generate a prepattern shape based on the sub-resolution assist feature design shape; and using a computer to evaluate if a directed self-assembly pattern of the self-assembly material based on the prepattern shape is within specified ranges of dimensional and positional targets of the target design shape on the substrate. | 08-25-2011 |
20110256486 | PHOTOLITHOGRAPHY FOCUS IMPROVEMENT BY REDUCTION OF AUTOFOCUS RADIATION TRANSMISSION INTO SUBSTRATE - An anti-reflective coating material, a microelectronic structure that includes an anti-reflective coating layer formed from the anti-reflective coating material and a related method for exposing a resist layer located over a substrate while using the anti-reflective coating layer provide for attenuation of secondary reflected vertical alignment beam radiation when aligning the substrate including the resist layer located thereover. Such enhanced vertical alignment provides for improved dimensional integrity of a patterned resist layer formed from the resist layer, as well as additional target layers that may be fabricated while using the resist layer as a mask. | 10-20-2011 |
20120070787 | PHOTORESIST COMPOSITIONS AND METHODS FOR SHRINKING A PHOTORESIST CRITICAL DIMENSION - A method for reducing a photoresist critical dimension, the method comprising depositing a photoresist film on a substrate, wherein the photoresist film includes a thermal base generator; patterning the photoresist film to form a first patterned film possessing a first critical dimension; depositing a crosslinkable film over the first patterned film; heat-activating the first patterned film, either before or after depositing the crosslinkable film, to release a base in the first patterned film and cause crosslinking in the crosslinkable film in contact with the first patterned film; and developing the crosslinkable film to remove non-crosslinked soluble portions therein to form a second patterned film possessing a reduced critical dimension compared to the first critical dimension. | 03-22-2012 |
20120112302 | Novel Integration Process to Improve Focus Leveling Within a Lot Process Variation - A method of improving the focus leveling response of a semiconductor wafer is described. The method includes combining organic and inorganic or metallic near infrared (NIR) hardmask on a semiconductor substrate; forming an anti-reflective coating (ARC) layer on the combined organic NIR-absorption and the inorganic or metallic NIR-absorption hardmask; and forming a photoresist layer on the ARC layer. A semiconductor structure is also described including a substrate, a resist layer located over the structure; and an absorptive layer located over the substrate. The absorptive layer includes an inorganic or metallic NIR-absorbing hardmask layer. | 05-10-2012 |
20120122031 | PHOTORESIST COMPOSITION FOR NEGATIVE DEVELOPMENT AND PATTERN FORMING METHOD USING THEREOF - The present invention relates to a photoresist composition capable of negative development and a pattern forming method using the photoresist composition. The photoresist composition includes an imaging polymer and a radiation sensitive acid generator. The imaging polymer includes a first monomeric unit having a pendant acid labile moiety and a second monomeric unit containing a reactive ether moiety, an isocyanide moiety or an isocyanate moiety. The patterning forming method utilizes an organic solvent developer to selectively remove unexposed regions of a photoresist layer of the photoresist composition to form a patterned structure in the photoresist layer. The photoresist composition and the pattern forming method are especially useful for forming material patterns on a semiconductor substrate using 193 nm (ArF) lithography. | 05-17-2012 |
20120156450 | MULTI-EXPOSURE LITHOGRAPHY EMPLOYING DIFFERENTIALLY SENSITIVE PHOTORESIST LAYERS - A stack of a second photoresist having a second photosensitivity and a first photoresist having a first photosensitivity, which is greater than second photosensitivity, is formed on a substrate. A first pattern is formed in the first photoresist by a first exposure and a first development, while the second photoresist underneath remains intact. A second pattern comprising an array of lines is formed in the second photoresist. An exposed portion of the second photoresist underneath a remaining portion of the first photoresist forms a narrow portion of a line pattern, while an exposed portion of the second photoresist outside the area of the remaining portions of the photoresist forms a wide portion of the line pattern. Each wide portion of the line pattern forms a bulge in the second pattern, which increases overlay tolerance between the second pattern and the pattern of conductive vias. | 06-21-2012 |
20120264295 | STRUCTURE AND METHOD OF REDUCING ELECTROMIGRATION CRACKING AND EXTRUSION EFFECTS IN SEMICONDUCTOR DEVICES - A structure for reducing electromigration cracking and extrusion effects in semiconductor devices includes a first metal line formed in a first dielectric layer; a cap layer formed over the first metal line and first dielectric layer; a second dielectric layer formed over the cap layer; and a void formed in the second dielectric layer, stopping on the cap layer, wherein the void is located in a manner so as to isolate structural damage due to electromigration effects of the first metal line, the effects including one or more of extrusions of metal material from the first metal line and cracks from delamination of the cap layer with respect to the first dielectric layer. | 10-18-2012 |
20120331428 | METHOD FOR DESIGNING OPTICAL LITHOGRAPHY MASKS FOR DIRECTED SELF-ASSEMBLY - A method and a computer system for designing an optical photomask for forming a prepattern opening in a photoresist layer on a substrate wherein the photoresist layer and the prepattern opening are coated with a self-assembly material that undergoes directed self-assembly to form a directed self-assembly pattern. The methods includes: generating a mask design shape from a target design shape; generating a sub-resolution assist feature design shape based on the mask design shape; using a computer to generate a prepattern shape based on the sub-resolution assist feature design shape; and using a computer to evaluate if a directed self-assembly pattern of the self-assembly material based on the prepattern shape is within specified ranges of dimensional and positional targets of the target design shape on the substrate. | 12-27-2012 |
20130157463 | NEAR-INFRARED ABSORBING FILM COMPOSITION FOR LITHOGRAPHIC APPLICATION - The present invention relates to a near-infrared (NIR) film composition for use in vertical alignment and correction in the patterning of integrated semiconductor wafers and a pattern forming method using the composition. The NIR absorbing film composition includes a NIR absorbing dye having a polymethine cation and a crosslinkable anion, a crosslinkable polymer and a crosslinking agent. The patterning forming method includes aligning and focusing a focal plane position of a photoresist layer by sensing near-infrared emissions reflected from a substrate containing the photoresist layer and a NIR absorbing layer formed from the NIR absorbing film composition under the photoresist layer. The NIR absorbing film composition and the pattern forming method are especially useful for forming material patterns on a semiconductor substrate having complex buried topography. | 06-20-2013 |
20130164680 | PHOTORESIST COMPOSITION FOR NEGATIVE DEVELOPMENT AND PATTERN FORMING METHOD USING THEREOF - The present invention relates to a photoresist composition capable of negative development and a pattern forming method using the photoresist composition. The photoresist composition includes an imaging polymer and a radiation sensitive acid generator. The imaging polymer includes a first monomeric unit having a pendant acid labile moiety and a second monomeric unit containing a reactive ether moiety, an isocyanide moiety or an isocyanate moiety. The patterning forming method utilizes an organic solvent developer to selectively remove unexposed regions of a photoresist layer of the photoresist composition to form a patterned structure in the photoresist layer. The photoresist composition and the pattern forming method are especially useful for forming material patterns on a semiconductor substrate using 193 nm (ArF) lithography. | 06-27-2013 |
20130214391 | Lateral-Dimension-Reducing Metallic Hard Mask Etch - A combination of gases including at least a fluorocarbon gas, oxygen, and an inert sputter gas is employed to etch at least one opening into an organic photoresist. The amount of oxygen is controlled to a level that limits conversion of a metallic nitride material in an underlying hard mask layer to a metal oxide, and causes organic polymers generated from the organic photoresist to cover peripheral regions of each opening formed in the organic photoresist. The hard mask layer is etched with a taper by the oxygen-limited fluorine-based etch chemistry provided by the combination of gases. The taper angle can be controlled such that a shrink ratio of the lateral dimension by the etch can exceed 2.0. | 08-22-2013 |
20130233608 | Physical Unclonable Interconnect Function Array - A method for fabricating an interconnect function array includes forming a first plurality of conductive lines on a substrate, forming an insulator layer over the first plurality of conductive lines and the substrate, removing portions of the insulator layer to define cavities in the insulator layer that expose portions of the substrate and the first plurality of conductive lines, wherein the removal of the portions of the insulator layer results in a substantially random arrangement of cavities exposing portions of the substrate and the first plurality of conductive lines, depositing a conductive material in the cavities, and forming a second plurality of conductive lines on portions of the conductive material in the cavities and the insulator layer. | 09-12-2013 |
20130288178 | PHOTORESIST COMPOSITION CONTAINING A PROTECTED HYDROXYL GROUP FOR NEGATIVE DEVELOPMENT AND PATTERN FORMING METHOD USING THEREOF - The present invention relates to a photoresist composition capable of negative development and a pattern forming method using the photoresist composition. The photoresist composition includes an imaging polymer, a crosslinking agent and a radiation sensitive acid generator. The imaging polymer includes a monomeric unit having an acid-labile moiety-substituted hydroxyl group. The patterning forming method utilizes an organic solvent developer to selectively remove an unexposed region of a photoresist layer of the photoresist composition to form a patterned structure in the photoresist layer. The photoresist composition and the pattern forming method are especially useful for forming material patterns on a semiconductor substrate using 193 nm (ArF) lithography. | 10-31-2013 |
20140035142 | PROFILE CONTROL IN INTERCONNECT STRUCTURES - The profile of a via can be controlled by forming a profile control liner within each via opening that is formed into a dielectric material prior to forming a line opening within the dielectric material. The presence of the profile control liner within each via opening during the formation of the line opening prevents rounding of the corners of a dielectric material portion that is present beneath the line opening and adjacent the via opening. | 02-06-2014 |
20140072915 | PHOTORESIST COMPOSITION CONTAINING A PROTECTED HYDROXYL GROUP FOR NEGATIVE DEVELOPMENT AND PATTERN FORMING METHOD USING THEREOF - The present invention relates to a photoresist composition capable of negative development and a pattern forming method using the photoresist composition. The photoresist composition includes an imaging polymer, a crosslinking agent and a radiation sensitive acid generator. The imaging polymer includes a monomeric unit having an acid-labile moiety-substituted hydroxyl group. The patterning forming method utilizes an organic solvent developer to selectively remove an unexposed region of a photoresist layer of the photoresist composition to form a patterned structure in the photoresist layer. The photoresist composition and the pattern forming method are especially useful for forming material patterns on a semiconductor substrate using 193 nm (ArF) lithography. | 03-13-2014 |
20140203447 | METAL LINES HAVING ETCH-BIAS INDEPENDENT HEIGHT - A dielectric material stack including at least a via level dielectric material layer, at least one patterned etch stop dielectric material portion, a line level dielectric material layer, and optionally a dielectric cap layer is formed over a substrate. At least one patterned hard mask layer including a first pattern can be formed above the dielectric material stack. A second pattern is transferred through the line level dielectric material layer employing the at least one etch stop dielectric material portion as an etch stop structure. The first pattern is transferred through the line level dielectric material layer employing the at least one etch stop dielectric material portion as an etch stop structure while the second pattern is transferred through the via level dielectric material layer to form integrated line and via trenches, which are filled with a conductive material to form integrated line and via structures. | 07-24-2014 |
20140210034 | NEAR-INFRARED ABSORBING FILM COMPOSITIONS - A curable liquid formulation comprising: (i) one or more near-infrared absorbing polymethine dyes; (ii) one or more crosslinkable polymers; and (iii) one or more casting solvents. The invention is also directed to solid near-infrared absorbing films composed of crosslinked forms of the curable liquid formulation. The invention is also directed to a microelectronic substrate containing a coating of the solid near-infrared absorbing film as well as a method for patterning a photoresist layer coated on a microelectronic substrate in the case where the near-infrared absorbing film is between the microelectronic substrate and a photoresist film. | 07-31-2014 |
20140217612 | ELECTRONIC FUSE HAVING A DAMAGED REGION - An electronic fuse structure including an M | 08-07-2014 |
20150028484 | RANDOM LOCAL METAL CAP LAYER FORMATION FOR IMPROVED INTEGRATED CIRCUIT RELIABILITY - A method and structure for preventing integrated circuit failure due to electromigration and time dependent dielectric breakdown is disclosed. A randomly patterned metal cap layer is selectively formed on the metal interconnect lines (typically copper (Cu)) with an interspace distance between metal cap segments that is less than the critical length (for short-length effects). Since the diffusivity is lower for the Cu/metal cap interface than for the Cu/dielectric cap interface, the region with a metal cap serves as a diffusion barrier. | 01-29-2015 |
20150035154 | PROFILE CONTROL IN INTERCONNECT STRUCTURES - The profile of a via can be controlled by forming a profile control liner within each via opening that is formed into a dielectric material prior to forming a line opening within the dielectric material. The presence of the profile control liner within each via opening during the formation of the line opening prevents rounding of the corners of a dielectric material portion that is present beneath the line opening and adjacent the via opening. | 02-05-2015 |