Patent application number | Description | Published |
20080224740 | FREQUENCY MIXER HAVING FERROMAGNETIC FILM - A frequency conversion device, which may include a radiofrequency (RF) mixer device, includes a substrate and a ferromagnetic film disposed over a surface of the substrate. An insulator is disposed over the ferromagnetic film and at least one microstrip antenna is disposed over the insulator. The ferromagnetic film provides a non-linear response to the frequency conversion device. The frequency conversion device may be used for signal mixing and amplification. The frequency conversion device may also be used in data encryption applications. | 09-18-2008 |
20090096044 | Spin-Wave Architectures - Nano-scale and multi-scale computational architectures using spin waves as a physical mechanism for device interconnection are provided. Solid-state spin-wave computing devices using nano-scale and multi-scale computational architectures comprised of a plurality of inputs and a plurality of outputs are described where such devices are configured to simultaneously transmit data elements from the inputs to the outputs by using spin-waves of differing frequencies. These devices include but are not limited to a spin-wave crossbar, a spin-wave reconfigurable mesh, a spin-wave fully-interconnected cluster, a hierarchical multi-scale spin-wave crossbar, a hierarchical multi-scale spin-wave reconfigurable mesh and a hierarchical multi-scale spin-wave fully-interconnected cluster. | 04-16-2009 |
20090127543 | VERTICAL GATE-DEPLETED SINGLE ELECTRON TRANSISTOR - A vertical gate-depleted single electron transistor (SET) is fabricated on a conducting or insulating substrate. A plurality of lightly doped basic materials and tunneling barriers are fabricated on top of a substrate, wherein at least two of the layers of basic materials sandwich the layers of tunneling barriers and at least two of the layers of tunneling barriers sandwich at least one of the layers of basic materials. A mesa is fabricated on top of the layers of basic materials and tunneling barriers, and has an undercut shape. An ohmic contact is fabricated on top of the mesa, and one or more gate Schottky contacts are fabricated on top of the layers of lightly doped basic materials and tunneling barriers. A quantum dot is induced by gate depletion, when a source voltage is set as zero, a drain voltage is set to be less than 0.1, and a gate voltage is set to be negative. The depletion region expands toward the center of the device and forms a lateral confinement to the quantum well, wherein a quantum dot is obtained. Because the size of the quantum dot is so small, the Coulomb charging energy achieved is large enough to let the device operate at room temperature. | 05-21-2009 |
20100308391 | SEMICONDUCTOR DEVICE - Provided are a semiconductor device and a method of fabricating the same. At least one mold structure defining at least one first opening is formed on a substrate, wherein the mold structure comprises first mold patterns and second mold patterns that are sequentially and alternatingly stacked. Thereafter, side surfaces of the first mold patterns are selectively etched to form undercut regions between the second mold patterns. Then, a semiconductor layer is formed to cover a surface of the mold structure where the undercut regions are formed, and gate patterns are formed, which fill respective undercut regions where the semiconductor layer is formed. | 12-09-2010 |
20110018051 | Integrated Circuit Memory Devices Having Vertical Transistor Arrays Therein and Methods of Forming Same - An integrated circuit device includes a transistor array having a vertical stack of independently controllable gate electrodes therein. A first semiconductor channel region is provided, which extends on a first sidewall of the vertical stack of independently controllable gate electrodes. A first electrically insulating layer is also provided, which extends between the first semiconductor channel region and the first sidewall of the vertical stack of independently controllable gate electrodes. Source and drain regions are provided, which are electrically coupled to first and second ends of the first semiconductor channel region, respectively. | 01-27-2011 |
20120028846 | GAS SENSOR INCORPORATING A POROUS FRAMEWORK - The disclosure provides sensor for gas sensing including CO | 02-02-2012 |
20120181593 | Semiconductor Device - Provided is a semiconductor device that can include a lower interconnection on a substrate and at least one upper interconnection disposed on the lower interconnection. At least one gate structure can be disposed between the upper interconnection and the lower interconnection, where the gate structure can include a plurality of gate lines that are vertically stacked so that each of the gate lines has a wiring portion that is substantially parallel to an upper surface of the substrate and a contact portion that extends from the wiring portion along a direction penetrating an upper surface of the substrate. At least one semiconductor pattern can connect the upper and lower interconnections. | 07-19-2012 |
20130295680 | GAS SENSOR INCORPORATING A POROUS FRAMEWORK - The disclosure provides sensor for gas sensing including CO | 11-07-2013 |
20140015032 | INTEGRATED CIRCUIT MEMORY DEVICES HAVING VERTICAL TRANSISTOR ARRAYS THEREIN AND METHODS OF FORMING SAME - An integrated circuit device includes a transistor array having a vertical stack of independently controllable gate electrodes therein. A first semiconductor channel region is provided, which extends on a first sidewall of the vertical stack of independently controllable gate electrodes. A first electrically insulating layer is also provided, which extends between the first semiconductor channel region and the first sidewall of the vertical stack of independently controllable gate electrodes. Source and drain regions are provided, which are electrically coupled to first and second ends of the first semiconductor channel region, respectively. | 01-16-2014 |
20140070344 | SYSTEMS AND METHODS FOR IMPLEMENTING MAGNETOELECTRIC JUNCTIONS - Embodiments of the invention implement DIOMEJ cells. In one embodiment, a DIOMEJ cell includes: an MEJ that includes, a ferromagnetic fixed layer, a ferromagnetic free layer, and a dielectric layer interposed between said fixed and free layers, where the fixed layer is magnetically polarized in a first direction, where the free layer has a first easy axis that is aligned with the first direction, and where the MEJ is configured such that when a potential difference is applied across it, the magnetic anisotropy of the free layer is altered such that the relative strength of the magnetic anisotropy along a second easy axis that is orthogonal to the first easy axis, as compared to the strength of the magnetic anisotropy along the first easy axis, is magnified for the duration of the application of the potential difference; and a diode, where the diode and the MEJ are arranged in series. | 03-13-2014 |
20140071728 | READ-DISTURBANCE-FREE NONVOLATILE CONTENT ADDRESSABLE MEMORY (CAM) - Voltage controlled magnetoelectric tunnel junction (MEJ) based content addressable memory is described which provides efficient high speed switching of MEJs toward eliminating any read disturbance of written data. Each cell of said CAM having two MEJs and transistor circuitry for performing a write at voltages of a first polarity, and reads at voltages of a second polarity. If the data searched does not equal the data written in the CAM, then the match line state is changed. | 03-13-2014 |
20140071732 | NONVOLATILE MAGNETO-ELECTRIC RANDOM ACCESS MEMORY CIRCUIT WITH BURST WRITING AND BACK-TO-BACK READS - Voltage controlled magneto-electric tunnel junctions (MEJ) and associated memory devices are described which provide efficient high speed switching of non-volatile magnetic random access memory (MeRAM) devices at high cell densities with multiple word access mechanisms, including a burst mode write of multiple words, and a back-to-back read of two words in consecutive clock cycles. In at least one preferred embodiment, these accesses are performed in a manner that prevents any possibility of a read disturbance arising. | 03-13-2014 |
20140124882 | SYSTEMS AND METHODS FOR IMPLEMENTING MAGNETOELECTRIC JUNCTIONS HAVING IMPROVED READ-WRITE CHARACTERISTICS - Embodiments of the invention implement MEJs having improved read-write characteristics. In one embodiment, an MEJ includes: ferromagnetic fixed and free layers, a dielectric layer interposed between the ferromagnetic layers, and an additional dielectric layer proximate the free layer, where the fixed layer is magnetically polarized in a first direction, where the free layer has a first easy axis that is aligned with the first direction, and where the MEJ is configured such that when subject to a potential difference, the magnetic anisotropy of the free layer is altered such that the relative strength of the magnetic anisotropy along a second easy axis that is orthogonal to the first easy axis, compared to the strength of the magnetic anisotropy along the first easy axis, is magnified during the application of the potential difference, where the extent of the magnification is enhanced by the presence of the additional layer. | 05-08-2014 |
20140169085 | VOLTAGE-CONTROLLED MAGNETIC MEMORY ELEMENT WITH CANTED MAGNETIZATION - A memory cell including information that is stored in the state of a magnetic bit (i.e. in a free layer, FL), where the FL magnetization has two stable states that may be canted (form an angle) with respect to the horizontal and vertical directions of the device is presented. The FL magnetization may be switched between the two canted states by the application of a voltage (i.e. electric field), which modifies the perpendicular magnetic anisotropy of the free layer. | 06-19-2014 |
20140177327 | VOLTAGE-CONTROLLED MAGNETIC ANISOTROPY (VCMA) SWITCH AND MAGNETO-ELECTRIC MEMORY (MERAM) - Voltage controlled magnetic tunnel junctions and memory devices are described which provide efficient high speed switching of non-volatile magnetic devices at high cell densities. Implementations are described which provide a wide range of voltage control alternatives with in-plane and perpendicular magnetization, bidirectionally switched magnetization, and control of domain wall dynamics. | 06-26-2014 |
Patent application number | Description | Published |
20090001419 | Non-Volatile Memory Devices and Methods of Fabricating the Same - Provided are non-volatile memory devices that may realize high integration and have high reliability. A plurality of first semiconductor layers are stacked on a substrate. A plurality of second semiconductor layers are interposed between the plurality of first semiconductor layers, respectively, and are recessed from one end of each of the plurality of first semiconductor layers to define a plurality of first trenches between the plurality of first semiconductor layers. A plurality of first storage nodes are provided on surfaces of the second semiconductor layers inside the plurality of first trenches. Devices may include a plurality of first control gate electrodes that are formed on the plurality of first storage nodes to fill the plurality of first trenches. | 01-01-2009 |
20110089415 | EPITAXIAL GROWTH OF SINGLE CRYSTALLINE MGO ON GERMANIUM - The embodiments disclosed herein relate to growth of magnesium-oxide on a single crystalline substrate of germanium. The embodiments further describes a method of manufacturing and crystalline structure of a FM/MgO/Ge(001) heterostructure. The embodiments further related to method of manufacturing and a crystalline structure for a high-k dielectric//MgO [100](001)//Ge[110](001) heterostructure. | 04-21-2011 |
20110233524 | SPIN TRANSISTOR HAVING MULTIFERROIC GATE DIELECTRIC - A carrier-mediated magnetic phase change spin transistor is disclosed. In general, the spin transistor includes a Dilute Magnetic Semiconductor (DMS) channel and a gate stack formed on the DMS channel. The gate stack includes a multiferroic gate dielectric on the DMS channel, and a gate contact on a surface of the multiferroic gate dielectric opposite the DMS channel. The multiferroic gate dielectric is formed of a multiferroic material that exhibits a cross-coupling between magnetic and electric orders (i.e., magnetoelectric coupling), which in one embodiment is BiFeO | 09-29-2011 |
20130015429 | ALL GRAPHENE FLASH MEMORY DEVICEAANM Hong; Augustin J.AACI Los AngelesAAST CAAACO USAAGP Hong; Augustin J. Los Angeles CA USAANM Kim; Ji-YoungAACI Los AngelesAAST CAAACO USAAGP Kim; Ji-Young Los Angeles CA USAANM Wang; Kang-LungAACI Santa MonicaAAST CAAACO USAAGP Wang; Kang-Lung Santa Monica CA US - A Graphene Flash Memory (GFM) device is disclosed. In general, the GFM device includes a number of memory cells, where each memory cell includes a graphene channel, a graphene storage layer, and a graphene electrode. In one embodiment, by using a graphene channel, graphene storage layer, and graphene electrode, the memory cells of the GFM device are enabled to be scaled down much more than memory cells of a conventional flash memory device. More specifically, in one embodiment, the GFM device has a feature size less than 25 nanometers, less than or equal to 20 nanometers, less than or equal to 15 nanometers, less than or equal to 10 nanometers, or less than or equal to 5 nanometers. | 01-17-2013 |
20140042574 | TUNABLE AND METASTABLE FERROELECTRIC MATERIALS AND MAGNETO-ELECTRIC DEVICES - A ferroelectric device includes a first electrode, a second electrode spaced apart from the first electrode, and a ferroelectric element arranged between the first and second electrodes. The ferroelectric element has a plurality of quasistatic strain configurations that are selectable by the application of an electric field and the device has selectable electromechanical displacement by the application of the electric field. | 02-13-2014 |
20140153325 | BODY VOLTAGE SENSING BASED SHORT PULSE READING CIRCUIT - As memory geometries continue to scale down, current density of magnetic tunnel junctions (MTJs) make conventional low current reading scheme problematic with regard to performance and reliability. A body-voltage sense circuit (BVSC) short pulse reading (SPR) circuit is described using body connected load transistors and a novel sensing circuit with second stage amplifier which allows for very short read pulses providing much higher read margins, less sensing time, and shorter sensing current pulses. Simulation results (using 65-nm CMOS model SPICE simulations) show that our technique can achieve 550 mV of read margin at 1 ns performance under a 1V supply voltage, which is greater than reference designs achieve at 5 ns performance. | 06-05-2014 |