Patent application number | Description | Published |
20080303486 | Apparatuses and methods for detecting power source - A charger includes a detection pin, a voltage divider, and a comparator. The detection pin can couple the charger to a power source via a first data line. The voltage divider and the comparator are coupled to the detection pin. The voltage divider divides a power voltage provided by the power source and provides a detection voltage at the detection pin. The comparator compares the detection voltage with a predetermined reference voltage and identifies a type of the power source according to the comparing. | 12-11-2008 |
20090170930 | METHODS FOR DIRECTING DIFFERENTIATION OF CLONOGENIC NEURAL STEM CELLS WITH COUMARINS - A method for promoting differentiation of clonogenic neural stem cells (NSCs), comprising administering to a patient in the need of such promoting a coumarin compound represented by formula I or by formula II. The representative coumarin compounds include 7-hydroxycoumarin, daphnoretin, scopoletin, edgeworin, aesculetin and esculetin-6-β-D-glucopyranoside. The coumarin compounds showed significant activity of directing the differentiation of NSCs in pharmacological test and thereof could be used to prepare drugs to direct NSCs differentiated to oligodendrocyte progenitor cells (OPCs) for the treatment of demyelinating diseases or spinal cord injury. The drug could be a pure coumarin compound or a pharmaceutical composition comprising a therapeutical dose of a coumarin compound as active ingredients and a pharmaceutically-acceptable carrier. The content of the active ingredients in the pharmaceutical composition is between 0.1% and 99.5% by weight. | 07-02-2009 |
20100197927 | Protein Tyrosine Phosphatase 1B Inhibitor, Preparation Methods and Uses Thereof - PTP1B inhibitors with the following structure (formula I). Experiments indicate that these inhibitors can effectively inhibit the activity of protein tyrosine phosphatase 1B (PTP1B). They can be used as insulin sensitisers. They can be used to prevent, delay or treat diseases which are related to insulin antagonism mediated by PTP1B, especially diabetes type II and obesity. The invention also provides methods for preparing these inhibitors. | 08-05-2010 |
20110006731 | VEHICLE ELECTRONIC SYSTEMS WITH BATTERY MANAGEMENT FUNCTIONS - An electronic system in a vehicle includes a motor, a charger, a battery pack, and a bus. The motor drives wheels and propellers of the vehicle. The charger generates charging power according to a control signal. The battery pack coupled to the charger and the motor is operable for generating the control signal based upon a status of each cell of multiple cells in the battery pack, for receiving the charging power via a charging path when the vehicle is stalled, and for powering the motor via a discharging path when the vehicle is started. The bus coupled to the charger and the battery pack is operable for transmitting the control signal from the battery pack to the charger. | 01-13-2011 |
20110074433 | BATTERY CAPACITY DETECTION FOR MULTI BATTERY CELLS - A battery gas gauge includes a voltage detection unit and a processor. The voltage detection unit is coupled to a battery pack and can measure a plurality of open circuit voltages of a plurality of cells in the battery pack respectively. The processor is coupled to the voltage detection unit and can determine a minimum open circuit voltage of the open circuit voltages, and can determine a first relative state of charge of the battery pack based on a relationship between the minimum open circuit voltage and a corresponding relative state of charge of a cell having the minimum open circuit voltage. | 03-31-2011 |
20110089897 | BATTERY PACK WITH BALANCING MANAGEMENT - A battery management system for a battery pack comprising multiple battery modules is disclosed. Each of the battery modules includes multiple battery cells. The battery management system includes multiple first balancing units, multiple first controllers, a second balancing unit including multiple second balancing circuits, and a second controller coupled to the battery modules and the second balancing circuits. The first controllers are operable for controlling the first balancing units to adjust voltages of battery cells in the battery module if an unbalance occurs between the battery cells. The second controller is operable for controlling said second balancing circuits to adjust voltages of said battery modules if an unbalance occurs between battery modules. | 04-21-2011 |
20110121645 | BATTERY MANAGEMENT SYSTEMS AND METHODS - A battery management system includes a switch array, a first controller and a second controller. The switch array selects a battery module from multiple battery modules in a battery pack based upon a conduction state of the switch array. The first controller is coupled to the switch array and receives measurement information of cells in the battery pack through the switch array. The second controller is coupled to the switch array and the first controller and provides a control signal to control the conduction state of the switch array. The first controller further controls a balance circuit coupled to the battery pack to balance a selected battery module if the selected battery module is identified as an unbalanced battery module based upon measurement information associated with the selected battery module. | 05-26-2011 |
20110140650 | BATTERY PACK WITH BALANCING MANAGEMENT - A battery management system for a battery pack comprising multiple battery modules is disclosed. Each of the battery modules includes multiple battery cells. The battery management system includes multiple first balancing units, multiple first controllers, a second balancing unit including multiple second balancing circuits, and a second controller coupled to the battery modules and the second balancing circuits. The first controllers are operable for controlling the first balancing units to adjust voltages of battery cells in the battery module if an unbalance occurs between the battery cells. The second controller is operable for controlling said second balancing circuits to adjust voltages of said battery modules if an unbalance occurs between battery modules. | 06-16-2011 |
20110148324 | METHODS AND SYSTEMS FOR LED DRIVER HAVING CONSTANT OUTPUT CURRENT - A control circuit for a switched mode power supply includes a transconductance amplifier circuit for receiving a voltage signal related to a current from an input of the power supply and producing a first signal, an analog signal processor coupled to the amplifier circuit for receiving the first signal and a second signal from the input of the power supply and a third signal from an output of the power supply. The analog signal processor is configured to produce a fourth signal as a function of the first, the second, and the third signals. An adder circuit is coupled to the fourth signal and a dimmer control signal, and the adder circuit is configured to output a fifth signal. A comparator circuit is coupled to the adder circuit for providing a control signal to a power transistor that controls current flow in the power supply based on comparison of the fifth signal and a reference signal. | 06-23-2011 |
20110216687 | Method and Apparatus for Accounting Multicast Broadcast Service - In a method for accounting a multicast broadcast service (MBS), an Access Service Network (ASN) receives MBS service accounting information sent by an MBS accounting agent. The MBS service accounting information includes an MBS service identifier and MBS service granularity-based accounting information. A mobile station (MS) is determined using the MBS service according to the MBS service identifier. Subscriber service granularity-based accounting information of the MS is generated and the generated accounting information is sent to an accounting system. | 09-08-2011 |
20110234170 | CIRCUITS, SYSTEMS AND METHODS FOR BALANCING BATTERY CELLS - A circuit for balancing a plurality of battery cells includes a controller and an electronic control unit (ECU) coupled to the controller. The controller samples multiple discharging cell voltages of the battery cells respectively at a predetermined time during a discharging state of the battery cells, and samples multiple charging cell voltages of the battery cells respectively during a charging state of the battery cells. The ECU processes the charging cell voltages and the discharging cell voltages, thereby providing control commands for the controller to control the battery cells to achieve a balance. | 09-29-2011 |
20110241622 | SYSTEMS AND METHODS FOR CELL BALANCING - A method for balancing multiple battery cells which are grouped into multiple battery modules includes: obtaining cell parameters of the battery cells, respectively; calculating an average cell parameter for each of the battery modules according to the cell parameters; identifying a donator module and a receiver module from the battery modules based upon the average cell parameter; and transferring energy from the donator module to the receiver module to balance the battery cells. | 10-06-2011 |
20110250868 | METHOD, SERVER, AND SYSTEM FOR CONFIGURING PAGING GROUP AND NEIGHBOR CELL LIST OF FEMTO ACCESS POINT - A method, a server, and a system for configuring a paging group (PG) and a neighbor cell list of a femto access point (FAP) are provided. The method includes: receiving a configuration request from a security gateway or an FAP; acquiring location information of the FAP; determining an access service network gateway (ASN-GW) accessed by the FAP, and notifying the location information of the FAP to the ASN-GW, so that the ASN-GW allocates a PG to the FAP according to the location information of the FAP, and delivers an identifier (ID) of the allocated PG; and receiving the ID of the PG from the ASN-GW, and delivering the ID of the PG to the FAP. Therefore, the FAP can dynamically join into a PG and the neighbor cell list can be dynamically updated. | 10-13-2011 |
20110286439 | METHOD AND SYSTEM FOR IMPLEMENTING LOCAL SWITCHING - A method and a system for implementing local switching are disclosed. The method includes: after receiving the uplink data sent by a sending MS, determining, according to information carried in the uplink data, information about location of a receiving Mobile Station (MS) that is to receive uplink data; and implementing, according to local switching rules that specify a local switching control mode, local switching for data transmitted between the sending MS and the receiving MS if determining, according to the information about location of the receiving MS and information about location of the sending MS, that the data transmitted between the sending MS and the receiving MS meets local switching conditions. In this way, network transmission resources are saved in the process of transmitting data, transmission delay is shortened, and data transmission efficiency is improved. | 11-24-2011 |
20110289237 | INTELLIGENT BUS ADDRESS SELF-CONFIGURATION IN A MULTI-MODULE SYSTEM - According to one aspect there is disclosed an apparatus. The apparatus may include a first module including at least one bus port configured to couple the first module to a bus; a first configuration port configured to receive an input indicating whether address assignment is enabled or disabled for the first module; a second configuration port configured to provide an output indicating whether address assignment is enabled or disabled for a second module; a memory configured to store a unique address, wherein the unique address is configured to identify the first module; and a controller configured to be coupled to a central management unit via the bus, the controller further configured to receive the unique address from the central management unit, determine whether address assignment is enabled for the first module and to store the unique address in the memory if address assignment is enabled for the first module, enable or disable address assignment for a second module when the second module is coupled to the first module, and the controller further configured to enable or disable address assignment for the second module based, at least in part, on a message from the central management unit. | 11-24-2011 |
20110316483 | BATTERY PACK WITH BALANCING MANAGEMENT - A battery management system for a battery pack includes a plurality of battery modules and a plurality of first balancing units coupled to the plurality of battery modules. The battery management system also includes a plurality of second balancing units coupled to the plurality of battery modules, wherein a first balancing unit of the plurality of first balancing units and a second balancing unit of the plurality of second balancing units are coupled to each respective battery module. Lastly, the battery management system includes a plurality of controllers coupled to the plurality of battery modules, wherein each controller is coupled to a respective battery module. A first controller of the plurality of controllers is operable to control a first balancing unit of a first battery module to adjust a voltage output of the first battery module when the first controller determines the voltage output of the first battery module is greater than a combined voltage output of the first battery module and a second battery module. The first controller of the plurality of controllers is further operable to control a second balancing unit of the first battery module to adjust the combined voltage output of the first battery module and the second battery module when the first controller determines the combined voltage output of the first battery module and the second battery module is greater than the voltage output of the first battery module. | 12-29-2011 |
20120007603 | CIRCUITS AND METHODS FOR CELL NUMBER DETECTION - A circuit used for determining a cell number of several battery cells. The circuit includes a detection block and a controller, and operates in a first detection mode and a second detection mode. The detection block is coupled to each of the battery cells. In the first detection mode, the detection block provides a terminal voltage signal indicative of a terminal voltage of a battery cell. In the second detection mode, the detection block provides a cell voltage signal indicative of a cell voltage of the battery cell. The controller compares the terminal voltage signal with a first threshold in the first detection mode and compares the cell voltage signal with a second threshold in the second detection mode, and provides a cell count signal indicative of the cell number based on the terminal voltage signal and the cell voltage signal. | 01-12-2012 |
20120099481 | METHOD AND SYSTEM FOR OBTAINING A DEPLOYMENT SCHEME OF WIRELESS LOCAL AREA NETWORK ACCESS POINTS - A method for obtaining a deployment scheme of Wireless Local Area Network (WLAN) Access Points (APs) is provided. The method includes obtaining coverage information of each AP according to a WLAN competition model and deployment information; and combining a constraint relationship between the coverage information of each AP and cost information of each AP, and obtaining the deployment scheme of the APs through calculation. A device and a system are further provided, so as to automatically obtain a deployment scheme of APs, and control the cost. | 04-26-2012 |
20120106663 | METHOD FOR TRANSMITTING DATA - Embodiments in accordance with the present invention provide a method for transmitting a data frame between a battery management system (BMS) and an associated device. The battery management system is coupled to an associated device via a one-wire bi-directional communication line. The method includes obtaining a control right of the one-wire bi-directional communication line and determining a target device based on a frame header by sending the frame header of a data frame by a source device; sending a specific data byte of the data frame from the source device to the target device; checking whether an acknowledge character from the target device is received by the source device within a predetermined time period; and releasing the control right of the one-wire bi-directional communication line if the acknowledge character is received within the predetermined time period by the source device or otherwise resending the data frame. | 05-03-2012 |
20120112703 | System and Method for Managing a Battery - A method for managing a battery with multiple battery cells is disclosed. The method includes monitoring parameters of the battery cells by an information acquisition unit. Parameters of the battery cells include individual cell voltages. The method further includes selecting, by a controller one of multiple charging modes in which the battery cells are charged according to the cell voltages. The charging modes include a constant current charging mode, a constant voltage charging mode, and a pulse charging mode. | 05-10-2012 |
20120139482 | BATTERY CHARGING MANAGEMENT - A battery charging management apparatus includes an information obtaining unit and a controlling unit coupled to the information obtaining unit. The information obtaining unit obtains parameter information for temperature of a battery during a charging process performed by a charger for the battery. The controlling unit controls the charger to charge the battery based on the parameter information of the battery, so that operation of the charger conforms to a charging rule corresponding to the charging process. The controlling unit decreases a charging signal of the charger by a predetermined decrement if the temperature of the battery increases by a predefined increment. | 06-07-2012 |
20120177052 | USER-ORIENTED COMMUNICATION METHOD, ROUTE REGISTRATION METHOD AND DEVICE, AND COMMUNICATION SYSTEM - Embodiments of the present disclosure disclose a user-oriented communication method, a route registration method and device, and a communication system. In the method, a first domain router receives a first data packet sent by a first terminal. The first data packet includes a user identifier of a first user and a user identifier of a second user, the first terminal belongs to the first user, and a second terminal belongs to the second user. The first domain router queries for a second domain router connected to the second terminal according to the user identifier of the second user and sends the first data packet to the second domain router, so that the second domain router sends the first data packet to the second terminal. | 07-12-2012 |
20120182063 | Power Device Using Photoelectron Injection to Modulate Conductivity and the Method Thereof - The present invention belongs to the technical field of semiconductor devices, and discloses a power device using photoelectron injection to modulate conductivity and the method thereof. The power device comprises at least one photoelectron injection light source and a power MOS transistor. The present invention uses photoelectron injection method to inject carriers to the drift region under the gate of the power MOS transistor, thus modulating the conductivity and further decreasing the specific on-resistance of the power MOS transistor. Moreover, as the doping concentration of the drift region can be decreased and the blocking voltage can be increased, the performance of the power MOS transistor can be greatly improved and the application of power MOS transistor can be expanded to high-voltage fields. | 07-19-2012 |
20120182995 | METHOD AND SYSTEM FOR DATA TRANSMISSION - A method for data transmission includes: a router receives a data packet sent by an access device of a first user, where the data packet carries target device selection information including at least a user identity of a second user, and the user identity is associated with at least one access device of the second user; the router obtains a routing address of an optimal access device among access devices associated with the user identity; and the router sends the data packet to the optimal access device according to the routing address. | 07-19-2012 |
20120200342 | GATE CONTROLLED PN FIELD-EFFECT TRANSISTOR AND THE CONTROL METHOD THEREOF - The present invention belongs to the technical field of semiconductor devices, and more specifically, relates to a gate-controlled PN field-effect transistor and the control method thereof The gate-controlled PN field-effect transistor disclosed by the present invention comprises a semiconductor substrate region, a drain region and a source region on the left and right sides of the substrate region, and gate regions on the upper and lower sides of the substrate region. The gate-controlled PN field-effect transistor works in the positive bias state of the source-drain PN junction and is conducted from the middle of the substrate region. The gate-controlled PN field-effect transistor provided by the present invention decreases the leakage current and increases the drive current at the same time, namely decreases the chip power consumption and improves the chip performances at the same time. The present invention further discloses a method for controlling the gate-controlled PN field-effect transistor, including cut-off and conduction operation. | 08-09-2012 |
20120225327 | BATTERY WITH EMBEDDED DETECTING UNITS - A battery includes multiple battery cells separated by isolating plates, and multiple detecting units coupled to the battery cells and operable for detecting a status of the battery cells. The battery further includes multiple interfaces coupled to the detecting units and operable for receiving detecting results indicating the status from the detecting units. After the battery is airproofed, the battery cells and the detecting units are enveloped inside the battery. | 09-06-2012 |
20120261669 | PHOTO DETECTOR CONSISTING OF TUNNELING FIELD-EFFECT TRANSISTORS AND THE MANUFACTURING METHOD THEREOF - The present invention belongs to the technical field of optical interconnection and relates to a photo detector, in particular to a photo detector consisting of tunneling field-effect transistors. | 10-18-2012 |
20120261744 | MICROELECTRONIC DEVICE STRUCTURE AND MANUFACTURING METHOD THEREOF - The present invention refers to a semiconductor device especially a tunneling filed effect transistor (TFET) using narrow bandgap material as the source electrode material. A Semiconductor device which is a tunneling field effect transistor type semiconductor device, in which the source material is characterized as narrow band-gap material; meanwhile, there is a u-groove channel. The narrow band-gap material results in a raise of driving current and the u-groove channel reduced drain leakage current. The TFET disclosed in to present invention has the advantages of low leakage current, high drive current, and high integration density. The static power consumption is also reduced by using the present invention. The integration density is improved as well. | 10-18-2012 |
20120273866 | Semiconductor Memory Device with a Buried Drain and Its Memory Array - A semiconductor memory device with a buried drain is provided. The device comprises a semiconductor substrate ( | 11-01-2012 |
20120305880 | RESISTIVE RANDOM ACCESS MEMORY WITH ELECTRIC-FIELD STRENGTHENED LAYER AND MANUFACTURING METHOD THEREOF - This invention belongs to the technical field of memories and specifically relates to a resistive random access memory structure with an electric-field strengthened layer and a manufacturing method thereof. The resistive random access memory in the present invention can include a top electrode, a bottom electrode and a composite layer which is placed between the top electrode and the bottom electrode and have a first resistive switching layer and a second resistive switching and electric-field strengthened layer; the second resistive switching and electric-field strengthened layer cab be adjacent to the first resistive switching layer and have a dielectric constant lower than that of the first resistive switching layer. The electric-field distribution in the RRAM unit is adjustable. | 12-06-2012 |
20120305882 | NiO-based Resistive Random Access Memory and the Preparation Method Thereof - The present invention belongs to the technical field of memory storage and specially relates to a NiO-based resistive random access memory system (RRAM) and a preparation method thereof. The RRAM is comprised of a substrate and a metal-insulator-metal (MIM) structure, wherein the electrodes are metal films, such as copper, aluminum, etc., capable of being applied to the interconnection process, and the resistive switching insulator is an Al | 12-06-2012 |
20120309118 | SILICON WAFER ALIGNMENT METHOD USED IN THROUGH-SILICON-VIA INTERCONNECTION - A method of silicon wafer alignment used in through-silicon-via interconnection for use in the field of high-integrity packaging technology is disclosed. In one aspect, the method includes aligning and calibrating the upper and lower silicon wafers, stacked and interconnected electrically, so as to improve alignment accuracy of silicon wafers and reduce interconnection resistances. In some embodiments, the integrated circuit chip made by the method improves speed and energy performance. | 12-06-2012 |
20120328588 | COMPOUND PREPARATION AND ITS USES FOR PREVENTION AND TREATMENT OF HEARING IMPAIRMENT - A compound preparation contains alpha-lipoic acid and nimodipine at a ratio from 5:1 to 40:1. The above-mentioned compound preparation can be used for the prevention and treatment of noise-induced hearing impairment. This compound preparation not only increases the efficacy but decreases the dosage of nimodipine, reduces the side effects and improves the patient compliance. | 12-27-2012 |
20130016643 | METHOD AND DEVICE FOR CONTROLLING MULTI-CARRIER FREQUENCY POWER AMPLIFIER RESOURCES - A control method and device for multi-carrier frequency power amplifier resources includes service data which is first distributed to a primary carrier frequency board; if it is determined that channel resource blocks of the primary carrier frequency board are all distributed with the service data, the rest service data is distributed to a secondary carrier frequency board according to a sequence of time slots, and if the primary carrier frequency board is not completely distributed with the service data, skip this step; after the service data is scheduled, an energy-saving operation may be started for the primary carrier frequency board in the time slot in which a carrier frequency can be turned off and for the secondary carrier frequency board, so as to eliminate static power consumption of the power amplifier. | 01-17-2013 |
20130020970 | Control System and Control Method for Electric Bicycle - A system and methods for controlling an electric motor in an electric vehicle. The system includes a battery management system and a motor controller. The battery management system monitors output voltage of each individual cell unit in a battery pack with a plurality of cell units and generates a state signal and a count value according to the monitored output voltages. The motor controller receives the state signal and the count value from the battery management system and controls the output current to the electrical motor. The battery management system generates the state signal in a first state if none of the monitored output voltages is below a predefined voltage for longer than a predefined period. The battery management system increases the count value each time a monitored output voltage drops below the predefined voltage. The cell units in the battery pack are protected by the battery management system. | 01-24-2013 |
20130033231 | SYSTEMS AND METHODS FOR BALANCING BATTERY CELLS - A cell balancing system includes multiple bypass paths and a battery management circuit. The multiple bypass paths are coupled in parallel to the battery cells. The battery management circuit is coupled to the bypass paths and monitors cell voltages of the battery cells, compares the cell voltages with a first reference voltage for a first stage, enables a bypass path in the first stage if a battery cell in parallel with the bypass path has a cell voltage at the first reference voltage, and compares the cell voltages of the battery cells with a second reference voltage for a second stage if a specified cell voltage in the first stage is at the first reference voltage. | 02-07-2013 |
20130055553 | SYSTEMS AND METHODS FOR GROUPING BATTERIES - Methods and systems for grouping multiple battery modules in a battery pack are disclosed. Multiple characteristic parameters of multiple cells in a battery module of the battery modules are measured to produce a measured result. Multiple differences between the multiple characteristic parameters are calculated according to the measured result. The battery module is classified according to the multiple differences. | 03-07-2013 |
20130056848 | INDUCTIVE LOOP FORMED BY THROUGH SILICON VIA INTERCONNECTION - The present invention discloses an inductive element formed by through silicon via interconnections. The inductive element formed by means of the special through silicon via interconnection by using through silicon via technology features advantages such as high inductance and density. Moreover, the through silicon via interconnection integrated process forming the inductive element is compatible with the ordinary through silicon interconnection integrated process without any other steps, thus making the process simple and steady. The inductive element using the present invention is applicable to the through silicon via package manufacturing of various chips, especially the package manufacturing of power control chips and radio-frequency chips. | 03-07-2013 |
20130061805 | EPITAXIAL WAFER SUSCEPTOR AND SUPPORTIVE AND ROTATIONAL CONNECTION APPARATUS MATCHING THE SUSCEPTOR - Disclosed is an epitaxial wafer susceptor and a supportive and rotational connection apparatus matching the susceptor used for an MOCVD reaction chamber. The susceptor comprises a top surface and a susceptor rotating shaft protruding downward. A vertical driving shaft is coupled to the susceptor. The driving shaft comprises a counter bore inside an upper end of the driving shaft. At least a part of the susceptor rotating shaft is inserted into the counter bore if the susceptor is loaded. The susceptor is positioned and supported in the reaction chamber via coupling and connection between a contact surface of the susceptor rotating shaft and a corresponding contact surface of the counter bore. The susceptor is driven to rotate by the driving shaft if the driving shaft rotates. Reactant gases are introduced into the reaction chamber for an epitaxial reaction or a film deposition on the epitaxial wafers placed on the susceptor. | 03-14-2013 |
20130062684 | GATE STACK STRUCTURE AND FABRICATING METHOD USED FOR SEMICONDUCTOR FLASH MEMORY DEVICE - The invention relates to a gate stack structure suitable for use in a semiconductor flash memory device and its fabricating method. The gate stack structure is fabricated on a p-type 100 silicon substrate, which also includes the following components in sequence from bottom to top: a charge tunnel layer of Al | 03-14-2013 |
20130065365 | Method for Manufacturing Semiconductor Substrate of Large-power Device - The invention belongs to the technical field of high-voltage, large-power devices and in particular relates to a method for manufacturing a semiconductor substrate of a large-power device. According to the method, the ion implantation is carried out on the front face of a floating zone silicon wafer first, then a high-temperature resistant metal is used as a medium to bond the back-off floating zone silicon wafer, and a heavily CZ-doped silicon wafer forms the semiconductor substrate. After bonding, the floating zone silicon wafer is used to prepare an insulated gate bipolar transistor (IGBT), and the heavily CZ-doped silicon wafer is used as the low-resistance back contact, so the required amount of the floating zone silicon wafers used is reduced, and production cost is lowered. Meanwhile, the back metallization process is not required after bonding, so the processing procedures are simplified, and the production yield is enhanced. | 03-14-2013 |
20130069704 | ONE-WIRE COMMUNICATION CIRCUIT AND ONE-WIRE COMMUNICATION METHOD - A communication circuit facilitating communication between a first equipment and a second equipment including a conversion circuit, an input port, an output port, and a communication port is disclosed. The conversion circuit converts an input signal to a first intermediate signal, and converts a second intermediate signal to an output signal. The input port inputs the input signal to the first conversion circuit. The output port outputs the output signal to the control unit. The communication port inputs the second intermediate signal to the conversion circuit, and outputs the first intermediate signal to the second equipment. A voltage of the first intermediate signal is determined based on a voltage of a power source if the first intermediate signal is logic high, and a voltage of the second intermediate signal is determined based on the voltage of the power source if the second intermediate signal is logic high. | 03-21-2013 |
20130078761 | METHOD FOR MANUFACTURING A FLEXIBLE TRANSPARENT 1T1R STORAGE UNIT BASED ON A COMPLETELY LOW-TEMPERATURE PROCESS - The present invention belongs to the technical field of low temperature atomic layer deposition technology, and specifically relates to a method for manufacturing a flexible transparent 1T1R storage unit. In the present invention, a fully transparent 1T1R storage unit is developed on a flexible substrate through a completely low-temperature process, including an oxide layer dielectric, a transparent electrode and a transparent substrate which are deposited together through a low-temperature process, thus realizing a fully transparent device capable of achieving the functions of nontransparent devices. The present invention can be applied to the manufacturing of flexible low-temperature storage units in the future, as well as changing the packaging and existing modes of devices, which will make foldable and bendable portable storage units possible. | 03-28-2013 |
20130078793 | METHOD FOR DEPOSITING A GATE OXIDE AND A GATE ELECTRODE SELECTIVELY - The present invention belongs to the technical field of integrated semiconductor circuits, and relates to a method for depositing a gate oxide and a gate electrode selectively. The present invention makes use of Octadecyltriethoxysilane's (ODTS') easy attachment to the Si—OH interface and difficult attachment to the Si—H interface, and selectively deposits the gate oxide and gate electrode materials, which avoids the unnecessary waste of materials and saves cost. Meanwhile, the present invention will transfer the etching of the gate oxide and gate electrode into the etching of SiO | 03-28-2013 |
20130078797 | METHOD FOR MANUFACTURING A COPPER-DIFFUSION BARRIER LAYER USED IN NANO INTEGRATED CIRCUIT - The present invention belongs to the technical field of integrated semiconductor circuits, and relates to a method for manufacturing a copper-diffusion barrier layer. In the present invention, a proper reaction precursor has been selected and the atomic layer deposition (ALD) technology has been adopted to develop Co or Ru on a TaN layer to obtain a diffusion barrier layer used in the interconnection for process nodes no more than 32 nm, which overcomes the insufficiency of the PVD deposition Ta/TaN double-layer structure as the copper-diffusion barrier layer in step coverage and conformity, and also effectively solves various serious problems in the Cu/low-k dual damascene process, such as the generation of voids in grooves and through-holes, and electromigration stability. | 03-28-2013 |
20130078798 | METHOD FOR IMPROVING THE ELECTROMIGRATION RESISTANCE IN THE COPPER INTERCONNECTION PROCESS - The present invention belongs to the technical field of integrated semiconductor circuits, and relates to a method used in a process no greater than 32 nm to improve the electromigration resistance of Cu interconnects. Coating layers on Cu interconnects, such as CuSi | 03-28-2013 |
20130078819 | METHOD FOR CLEANING & PASSIVATING GALLIUM ARSENIDE SURFACE AUTOLOGOUS OXIDE AND DEPOSITING AL2O3 DIELECTRIC - The present invention belongs to the technical field of semiconductor materials and specifically relates to a method for cleaning & passivizing gallium arsenide (GaAs) surface autologous oxide and depositing an Al | 03-28-2013 |
20130092902 | NANOWIRE TUNNELING FIELD EFFECT TRANSISTOR WITH VERTICAL STRUCTURE AND A MANUFACTURING METHOD THEREOF - The present invention belongs to the technical field of semiconductor devices and specifically relates to a method for manufacturing a nanowire tunneling field effect transistor (TFET). In the method, the ZnO nanowire required is developed in a water bath without the need for high temperatures and high pressure, featuring a simple solution preparation, convenient development and low cost, as well as constituting MOS devices of vertical structure with nanowire directly, thus omitting the nanowire treatment in the subsequent stage. The present invention has the advantages of simple structure, convenient manufacturing, and low cost, and control of the nanowire channel developed and the MOSFET array with vertical structure made of it though the gate, so as to facilitate the manufacturing of large-scale MOSFET array directly. | 04-18-2013 |
20130093238 | POWER MANAGEMENT FOR ELECTRIC VEHICLES - An apparatus for managing power in an electric vehicle includes a control circuit and a first switch. The control circuit is configured to generate a first control signal based on a current of a battery operable for powering the electric vehicle, and to generate a second control signal based on a voltage of the battery. The first switch is configured to control connection of the battery to a power source and a load in the electric vehicle according to the first control signal. The first control signal controls a voltage at a terminal of the first switch to maintain the current of the battery to be substantially equal to a current setting, and the second control signal controls the battery to switch between a first state and a second state. | 04-18-2013 |
20130099723 | SYSTEMS AND METHODS FOR CELL BALANCING - A method for balancing multiple battery cells which are grouped into multiple battery modules includes: obtaining cell parameters of the battery cells, respectively; calculating an average cell parameter for each of the battery modules according to the cell parameters; identifying a donator module and a receiver module from the battery modules based upon the average cell parameter; and transferring energy from the donator module to the receiver module to balance the battery cells. | 04-25-2013 |
20130121252 | Information Push Method, Apparatus, and System - The present invention provides a new Push method, apparatus, and system. The Push method includes: receiving a Push message delivered by an application server; obtaining a private IP address of a UE according to a user identifier, where the user identifier is obtained from the Push message; and obtaining, according to the private IP address of the UE, a PS domain node currently connected to the UE, sending the Push message to the PS domain node, and sending the Push message to the UE through the PS domain node. | 05-16-2013 |
20130126954 | Dynamic Random Access Memory Array and Method of Making - The present invention is related to microelectronic technologies, and discloses specifically a dynamic random access memory (DRAM) array and methods of making the same. The DRAM array uses vertical MOS field effect transistors as array devices for the DRAM, and a buried metal silicide layer as buried bit lines for connecting multiple consecutive vertical MOS field effect transistor array devices. Each of the vertical MOS field-effect-transistor array devices includes a double gate structure with a buried layer of metal, which acts at the same time as buried word lines for the DRAM array. The DRAM array according to the present invention provides increased DRAM integration density, reduced buried bit line resistivity, and improved memory performance of the array devices. The present invention also provides a method of making a DRAM array. | 05-23-2013 |
20130134070 | Method for Seperating Carbon Nanotubes with Different Conductive Properties - This invention belongs to the technical field of integrated circuit manufacturing and specifically relates to a method for separating carbon nanotube materials with different conductive properties. The method is comprised of: immersing an integrated circuit material containing metallic carbon nanotubes and semiconductor carbon nanotubes into fluid; introducing the fluid into the same container from the same inlet; on the four sides of the container, forming an electric field and arranging a pair of magnetic poles generating magnetic lines vertical to the electric field; changing the direction and intensity of the electric lines of the electric field and those of the magnetic fields to separate the metallic carbon nanotubes from the semiconductor carbon nanotubes. By means of the method of this invention, the purity of the obtained semiconductor carbon nanotubes and the metallic carbon nanotubes is high, so the product yield of the integrated circuit containing the semiconductor carbon nanotubes is capable of being greatly enhanced. This method is simple, easy, low in cost and capable of greatly reducing the manufacturing cost of high-purity carbon nanotubes. | 05-30-2013 |
20130140625 | Field-Effect Transistor and Method of Making - The present invention belongs to the field of microelectronic device technologies. Specifically, an asymmetric source/drain field-effect transistor and its methods of making are disclosed. A structure of the field-effect transistor comprises: a semiconductor substrate, a gate structure, and a source region and a drain region having a mixed junction and a P-N junction, respectively. The source region and the drain region are asymmetrical structured with respect to each other, one of which comprises a P-N junction, and the other of which comprises a mixed junction, the mixed junction being a combination of a Schottky junction and a P-N junction. According to the present disclosure, a location of a doped region formed by ion implantation is controlled by adjusting an implantation angle, and a unique structure is formed for the asymmetric source/drain field-effect transistor. | 06-06-2013 |
20130149824 | METHOD FOR MANUFACTURING A TUNNELING FIELD EFFECT TRANSISTOR WITH A U-SHAPED CHANNEL - The present invention belongs to the technical field of semiconductor device manufacturing and specifically relates to a method for manufacturing a tunneling field effect transistor with a U-shaped channel. The U-shaped channel can effectively extend the transistor channel length, restrain the generation of leakage current in the transistor, and decrease the chip power consumption. The method for manufacturing a tunneling field effect transistor with a U-shaped channel put forward in the present invention is capable of realizing an extremely narrow U-shaped channel, overcoming the alignment deviation introduced by photoetching, and improving the chip integration degree. | 06-13-2013 |
20130149848 | METHOD FOR MANUFACTURING VERTICAL-CHANNEL TUNNELING TRANSISTOR - The present invention belongs to the technical field of semiconductors and specifically relates to a method for manufacturing a vertical-channel tunneling transistor. In the present invention, the surrounding gate gate structure improves the control capacity of the gate and the source of narrow band gap material can enhance the device driving current. The method for manufacturing a vertical-channel tunneling transistor put forward by the present invention capable of controlling the channel length precisely features simple process, easy control and reduction of production cost. | 06-13-2013 |
20130162959 | Brightness-adjustable Light-emitting Device and Array and the Manufacturing Methods Thereof - The present invention belongs to the technical field of semiconductor devices and relates to a brightness-adjustable illuminator and an array and the manufacturing methods thereof. The illuminator is comprised of a semiconductor substrate, a MOSFET and a light-emitting diode that are located on the semiconductor substrate. The light-emitting diode (LED) and the control element (MOSFET) thereof are integrated on the same chip, so a single chip is capable of realizing the image transmission. An illuminator array may consist of a plurality of illuminators. Meanwhile, the invention also discloses a method for manufacturing the illuminator. Therefore, the projection equipment manufactured by the technology of the present invention has the advantages of small size, portability, low power consumption, etc. Furthermore, the use of the integrated circuit chip greatly simplifies the system of the projection equipment, reduces the production cost and greatly enhances the pixel quality and brightness. | 06-27-2013 |
20130173757 | Method, System, Push Client, and User Equipment for Service Communication - The present invention discloses a method, a system, a Push client, and a user equipment for service communication. The method disclosed in the present invention includes that: A source Push client generates a Push message, where the Push message carries a destination user Push identifier for identifying a destination user; the source Push client sends the Push message to a destination Push server to which the destination user belongs; the destination Push server obtains, according to the destination user Push identifier, a network address for reaching a destination Push client; and the destination Push server sends, based on the network address, the Push message to the destination Push client. With the present invention, communication of various services can be established without relying on a third party application server, which can reduce power consumption of a terminal and save network resources. | 07-04-2013 |
20130178012 | METHOD FOR MANUFACTURING A GATE-CONTROL DIODE SEMICONDUCTOR DEVICE - This invention belongs to semiconductor device manufacturing field and discloses a method for manufacturing a gate-control diode semiconductor device. When the gate voltage is relatively high, the channel under the gate is of n-type and the device is of a simple gate-control pn junction structure; by way of controlling the effective n-type concentration of the ZnO film through back-gate control, inverting the n-type ZnO into p-type through the gate, and using NiO as a p-type semiconductor, an n-p-n-p doping structure is formed. The method features capacity of manufacturing gate-control diode devices able to reduce chip power consumption through the advantages of high driving current and small sub-threshold swing. The present invention using a low temperature process production is especially applicable to the manufacturing of semiconductor devices based on flexible substrates and reading & writing devices that have a flat panel display and phase change memory. | 07-11-2013 |
20130178013 | METHOD FOR MANUFACTURING A GATE-CONTROL DIODE SEMICONDUCTOR DEVICE - This invention belongs to semiconductor device manufacturing field and discloses a method for manufacturing a gate-control diode semiconductor device. When the gate voltage is relatively high, the channel under the gate has an n type and the device has a simple gate-control pn junction structure; by way of controlling the effective n-type concentration of the ZnO film through back-gate control, inverting the n-type ZnO into p-type through the gate and using NiO as a p-type semiconductor, an n-p-n-p doping structure is formed. The present invention features capacity of manufacturing gate-control diode devices able to reduce the chip power consumption through the advantages of a high driving current and small sub-threshold swing, is especially applicable to the manufacturing of reading & writing devices having flat panel displays & phase change memory, and semiconductor devices based on flexible substrates. | 07-11-2013 |
20130178014 | METHOD FOR MANUFACTURING A GATE-CONTROL DIODE SEMICONDUCTOR MEMORY DEVICE - This invention belongs to semiconductor device manufacturing field and discloses a method for manufacturing a gate-control diode semiconductor storage device. When the floating gate voltage is relatively high, the channel under the floating gate is of n type and a simple gate-control pn junction structure is configured; by controlling effective n-type concentration of the ZnO film through back-gate control, inverting the n-type ZnO into p-type through a floating gate and using NiO as a p-type semiconductor, an n-p-n-p doping structure is formed while the quantity of charges in the floating gate determines the device threshold voltage, thus realizing memory functions. This invention features capacity of manufacturing gate-control diode memory devices able to reduce the chip power consumption through advantages of high driving current and small sub-threshold swing. This invention is applicable to semiconductor devices manufacturing based on flexible substrate and flat panel displays and floating gate memories, etc. | 07-11-2013 |
20130187278 | STRUCTURE FOR INTERCONNECTING COPPER WITH LOW DIELECTRIC CONSTANT MEDIUM AND THE INTEGRATION METHOD THEREOF - The present invention belongs to the technical field of semiconductor devices, and discloses a structure for interconnecting a medium of low dielectric constant with copper and the integration method thereof. It includes: using a combination of copper interconnections and air gaps to reduce capacity, and a special structure to support copper conductors so as to maintain the shape of copper conductors after removing the medium. The advantage of the present invention is that it can realize the complete air gap structure without short circuit or disconnection of copper conductors as well as the complete air gap structure with long conductors, thus reducing RC delay. | 07-25-2013 |
20130200856 | Device and Method for Battery Abnormality Processing - Embodiments in accordance with the present invention provide a battery abnormality processing device for processing abnormalities in a battery pack with multiple battery modules. The battery abnormality processing device includes a detecting unit coupled to the battery modules, a comparison unit coupled to the detecting unit and a processing unit coupled to the comparison unit. The detecting unit detects the temperature at each end of each battery module in the battery pack. The comparison unit determines the abnormalities in the battery pack based on the detected temperatures. The processing unit executes an abnormality handling process if an abnormality is determined. | 08-08-2013 |
20130237009 | METHOD FOR MANUFACTURING A GATE-CONTROL DIODE SEMICONDUCTOR DEVICE - The present invention belongs to the technical field of semiconductor device manufacturing, and specifically relates to a method for manufacturing a gate-control diode semiconductor device. The present invention manufactures gate-control diode semiconductor devices through a low-temperature process, features a simple process, low manufacturing cost, and capacity of manufacturing gate-control diode devices able to reduce the chip power consumption through advantages of high driving current and small sub-threshold swing. The method for manufacturing a gate-control diode semiconductor device proposed by the present invention is especially applicable to the manufacturing of reading & writing devices having flat panel displays and phase change memory, and semiconductor devices based on flexible substrates. | 09-12-2013 |
20130237010 | METHOD FOR MANUFACTURING A GATE-CONTROL DIODE SEMICONDUCTOR MEMORY DEVICE - The present invention belongs to the technical field of semiconductor device manufacturing, and specifically discloses a method for manufacturing a gate-control diode semiconductor storage device. The present invention manufactures gate-control diode semiconductor memory devices through a low-temperature process featuring a simple process, low manufacturing cost and capacity of manufacturing gate-control diode memory devices with a high driving current and small sub-threshold swing. The method for manufacturing a gate-control diode semiconductor memory device proposed by the present invention is especially applicable to the manufacturing of flat panel displays and phase change memories and memory devices based on flexible substrate. | 09-12-2013 |
20130245970 | Apparatus and Method for Detecting Battery Abnormality and Cause Thereof - Methods and apparatus for detecting abnormality of a battery pack are disclosed. The battery pack includes multiple battery cells coupled in series via at least one connecting wire. A first voltage drop between a positive electrode and a negative electrode of the battery pack is detected. A first set of voltage drops between a positive electrode and a negative electrode of each battery cell in the battery pack is also detected. A total voltage drop across the at least one connecting wire in the battery pack is calculated based on an absolute difference between the first voltage drop and a sum of the first set of voltage drops. Whether the battery pack is abnormal is determined by assessing the total voltage drop across the at least one connecting wire with respect to a predetermined threshold. | 09-19-2013 |
20130250856 | CARRIER BEARING METHOD AND DEVICE, AND RADIO REMOTE UNIT - The present disclosure discloses a carrier bearing method and device, and a base station. The carrier bearing method includes: obtaining transmit power of each carrier borne on all power amplifiers in a radio remote unit after detecting that transmit power of a carrier borne on a power amplifier in the radio remote unit changes; adjusting a correspondence between the carriers and the power amplifier in the radio remote unit according to the obtained transmit power; and bearing each carrier on its corresponding power amplifier according to the adjusted correspondence. The device and base station are used to implement the above method. | 09-26-2013 |
20130264632 | THIN FILM TRANSISTOR MEMORY AND ITS FABRICATING METHOD - The invention relates to a thin film transistor memory and its fabricating method, This memory using the substrate as the gate electrode from bottom to up includes a charge blocking layer, a charge storage layer, a charge tunneling layer, an active region of the device and source/drain electrodes. The charge blocking layer is the ALD grown Al | 10-10-2013 |
20130270615 | METHOD FOR MAKING TRANSISTORS - A method of making a transistor, comprising: providing a semiconductor substrate; forming a gate stack over the semiconductor substrate; forming an insulating layer over the semiconductor substrate; forming a depleting layer over the insulating layer; etching the depleting layer and the insulating layer; forming a metal layer over the semiconductor substrate; performing thermal annealing; and removing the metal layer. As advantages of the present invention, an upper outside part of each of the sidewalls include a material that can react with the metal layer, so that metal on two sides of the sidewalls is absorbed during the annealing process, preventing the metal from diffusing toward the semiconductor layer, and ensuring that the formed Schottky junctions can be ultra-thin and uniform, and have controllable and suppressed lateral growth. | 10-17-2013 |
20130295732 | METHOD FOR MAKING FIELD EFFECT TRANSISTOR - The present invention provides a method for making a field effect transistor, comprising of the following steps: providing a silicon substrate with a first type, forming a shallow trench by photolithography and etching processes, and forming silicon dioxide shallow trench isolations inside the shallow trench; forming by deposition a high-K gate dielectric layer and a metal gate electrode layer on the substrate and the shallow trench isolations; forming a gate structure by photolithography and etching processes; forming source/drain extension regions by ion implantation of dopants of a second type; depositing an insulating layer to form sidewalls tightly adhered to the sides of the gate; forming source/drain regions and PN junction interfaces between the source/drain region and the silicon substrate by ion implantation of dopants of the second type; and performing microwave annealing to activate implanted ions. The novel process of making a field effect transistor in the present invention can achieve impurity activation in the source/drain area at a low temperature and can reduce the influence of source/drain annealing on high-K gate dielectric and metal gate electrode. | 11-07-2013 |
20130324127 | METHOD AND BASE STATION FOR MANAGING CAPACITY OF A WIRELESS COMMUNICATION NETWORK - The present invention provides a method and a base station for managing capacity of a wireless communication network, which relates to the field of wireless communications and is capable of saving energy while adjusting capacity of a wireless communication network of a base station. The present invention includes: checking total traffic of all overlay networks belonging to the base station; if the checked total traffic keeps being lesser than a preset load threshold, searching for and determining a first overlay network; maintaining normal work of a power amplifier of at least one antenna in each group of antennas in the first overlay network and turning off power amplifiers of one or more other antennas; and connecting the one or more other antennas to the power amplifiers maintaining normal work in the groups in which the one or more other antennas are located. | 12-05-2013 |
20130341696 | METAL-OXIDE-SEMICONDUCTOR (MOS) TRANSISTOR STRUCTURE INTEGRATED WITH A RESISTANCE RANDOM ACCESS MEMORY (RRAM) AND THE MANUFACTURING METHODS THEREOF - The present invention belongs to the technical field of semiconductor memories, in particular to a metal oxide semiconductor (MOS) transistor structure integrated with a resistance random access memory (RRAM). The MOS transistor structure comprises a MOS transistor and a RRAM formed on a substrate, wherein a gate dielectric layer of said MOS transistor extends to the surface of a drain region of said MOS transistor; and the part of the gate dielectric layer on the surface of the drain region of said MOS transistor faults a resistance-variable storage layer of said RRAM. In this invention, the high-quality dielectric layer of the MOS transistor and the resistance-variable storage layer of the RRAM are obtained by primary atomic layer deposition which integrates the RRAM and MOS transistor together without increasing steps. This process is simple and can combine the shallow trench isolation or field oxygen isolation and ion implantation or diffusion of source electrode and drain electrode to make integration convenient. | 12-26-2013 |
20130341697 | TUNNEL TRANSISTOR STRUCTURE INTEGRATED WITH A RESISTANCE RANDOM ACCESS MEMORY (RRAM) AND A MANUFACTURING METHOD THEREOF - The invention relates to the technical field of semiconductor memories, in particular to a tunnel transistor structure integrated with a resistance random access memory and a manufacturing method thereof. The tunnel transistor structure in the present invention comprises a semiconductor substrate, and a tunnel transistor and a resistance random access memory formed on the semiconductor substrate, wherein the gate dielectric layer of the tunnel transistor extends to the surface of a drain region of the tunnel transistor; the part of the gate dielectric layer on the surface of the drain region of the tunnel transistor forms the resistance-variable storage layer of the resistance random access memory. In this invention, the high-quality gate dielectric layer of the tunnel transistor and the resistance-variable storage layer of the resistance random access memory are obtained by primary atomic layer deposition which integrates the resistance random access memory and tunnel transistor together without increasing steps. This process is simple and can combine the shallow trench isolation or field oxygen isolation and ion implantation or diffusion of source electrode and drain electrode to make integration convenient. | 12-26-2013 |
20140001837 | Dual Core DC/DC Module for Electrical Vehicle | 01-02-2014 |
20140003122 | SEMICONDUCTOR MEMORY STRUCTURE AND CONTROL METHOD THEREOF | 01-02-2014 |
20140004806 | SYSTEM AND METHOD FOR WIRELESS COMMUNICATIONS | 01-02-2014 |
20140034891 | SEMICONDUCTOR MEMORY STRUCTURE AND ITS MANUFACTURING METHOD THEREOF - The present invention belongs to the technical field of microelectronic devices, specifically relates to a semiconductor memory structure and its manufacturing method thereof. The semiconductor memory structure which carries out erasing, writing and reading operation on the phase change memory or the resistance change memory through a tunneling field-effect transistor is formed, for one hand, the high current passed through the tunneling field-effect transistor when the p-n junction the biased positively, meeting the high current requirements for erasing of and writing of the phase change memory and the resistance change memory, and on the other hand, Vertical structure of the field-effect transistor can greatly improve the density of memory devices arrays. The present invention also discloses a method, which is very suitable for the memory chips, for the manufacturing of the semiconductor memory structure using self-aligned process. | 02-06-2014 |
20140034955 | Nano-MOS Devices and Method of Making - The present invention discloses a method of making nano-MOS devices having a metal gate, thereby avoiding the poly depletion effect, and enhancing the MOS device's performance. The method forms metal gates by depositing a metal film over sidewall surfaces on two sides of a polycrystalline semiconductor layer. The metal in the metal film diffuses toward the sidewall surfaces of the polycrystalline semiconductor layer and forms, after annealing, metal-semiconductor compound nanowires (i.e., metal gates) on the sidewall surfaces of the polycrystalline semiconductor layer. Thus, high-resolution lithography is not required to form metal compound semiconductor nanowires, resulting in significant cost saving. At the same time, a nano-MOS device is also disclosed, which includes a metal gate, thereby avoiding the poly depletion effect, and resulting in enhanced MOS device performance. | 02-06-2014 |
20140034956 | Asymmetric Gate MOS Device and Method of Making - An asymetric gate MOS device is disclosed. The gate is a metal gate, and the metal gate has a different work function on the source side from that on the drain side of the MOS device, so that the overall performance parameters of the MOS device are more optimized. A method of making an asymetric gate MOS device is also disclosed. In the method, dopant ions are implanted into the gate of the MOS device, so as to cause the gate to have a different work function on the source side from that on the drain side of the MOS device. As a result, the overall performance parameters of the MOS device are more optimized. The method can be easily implemented. | 02-06-2014 |
20140037629 | HUMANIZED SINGLE-CHAIN ANTIBODY AGAINST BETA 3 INTEGRIN FOR THE TREATMENT AND PREVENTION OF METASTASIS - The present invention relates to methods inhibiting tumor metastasis and treating cancer in a subject that involve administering to the subject an antibody which recognizes GPIIIa49-66, under conditions effective to inhibit tumor metastasis and/or treat cancer in the subject. | 02-06-2014 |
20140048875 | Asymmetrical Gate MOS Device and Method of Making - An asymetric gate MOS device is disclosed. The gate is a metal gate, and the metal gate has a different work function on the source side from that on the drain side of the MOS device, so that the overall performance parameters of the MOS device are more optimized. A method of making an asymetric gate MOS device is also disclosed. In the method, dopant ions are implanted into the gate of the MOS device, so as to cause the gate to have a different work function on the source side from that on the drain side of the MOS device. As a result, the overall performance parameters of the MOS device are more optimized. The method can be easily implemented. | 02-20-2014 |
20140084472 | COMPOUND DIELECTRIC ANTI-COPPER-DIFFUSION BARRIER LAYER FOR COPPER CONNECTION AND MANUFACTURING METHOD THEREOF - The disclosure belongs to the field of manufacturing and interconnection of integrated circuits, and in particular relates to compound dielectric anti-copper-diffusion barrier layer for copper interconnection and a manufacturing method thereof The disclosure uses compound dielectric (oxide & metal) as the anti-copper-diffusion barrier layer. First, it can enhance the capable of metal for anti-copper-diffusion efficiently, and prevent the barrier layer for valid owing to oxidized and prolong the life of the barrier layer. Second, it can reduce the effective dielectric constant of the interconnection circuits and furthermore reduce the RC delay of the whole interconnection circuits. Besides, the alloy is firmly adhered to the copper, and the metal copper can be directly electroplated without growing a layer of seed crystal copper. The method is simple and feasible and is expected to be applied to manufacturing of the anti-copper-diffusion barrier layers for copper interconnections. | 03-27-2014 |
20140106759 | COMMUNICATIONS METHOD, DEVICE, AND SYSTEM - Embodiments of the present invention provide a communications method, device, and system. The method includes: monitoring whether a terminal on a macro network has a service requirement on a micro network, where the micro network is in the coverage area of the macro network, and all common physical channels or some common physical channels except a pilot channel on the micro network are in a disabled state; and if the terminal has a service requirement on the micro network, sending a network handover instruction that includes configuration information of the micro network to the terminal, where the network handover instruction is used to instruct the terminal to hand over from the macro network to the micro network. In the embodiments of the present invention, power consumption of a capacity station is reduced, and unnecessary power waste is reduced. | 04-17-2014 |
20140125395 | One-Wire Communication Circuit and One-Wire Communication Method - A communication circuit facilitating communication between a first equipment and a second equipment including a conversion circuit, an input port, an output port, and a communication port is disclosed. The conversion circuit converts an input signal to a first intermediate signal, and converts a second intermediate signal to an output signal. The input port inputs the input signal to the first conversion circuit. The output port outputs the output signal to the control unit. The communication port inputs the second intermediate signal to the conversion circuit, and outputs the first intermediate signal to the second equipment. A voltage of the first intermediate signal is determined based on a voltage of a power source if the first intermediate signal is logic high, and a voltage of the second intermediate signal is determined based on the voltage of the power source if the second intermediate signal is logic high. | 05-08-2014 |
20140159129 | NEAR-INFRARED-VISIBLE LIGHT ADJUSTABLE IMAGE SENSOR - The disclosure belongs to the field of semiconductor photoreceptors, in particular to a near-infrared-visible light adjustable image sensor. By adding a transfer transistor, the disclosure integrates a silicon-based photoelectric diode and a silicon germanium-based photoelectric diode on the same chip to realize that the silicon-based photoelectric diode and a silicon germanium-based photoelectric diode are controlled by the same readout circuit at different time, thus widening the spectrum response scope of the photoreceptor, realizing high integration and multifunction of the chip and reducing the manufacturing cost of the chip. The disclosure is applicable for intermediate and high-end products with low power consumption and photoreceptors for specific wave bands, in particular to military, communicative and other special fields. | 06-12-2014 |
20140167134 | SELF-ALIGNED VERTICAL NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - The present invention belongs to the technical field of semiconductor memory devices and specifically relates to a self-aligned vertical nonvolatile semiconductor memory device, Including: a semiconductor substrate, a drain region of a first doping type, two source regions of a second doping type, a stacked gate used to capture electrons; wherein the drain region, the two source regions and the stacked gate form two tunneling field effect transistors (TFETs) sharing one gate and one drain, the drain region current of each of the TFET is affected by the quantity and distribution of the charges in the stacked gate used to capture electrons, the drain is buried in the semiconductor substrate, the source regions above the drain region are separated from the drain through a channel and separated form each other through a region of the first doping type. The semiconductor memory device of the present invention features small unit area and simple manufacturing process. The memory chip using the present invention is of low manufacturing cost and high storage density. | 06-19-2014 |
20140221246 | HUMAN RARE BLOOD GROUP MULTIPLEX PCR DETECTION METHOD AND KIT - Disclosed are a human rare blood type detection method, a kit, a rapid screening method and applications thereof. By using multiple pairs of PCR specific primers directing to the SNP loci of multiple rare blood types, the SNP loci of multiple rare blood types are simultaneously detected in the same PCR reaction system; and the multiplex PCR detection method and a Pool detection method are combined to rapidly screen the human rare blood types. | 08-07-2014 |
20140252359 | Semiconductor Device and Method of Making - The present disclosure is related to semiconductor technologies and discloses a semiconductor device and its method of making. In the present disclosure, a transistor's source and drain are led out by forming vias or contact holes in an insulator layer covering the transistor and at metal silicide contact regions corresponding to the source and drain, and by filling the vias with metal-semiconductor compound. Because the metal-semiconductor compound has relatively low resistivity, the resistance of the material in the vias can be minimized. Also, because the material used to fill the vias and the material forming the source/drain contact regions are both metal-semiconductor compound, contact resistance between the material filling the vias and the source/drain contact regions can be minimized. Furthermore, because the material filling the vias is metal-semiconductor compound, the conducting material in the vias and dielectric material in the insulator layer can form good interface and have good adhesion properties, and the conducting material would not cause structural damage in the dielectric material. Thus, there is no need to form a barrier layer between the insulator layer and the material filling the vias. | 09-11-2014 |
20140284728 | Metal Silicide Thin Film, Ultra-Shallow Junctions, Semiconductor Device and Method of Making - A metal silicide thin film and ultra-shallow junctions and methods of making are disclosed. In the present disclosure, by using a metal and semiconductor dopant mixture as a target, a mixture film is formed on a semiconductor substrate using a physical vapor deposition (PVD) process. The mixture film is removed afterwards by wet etching, which is followed by annealing to form metal silicide thin film and ultra-shallow junctions. Because the metal and semiconductor dopant mixture is used as a target to deposit the mixture film, and the mixture film is removed by wet etching before annealing, self-limiting, ultra-thin, and uniform metal silicide film and ultra-shallow junctions are formed concurrently in semiconductor field-effect transistor fabrication processes, which are suitable for field-effect transistors at the 14 nm, 11 nm, or even further technology node. | 09-25-2014 |
20140306271 | Unltra-Shallow Junction Semiconductor Field-Effect Transistor and Method of Making - An ultra-shallow junction semiconductor field-effect transistor and its methods of making are disclosed. In the present disclosure, a mixture film is formed on a semiconductor substrate with a gate structure formed thereon using a physical vapor deposition (PVD) process, which employs a mixture of metal and semiconductor dopants as a target. The PVD process is followed by annealing, during which ultra-shallow junctions and ultra-thin metal silicide are formed. After removing the mixture film remaining on the semiconductor substrate, an ultra-shallow junction semiconductor field-effect transistor is formed. Because the mixture film comprises metal and semiconductor dopants, ultra-shallow junctions and ultra-thin metal silicide can be formed in a same annealing process. The ultra-shallow junction thus formed can be used in semiconductor field-effect transistors for the 14 nm, 11 nm, or even further technology node. | 10-16-2014 |
20140315366 | Semiconductor Device and Method of Making - The present disclosure is related to semiconductor technologies and discloses a semiconductor device and its method of making. In the present disclosure, a transistor's source and drain are led out by concurrently formed metal-semiconductor compound contact regions at the source and drain and metal-semiconductor compounds in vias formed at positions corresponding to the source and drain. Because the metal-semiconductor compound has relatively low resistivity, the resistance of the metal-semiconductor compounds in the vias can be minimized. Also, because the material used to fill the vias and the material forming the source/drain contact regions are both metal-semiconductor compound, contact resistance between the material filling the vias and the metal-semiconductor compound source/drain contact regions can be minimized. Furthermore, because the material filling the vias is metal-semiconductor compound, the conducting material in the vias and dielectric material in the insulator layer can form good interface and have good adhesion properties, and the conducting material would not cause structural damage in the dielectric material. Thus, there is no need to form a barrier layer between the insulator layer and the material filling the vias. | 10-23-2014 |
20140377892 | METHOD OF FORMING AN INTEGRATED INDUCTOR BY DRY ETCHING AND METAL FILLING - The present invention discloses an inductive element formed by through silicon via interconnections. The inductive element formed by means of the special through silicon via interconnection by using through silicon via technology features advantages such as high inductance and density. Moreover, the through silicon via interconnection integrated process forming the inductive element is compatible with the ordinary through silicon interconnection integrated process without any other steps, thus making the process simple and steady. The inductive element using the present invention is applicable to the through silicon via package manufacturing of various chips, especially the package manufacturing of power control chips and radio-frequency chips. | 12-25-2014 |
20150033104 | Smooth Navigation Between Content Oriented Pages - Smooth navigation can be provided when switching between content oriented pages by presenting an intermediate page while the requested page is being received and rendered. The intermediate page can be the current page but without navigational features. Alternatively, the intermediate page can be an advertisement provided by the source of the requested page. | 01-29-2015 |
20150061807 | Transformer - A transformer includes a magnetic core, a primary winding, and a plurality of secondary windings. The magnetic core has an axial and a radial direction. The primary winding includes a plurality of winding sections and at least one connecting section. The winding sections are arranged along the axial direction. The connecting section is connected between the two adjacent winding sections. Each of the winding sections includes a plurality of primary winding layers and pull-out portions. The primary winding layers surround the magnetic core and are arranged along the radial direction. One pull-out portion connects two primary winding layers adjacent to the pull-out portion. Part of normal projections of the primary winding layers on a surface of the magnetic core are located between normal projections of the pull-out portions on the surface of the magnetic core. The secondary windings surround the primary winding. | 03-05-2015 |
20150071267 | METHOD, DEVICE, AND SYSTEM FOR TRANSMITTING DATA BASED ON HARQ - Embodiments of the present invention provide a method, a device, and a system for transmitting data based on a hybrid automatic repeat request (HARQ). The method includes: adjusting, according to current physical resources, a channel quality indicator (CQI) fed back by a terminal to obtain an adjusted CQI and determining an initial transmit power corresponding to the adjusted CQI; calculating an optimum number N | 03-12-2015 |