Patent application number | Description | Published |
20090019309 | METHOD AND COMPUTER PROGRAM PRODUCT FOR DETERMINING A MINIMALLY DEGRADED CONFIGURATION WHEN FAILURES OCCUR ALONG CONNECTIONS - A minimally degraded configuration is determined when failing connections occur. Associative deconfigurations are determined from deconfiguring hardware items in a server system, associative groups are derived, and failed connections are determined. Failed connections are determined between two hardware items that are in the same associative group, and the two hardware items at both endpoints of the failed connection are deconfigured. Each associative group state is set to unknown, and the failed connections are counted where a single endpoint of the failed connection is within the associative group. The associative group state is set to deconfigured, if a member of the associative group was deconfigured. Counts of the associative groups that remain in the unknown state are analyzed, and the associative group with the smallest failed connection count is selected and set to a configured state. The other associative group at the other end is set to a deconfigured stated, and the hardware item in the other associative group is deconfigured. | 01-15-2009 |
20090300290 | Memory Metadata Used to Handle Memory Errors Without Process Termination - Embodiments of the invention provide an interrupt handler configured to distinguish between critical and non-critical unrecoverable memory errors, yielding different actions for each. Doing so may allow a system to recover from certain memory errors without having to terminate a running process. In addition, when an operating system critical task experiences an unrecoverable error, such a task may be acting on behalf of a non-critical process (e.g., when swapping out a virtual memory page). When this occurs, an interrupt handler may respond to a memory error with the same response that would result had the process itself performed the memory operation. Further, firmware may be configured to perform diagnostics to identify potential memory errors and alert the operating system before a memory region state change occurs, such that the memory error would become critical. | 12-03-2009 |
20090300425 | Resilience to Memory Errors with Firmware Assistance - Embodiments of the invention provide an interrupt handler configured to distinguish between critical and non-critical unrecoverable memory errors, yielding different actions for each. Doing so may allow a system to recover from certain memory errors without having to terminate a running process. In addition, when an operating system critical task experiences an unrecoverable error, such a task may be acting on behalf of a non-critical process (e.g., when swapping out a virtual memory page). When this occurs, an interrupt handler may respond to a memory error with the same response that would result had the process itself performed the memory operation. Further, firmware may be configured to perform diagnostics to identify potential memory errors and alert the operating system before a memory region state change occurs, such that the memory error would become critical. | 12-03-2009 |
20090300434 | Clearing Interrupts Raised While Performing Operating System Critical Tasks - Embodiments of the invention provide an interrupt handler configured to distinguish between critical and non-critical unrecoverable memory errors, yielding different actions for each. Doing so may allow a system to recover from certain memory errors without having to terminate a running process. In addition, when an operating system critical task experiences an unrecoverable error, such a task may be acting on behalf of a non-critical process (e.g., when swapping out a virtual memory page). When this occurs, an interrupt handler may respond to a memory error with the same response that would result had the process itself performed the memory operation. Further, firmware may be configured to perform diagnostics to identify potential memory errors and alert the operating system before a memory region state change occurs, such that the memory error would become critical. | 12-03-2009 |
20120266010 | CONVERSION OF TIMESTAMPS BETWEEN MULTIPLE ENTITIES WITHIN A COMPUTING SYSTEM - Method, apparatus and system are described for converting received timestamps to a time-recording standard recognized by the receiving computing system. Embodiments of the invention generally include receiving data from an external device that includes a timestamp. If the received data is the first communication from the external device, creating a time base used for converting subsequently received timestamps to a recognized standard. Moreover, the system updates the time base if a counter failure at the external device is detected. When the external device transmits subsequent data, the time base is added to the subsequently received timestamps to convert the subsequent timestamps to a time-recording standard recognized by the computing system. | 10-18-2012 |
20130080818 | CONVERSION OF TIMESTAMPS BETWEEN MULTIPLE ENTITIES WITHIN A COMPUTING SYSTEM - Method is described for converting received timestamps to a time-recording standard recognized by the receiving computing system. Embodiments of the invention generally include receiving data from an external device that includes a timestamp. If the received data is the first communication from the external device, creating a time base used for converting subsequently received timestamps to a recognized standard. Moreover, the system updates the time base if a counter failure at the external device is detected. When the external device transmits subsequent data, the time base is added to the subsequently received timestamps to convert the subsequent timestamps to a time-recording standard recognized by the computing system. | 03-28-2013 |
Patent application number | Description | Published |
20090188155 | Techniques for maintaining palatability of a bait material in a pest control device - A termite control bait container includes an upper end portion opposite a lower end portion. The bait container includes a chamber containing a termite bait. The lower end portion includes an air-trapping pocket below at least a portion of the bait to reduce intrusion of water through the lower end portion when installed in a selected orientation at least partially below ground. | 07-30-2009 |
20100043276 | Bait materials, pest monitoring devices and other pest control devices that include polyurethane foam - In one aspect of the application, a termite bait, monitoring device or other termite control device includes a plurality of cellulosic food material pieces palatable to termites embedded within a water resistant polyurethane foam matrix. In another aspect, a termite bait, monitoring device or other termite control device includes a plurality of cellulosic food material pieces palatable to termites embedded within a water-absorbent polyurethane foam matrix. In another aspect a termite bait, monitoring device or other termite control device includes at least one cellulosic food material piece encapsulated within a water resistant polyurethane foam coating. In another aspect of the application, a termite control device includes a container, a cellulosic food material within the container and a water resistant polyurethane foam positioned to separate the food material from its environment. In another aspect of the application, a termite bait container includes a chamber containing a cellulosic food material and at least one pocket containing a polyurethane foam barrier to reduce intrusion of water through the pocket to the food material. In still another aspect of the application, a termite control device includes a container, a cellulosic food material within the container and a water-absorbent polyurethane foam scaffold that operates to hold moisture in contact with food material. | 02-25-2010 |
20100123554 | High realibility pest detection - A pest detection device includes a housing with a sensor and one or more bait members. The sensor includes one or more of a chisel-shaped electrically conductive trace carried on a substrate, a low resistance electrically conductive ink defining an electrical pathway on a substrate with a pointed profile, and/or a substrate including a directional grain structure oriented in a predefined manner relative to an electrically conductive pathway. | 05-20-2010 |
20120055076 | SYSTEMS AND METHODS FOR PEST CONTROL - Systems and methods for controlling one or more types of pests include the use of one or more freestanding pesticidal baits positioned at a location below and/or adjacent to one or more foundation elements of a building structure. In one form, the pesticidal baits are formed by a compressed mixture of a pesticide and a bait material that is palatable to one or more types of pests. In another form however, the pesticidal baits are formed by an extruded mixture of a pesticide and a bait material that is palatable to one or more types of pests. In a further aspect of these forms, the bait material is palatable to one or more wood-destroying pest species such as termites. However, other embodiments, forms and applications are also envisioned. | 03-08-2012 |
20120126951 | HIGH RELIABILITY PEST DETECTION - A pest detection device includes a housing with a sensor and one or more bait members. The sensor includes one or more of a chisel-shaped electrically conductive trace carried on a substrate, a low resistance electrically conductive ink defining an electrical pathway on a substrate with a pointed profile, and/or a substrate including a directional grain structure oriented in a predefined manner relative to an electrically conductive pathway. | 05-24-2012 |
20120210629 | TECHNIQUES FOR MAINTAINING PALATABILITY OF A BAIT MATERIAL IN A PEST CONTROL DEVICE - A termite control bait container includes an upper end portion opposite a lower end portion. The bait container includes a chamber containing a termite bait. The lower end portion includes an air-trapping pocket below at least a portion of the bait to reduce intrusion of water through the lower end portion when installed in a selected orientation at least partially below ground. | 08-23-2012 |
20130276352 | BAIT MATERIALS, PEST MONITORING DEVICES AND OTHER PEST CONTROL DEVICES THAT INCLUDE POLYURETHANE FOAM - A termite bait includes a plurality of cellulosic food material pieces palatable to termites embedded within a water resistant polyurethane foam matrix. Another termite bait includes a plurality of cellulosic food material pieces embedded within a water-absorbent polyurethane foam matrix. Yet another termite bait includes at least one cellulosic food material piece encapsulated within a water resistant polyurethane foam coating. Such termite baits can be used alone or in a monitoring device or other termite control device. Another termite control device includes a container, a cellulosic food material within the container and a water resistant polyurethane foam positioned to separate the food material from its environment. The container can contain a termite bait as described above or can include a chamber containing a cellulosic food material and at least one pocket containing a polyurethane foam barrier to reduce intrusion of water through the pocket to the food material. | 10-24-2013 |
20130276354 | BAIT MATERIALS, PEST MONITORING DEVICES AND OTHER PEST CONTROL DEVICES THAT INCLUDE POLYURETHANE FOAM - A termite bait includes a plurality of cellulosic food material pieces palatable to termites embedded within a water resistant polyurethane foam matrix. Another termite bait includes a plurality of cellulosic food material pieces embedded within a water-absorbent polyurethane foam matrix. Yet another termite bait includes at least one cellulosic food material piece encapsulated within a water resistant polyurethane foam coating. Such termite baits can be used alone or in a monitoring device or other termite control device. Another termite control device includes a container, a cellulosic food material within the container and a water resistant polyurethane foam positioned to separate the food material from its environment. The container can contain a termite bait as described above or can include a chamber containing a cellulosic food material and at least one pocket containing a polyurethane foam barrier to reduce intrusion of water through the pocket to the food material. | 10-24-2013 |
20130287830 | PESTICIDE COMPOSITION DELIVERY VEHICLES - Vehicles for delivery and release of pesticide compositions are provided. In one aspect, the delivery vehicle is a capsule configured to resist release of a pesticide composition before application of the capsule at a locus where pest control is desired. The capsule is further configured to degrade following application at the locus where pest control is desired to facilitate release of the pesticide composition. In one particular but non-limiting form, the capsule includes a shell wall including a relatively high Bloom strength gelatin material and a plasticizer material, and the pesticide composition includes a fumigant such as 1,3-dichloropropene. Further embodiments, forms, objects, features, advantages, aspects, and benefits shall become apparent from the description and drawings. | 10-31-2013 |
20150305325 | METHOD OF MAKING A COMPOSITE MATERIAL INCLUDING A THERMOPLASTIC POLYMER, A PEST FOOD MATERIAL AND A PESTICIDE - Composite materials that are palatable to a wood-destroying pest species and also pesticidal to the pest species can be used in pest control devices and can be used as wood substitutes for structural components, which are resistant to destruction by wood-destroying pests. The composite materials include a thermoplastic polymer, a food material for the pest and a pesticide. The composite material is formed by mixing a thermoplastic polymer, wood fragments or other cellulosic materials and a quantity of pesticide, and thereafter creating a molten material within a mixer, compounder, extruder or the like. The molten material is extruded or molded to form the desired shape. | 10-29-2015 |
20150305326 | COMPOSITE MATERIAL INCLUDING A THERMOPLASTIC POLYMER, A PEST FOOD MATERIAL AND A PESTICIDE - Composite materials that are palatable to a wood-destroying pest species and also pesticidal to the pest species can be used in pest control devices and can be used as wood substitutes for structural components, which are resistant to destruction by wood-destroying pests. The composite materials include a thermoplastic polymer, a food material for the pest and a pesticide. The composite material is formed by mixing a thermoplastic polymer, wood fragments or other cellulosic materials and a quantity of pesticide, and thereafter creating a molten material within a mixer, compounder, extruder or the like. The molten material is extruded or molded to form the desired shape. | 10-29-2015 |
Patent application number | Description | Published |
20130254485 | COORDINATED PREFETCHING IN HIERARCHICALLY CACHED PROCESSORS - Processors and methods for coordinating prefetch units at multiple cache levels. A single, unified training mechanism is utilized for training on streams generated by a processor core. Prefetch requests are sent from the core to lower level caches, and a packet is sent with each prefetch request. The packet identifies the stream ID of the prefetch request and includes relevant training information for the particular stream ID. The lower level caches generate prefetch requests based on the received training information. | 09-26-2013 |
20130275720 | ZERO CYCLE MOVE - A system and method for reducing the latency of data move operations. A register rename unit within a processor determines whether a decoded move instruction is eligible for a zero cycle move operation. If so, control logic assigns a physical register identifier associated with a source operand of the move instruction to the destination operand of the move instruction. Additionally, the register rename unit marks the given move instruction to prevent it from proceeding in the processor pipeline. Further maintenance of the particular physical register identifier may be done by the register rename unit during commit of the given move instruction. | 10-17-2013 |
20130290680 | OPTIMIZING REGISTER INITIALIZATION OPERATIONS - A system and method for efficiently reducing the latency of initializing registers. A register rename unit within a processor determines whether prior to an execution pipeline stage it is known a decoded given instruction writes a particular numerical value in a destination operand. An example is a move immediate instruction that writes a value of 0 in its destination operand. Other examples may also qualify. If the determination is made, a given physical register identifier is assigned to the destination operand, wherein the given physical register identifier is associated with the particular numerical value, but it is not associated with an actual physical register in a physical register file. The given instruction is marked to prevent it from proceeding to an execution pipeline stage. When the given physical register identifier is used to read the physical register file, no actual physical register is accessed. | 10-31-2013 |
20130290681 | REGISTER FILE POWER SAVINGS - A system and method for efficiently reducing the power consumption of register file accesses. A processor is operable to execute instructions with two or more data types, each with an associated size and alignment. Data operands for a first data type use operand sizes equal to an entire width of a physical register within a physical register file. Data operands for a second data type use operand sizes less than an entire width of a physical register. Accesses of the physical register file for operands associated with a non-full-width data type do not access a full width of the physical registers. A given numerical value may be bypassed for the portion of the physical register that is not accessed. | 10-31-2013 |
20130298127 | LOAD-STORE DEPENDENCY PREDICTOR CONTENT MANAGEMENT - Methods and apparatuses for managing load-store dependencies in an out-of-order processor. A load store dependency predictor may include a table for storing entries for load-store pairs that have been found to be dependent and execute out of order. Each entry in the table includes a counter to indicate a strength of the dependency prediction. If the counter is above a threshold, a dependency is enforced for the load-store pair. If the counter is below the threshold, the dependency is not enforced for the load-store pair. When a store is dispatched, the table is searched, and any matching entries in the table are armed. If a load is dispatched, matches on an armed entry, and the counter is above the threshold, then the load will wait to issue until the corresponding store issues. | 11-07-2013 |
20130326198 | LOAD-STORE DEPENDENCY PREDICTOR PC HASHING - Methods and processors for managing load-store dependencies in an out-of-order instruction pipeline. A load store dependency predictor includes a table for storing entries for load-store pairs that have been found to be dependent and execute out of order. Each entry in the table includes hashed values to identify load and store operations. When a load or store operation is detected, the PC and an architectural register number are used to create a hashed value that can be used to uniquely identify the operation. Then, the load store dependency predictor table is searched for any matching entries with the same hashed value. | 12-05-2013 |
20130339671 | ZERO CYCLE LOAD - A system and method for reducing the latency of load operations. A register rename unit within a processor determines whether a decoded load instruction is eligible for conversion to a zero-cycle load operation. If so, control logic assigns a physical register identifier associated with a source operand of an older dependent store instruction to the destination operand of the load instruction. Additionally, the register rename unit marks the load instruction to prevent it from reading data associated with the source operand of the store instruction from memory. Due to the duplicate renaming, this data may be forwarded from a physical register file to instructions that are younger and dependent on the load instruction. | 12-19-2013 |
20140025892 | CONVERTING MEMORY ACCESSES NEAR BARRIERS INTO PREFETCHES - Methods, apparatuses, and processors for reducing memory latency in the presence of barriers. When a barrier operation is executed, subsequent memory access operations are delayed until the barrier operation retires. While the memory access operation is delayed, the memory access operation is converted into a prefetch request and sent to the L2 cache. Then, data corresponding to the prefetch request is retrieved and stored in the L1 data cache. When the memory access operation wakes up, the data for the operation will already be stored in the L1 data cache, reducing the memory latency of the operation. | 01-23-2014 |
20140089589 | BARRIER COLORS - Methods and processors for enforcing an order of memory access requests in the presence of barriers in an out-of-order processor pipeline. A speculative color is assigned to instruction operations in the front-end of the processor pipeline, while the instruction operations are still in order. The instruction operations are placed in any of multiple reservation stations and then issued out-of-order from the reservation stations. When a barrier is encountered in the front-end, the speculative color is changed, and instruction operations are assigned the new speculative color. A core interface unit maintains an architectural color, and the architectural color is changed when a barrier retires. The core interface unit stalls instruction operations with a speculative color that does match the architectural color. | 03-27-2014 |
20140089617 | Trust Zone Support in System on a Chip Having Security Enclave Processor - An SOC implements a security enclave processor (SEP). The SEP may include a processor and one or more security peripherals. The SEP may be isolated from the rest of the SOC (e.g. one or more central processing units (CPUs) in the SOC, or application processors (APs) in the SOC). Access to the SEP may be strictly controlled by hardware. For example, a mechanism in which the CPUs/APs can only access a mailbox location in the SEP is described. The CPU/AP may write a message to the mailbox, which the SEP may read and respond to. The SEP may include one or more of the following in some embodiments: secure key management using wrapping keys, SEP control of boot and/or power management, and separate trust zones in memory. | 03-27-2014 |
20140089638 | Multi-Destination Instruction Handling - Various techniques for processing instructions that specify multiple destinations. A first portion of a processor pipeline is configured to split a multi-destination instruction into a plurality of single-destination operations. A second portion of the pipeline is configured to process the plurality of single-destination operations. A third portion of the pipeline is configured to merge the plurality of single-destination operations into one or more multi-destination operations. The one or more multi-destination operations may be performed. The first portion of the pipeline may include a decode unit. The second portion of the pipeline may include a map unit, which may in turn include circuitry configured to maintain a list of free architectural registers and a mapping table that maps physical registers to architectural registers. The third portion of the pipeline may comprise a dispatch unit. In some embodiments, this may provide certain advantages such as reduced area and/or power consumption. | 03-27-2014 |
20140089647 | Branch Predictor for Wide Issue, Arbitrarily Aligned Fetch - In an embodiment, a processor may be configured to fetch N instruction bytes from an instruction cache (a “fetch group”), even if the fetch group crosses a cache line boundary. A branch predictor may be configured to produce branch predictions for up to M branches in the fetch group, where M is a maximum number of branches that may be included in the fetch group. In an embodiment, a branch direction predictor may be updated responsive to a misprediction and also responsive to the branch prediction being within a threshold of transitioning between predictions. To avoid a lookup to determine if the threshold update is to be performed, the branch predictor may detect the threshold update during prediction, and may transmit an indication with the branch. | 03-27-2014 |
20140181403 | CACHE POLICIES FOR UNCACHEABLE MEMORY REQUESTS - Systems, processors, and methods for keeping uncacheable data coherent. A processor includes a multi-level cache hierarchy, and uncacheable load memory operations can be cached at any level of the cache hierarchy. If an uncacheable load misses in the L2 cache, then allocation of the uncacheable load will be restricted to a subset of the ways of the L2 cache. If an uncacheable store memory operation hits in the L1 cache, then the hit cache line can be updated with the data from the memory operation. If the uncacheable store misses in the L1 cache, then the uncacheable store is sent to a core interface unit. | 06-26-2014 |
20140195737 | Flush Engine - Techniques are disclosed related to flushing one or more data caches. In one embodiment an apparatus includes a processing element, a first cache associated with the processing element, and a circuit configured to copy modified data from the first cache to a second cache in response to determining an activity level of the processing element. In this embodiment, the apparatus is configured to alter a power state of the first cache after the circuit copies the modified data. The first cache may be at a lower level in a memory hierarchy relative to the second cache. In one embodiment, the circuit is also configured to copy data from the second cache to a third cache or a memory after a particular time interval. In some embodiments, the circuit is configured to copy data while one or more pipeline elements of the apparatus are in a low-power state. | 07-10-2014 |
20140195789 | Usefulness Indication For Indirect Branch Prediction Training - A circuit for implementing a branch target buffer. The branch target buffer may include a memory that stores a plurality of entries. Each entry may include a tag value, a target value, and a prediction accuracy value. A received index value corresponding to an indirect branch instruction may be used to select one of entries of the plurality of entries, and a received tag value may then be compared to the tag value of the selected entries in the memory. An entry in the memory may be selected in response to a determination that the received tag does not match the tag value of compared entries. The selected entry may be allocated to the indirect instruction branch dependent upon the prediction accuracy values of the plurality of entries. | 07-10-2014 |
20140215182 | Persistent Relocatable Reset Vector for Processor - In an embodiment, an integrated circuit includes at least one processor. The processor may include a reset vector base address register configured to store a reset vector address for the processor. Responsive to a reset, the processor may be configured to capture a reset vector address on an input, updating the reset vector base address register. Upon release from reset, the processor may initiate instruction execution at the reset vector address. The integrated circuit may further include a logic circuit that is coupled to provide the reset vector address. The logic circuit may include a register that is programmable with the reset vector address. More particularly, in an embodiment, the register may be programmable via a write operation issued by the processor (e.g. a memory-mapped write operation). Accordingly, the reset vector address may be programmable in the integrated circuit, and may be changed from time to time. | 07-31-2014 |
20140215188 | Multi-Level Dispatch for a Superscalar Processor - In an embodiment, a processor includes a multi-level dispatch circuit configured to supply operations for execution by multiple parallel execution pipelines. The multi-level dispatch circuit may include multiple dispatch buffers, each of which is coupled to multiple reservation stations. Each reservation station may be coupled to a respective execution pipeline and may be configured to schedule instruction operations (ops) for execution in the respective execution pipeline. The sets of reservation stations coupled to each dispatch buffer may be non-overlapping. Thus, if a given op is to be executed in a given execution pipeline, the op may be sent to the dispatch buffer which is coupled to the reservation station that provides ops to the given execution pipeline. | 07-31-2014 |
20140244976 | IT INSTRUCTION PRE-DECODE - Various techniques for processing and pre-decoding branches within an IT instruction block. Instructions are fetched and cached in an instruction cache, and pre-decode bits are generated to indicate the presence of an IT instruction and the likely boundaries of the IT instruction block. If an unconditional branch is detected within the likely boundaries of an IT instruction block, the unconditional branch is treated as if it were a conditional branch. The unconditional branch is sent to the branch direction predictor and the predictor generates a branch direction prediction for the unconditional branch. | 08-28-2014 |
20140317358 | GLOBAL MAINTENANCE COMMAND PROTOCOL IN A CACHE COHERENT SYSTEM - A system may include a command queue controller coupled to a number of clusters of cores, where each cluster includes a cache shared amongst the cores. An originating core of one of the clusters may detect a global maintenance command and send the global maintenance command to the command queue controller. The command queue controller may broadcast the global maintenance command to the clusters including the originating core's cluster. Each of the cores of the clusters may execute the global maintenance command. Each cluster may send an acknowledgement to the command queue controller upon completed execution of the global maintenance command by each core of the cluster. The command queue controller may also send, upon receiving an acknowledgement from each cluster, a final acknowledgement to the originating core's cluster. | 10-23-2014 |
20140317425 | MULTI-CORE PROCESSOR INSTRUCTION THROTTLING - An apparatus for performing instruction throttling for a multi-processor system is disclosed. The apparatus may include a power estimation circuit, a table, a comparator, and a finite state machine. The power estimation circuit may be configured to receive information on high power instructions issued to a first processor and a second processor, and generate a power estimate dependent upon the received information. The table may be configured to store one or more pre-determined power threshold values, and the comparator may be configured to compare the power estimate with at least one of the pre-determined power threshold values. The finite state machine may be configured to adjust the throttle level of the first and second processors dependent upon the result of the comparison. | 10-23-2014 |
20150026404 | Least Recently Used Mechanism for Cache Line Eviction from a Cache Memory - A mechanism for evicting a cache line from a cache memory includes first selecting for eviction a least recently used cache line of a group of invalid cache lines. If all cache lines are valid, selecting for eviction a least recently used cache line of a group of cache lines in which no cache line of the group of cache lines is also stored within a higher level cache memory such as the L1 cache, for example. Lastly, if all cache lines are valid and there are no non-inclusive cache lines, selecting for eviction the least recently used cache line stored in the cache memory. | 01-22-2015 |
20150026413 | Access Map-Pattern Match Based Prefetch Unit for a Processor - In an embodiment, a processor may implement an access map-pattern match (AMPM)-based prefetcher in which patterns may include wild cards for some cache blocks. The wild card may match any access for the corresponding cache block (e.g. no access, demand access, prefetch, successful prefetch, etc.). Furthermore, patterns with irregular strides and/or irregular access patterns may be included in the matching patterns and may be detected for prefetch generation. In an embodiment, the AMPM prefetcher may implement a chained access map for large streaming prefetches. If a stream is detected, the AMPM prefetcher may allocate a pair of map entries for the stream and may reuse the pair for subsequent access map regions within the stream. In some embodiments, a quality factor may be associated with each access map and may control the rate of prefetch generation. | 01-22-2015 |
20150143044 | MECHANISM FOR SHARING PRIVATE CACHES IN A SOC - Systems, processors, and methods for sharing an agent's private cache with other agents within a SoC. Many agents in the SoC have a private cache in addition to the shared caches and memory of the SoC. If an agent's processor is shut down or operating at less than full capacity, the agent's private cache can be shared with other agents. When a requesting agent generates a memory request and the memory request misses in the memory cache, the memory cache can allocate the memory request in a separate agent's cache rather than allocating the memory request in the memory cache. | 05-21-2015 |
20160048395 | Branch Predictor for Wide Issue, Arbitrarily Aligned Fetch - In an embodiment, a processor may be configured to fetch N instruction bytes from an instruction cache (a “fetch group”), even if the fetch group crosses a cache line boundary. A branch predictor may be configured to produce branch predictions for up to M branches in the fetch group, where M is a maximum number of branches that may be included in the fetch group. In an embodiment, a branch direction predictor may be updated responsive to a misprediction and also responsive to the branch prediction being within a threshold of transitioning between predictions. To avoid a lookup to determine if the threshold update is to be performed, the branch predictor may detect the threshold update during prediction, and may transmit an indication with the branch. | 02-18-2016 |
20160055099 | Least Recently Used Mechanism for Cache Line Eviction from a Cache Memory - A mechanism for evicting a cache line from a cache memory includes first selecting for eviction a least recently used cache line of a group of invalid cache lines. If all cache lines are valid, selecting for eviction a least recently used cache line of a group of cache lines in which no cache line of the group of cache lines is also stored within a higher level cache memory such as the L1 cache, for example. Lastly, if all cache lines are valid and there are no non-inclusive cache lines, selecting for eviction the least recently used cache line stored in the cache memory. | 02-25-2016 |
Patent application number | Description | Published |
20110182946 | Formation of Nanostructured Particles of Poorly Water Soluble Drugs and Recovery by Mechanical Techniques - The present invention provides a composition and method of forming an amorphous drug-loaded particle by forming one or more amorphous drug-loaded nanoparticles comprising one or more active agents stabilized by one or more polymers, desolvating the one or more amorphous drug-loaded nanoparticles to form one or more flocculated amorphous drug-loaded nanoparticles, filtering the one or more flocculated amorphous drug-loaded nanoparticles and drying the one or more flocculated amorphous drug-loaded nanoparticles to form amorphous drug-loaded particles. | 07-28-2011 |
20110224232 | Treatment of Pulmonary Fungal Infection With Voriconazole via Inhalation - A method of treating fungal infection by pulmonary administration of a solution of voriconazole and cyclodextrin is provided The fungal infection can be a pulmonary infection. The solution can be an inhalable aqueous formulation that can be administered via the mouth or nose. The cyclodextrin can be a water soluble cyclodextrin derivative such as sulfoalkyl ether cyclodextrin. The formulation can be administered via a spray device or nebulizer. | 09-15-2011 |
20120251595 | EMULSION TEMPLATE METHOD TO FORM SMALL PARTICLES OF HYDROPHOBIC AGENTS WITH SURFACE ENRICHED HYDROPHILICITY BY ULTRA RAPID FREEZING - The present invention relates to methods and compositions to prepare small size particles of poorly water soluble agents or drugs with surface enriched hydrophilicity. | 10-04-2012 |
20130303630 | Thermo-Kinetic Mixing for Pharmaceutical Applications - Compositions and methods for making a pharmaceutical dosage form include making a pharmaceutical composition that includes one or more active pharmaceutical ingredients (API) with one or more pharmaceutically acceptable excipients by thermokinetic compounding into a composite. Compositions and methods of preprocessing a composite comprising one or more APIs with one or more excipients include thermokinetic compounding, comprising thermokinetic processing the APIs with the excipients into a composite, wherein the composite can be further processed by conventional methods known in the art, such as hot melt extrusion, melt granulation, compression molding, tablet compression, capsule filling, film-coating, or injection molding. | 11-14-2013 |
20140030340 | PREPARATION OF DRUG PARTICLES USING EVAPORATION PRECIPITATION INTO AQUEOUS SOLUTIONS - A method for preparing poorly water soluble drug particles is disclosed. The method comprises dissolving a drug in at least one organic solvent to form a drug/organic mixture, spraying the drug/organic mixture into an aqueous solution and concurrently evaporating the organic solvent in the presence of the aqueous solution to form an aqueous dispersion of the drug particles. The resulting drug particles are in the nanometer to micrometer size range and show enhanced dissolution rates and reduced crystallinity when compared to the unprocessed drug. The present invention additionally contemplates products and processes for new drug formulations of insoluble drug particles having high dissolution rates and extremely high drug-to-excipient ratios. | 01-30-2014 |
20140039031 | PHARMACEUTICAL FORMULATIONS OF ACETYL-11-KETO-B-BOSWELLIC ACID, DIINDOLYLMETHANE, AND CURCUMIN FOR PHARMACEUTICAL APPLICATIONS - The present disclosure is directed to compositions and methods for formulating a pharmaceutical dosage form by forming a composition comprising acetyl-11-keto-β-boswellic acid, diindolylmethane, or curcumin with one or more pharmaceutically acceptable excipients for enhanced solubility to increase bioavailability and improve therapeutic efficacy. The composition can be processed by thermo-kinetic compounding along with conventional methods known in the art, such as hot melt extrusion, melt granulation, compression molding, tablet compression, capsule filling, film-coating, or injection molding. | 02-06-2014 |
20150209289 | FORMATION OF STABLE SUBMICRON PEPTIDE OR PROTEIN PARTICLES BY THIN FILM FREEZING - The present invention includes compositions and methods for preparing micron-sized or submicron-sized particles by dissolving a water soluble effective ingredient in one or more solvents; spraying or dripping droplets solvent such that the effective ingredient is exposed to a vapor-liquid interface of less than 50, 100, 150, 200, 250, 200, 400 or 500 cm | 07-30-2015 |
20150224062 | ENHANCED DELIVERY OF IMMUNOSUPPRESSIVE DRUG COMPOSITIONS FOR PULMONARY DELIVERY - The present invention includes compositions and methods for making and using a rapid dissolving, high potency, substantially amorphous nanostructured aggregate for pulmonary delivery of tacrolimus and a stabilizer matrix comprising, optionally, a polymeric or non-polymeric surfactant, a polymeric or non-polymeric saccharide or both, wherein the aggregate comprises a surface area greater than 5 m | 08-13-2015 |
20150320740 | ENHANCED DELIVERY OF DRUG COMPOSITIONS TO TREAT LIFE THREATENING INFECTIONS - Inhalable compositions are described. The inhalable compositions comprise one or more respirable aggregates, the respirable aggregates comprising one or more poorly water soluble active agents, wherein at least one of the active agents reaches a maximum lung concentration (C | 11-12-2015 |