Patent application number | Description | Published |
20080216044 | METHOD, SYSTEM AND PROGRAM PRODUCT FOR SPECIFYING A CONFIGURATION FOR A DIGITAL SYSTEM UTILIZING DIAL BIASING WEIGHTS - In a method of data processing, a database defines a Dial entity and at least one instance of the Dial entity. Each instance of the Dial entity has an input having a plurality of different possible input values and one or more outputs, and each of the plurality of different possible input values has a different associated output value set for the one or more outputs. Each instance of the Dial entity determines a value of at least one of a plurality of configuration latches in a digital system separate from the database. The database also associates with the Dial entity at least one set of biasing weights that, when applied, determines a probability of each instance of the Dial entity having particular ones of the plurality of different possible input values. In response to a call to set the plurality of configuration latches, the database is accessed to apply the at least one set of biasing weights to select one of the plurality of different possible input values for the at least one instance of the Dial entity. The plurality of configuration latches in the digital system are set based upon the output value set for the one or more outputs of the at least one instance of the Dial entity. | 09-04-2008 |
20080229193 | PROGRAM PRODUCT SUPPORTING SPECIFICATION OF SIGNALS FOR SIMULATION RESULT VIEWING - According to a method of data processing, a data set including at least one entry specifying a signal group by a predetermined signal group name is received by a data processing system. In response to receipt of the data set, the entry in the data set is processed to identify the signal group name. Signal group information associated with an event trace file containing simulation results is accessed to determine signal names of multiple signals that are members of the signal group. Simulation results from the event trace file that are associated with instances of said multiple signals are then included within a presentation of simulation results. | 09-18-2008 |
20080235648 | PROGRAM PRODUCT PROVIDING A CONFIGURATION SPECIFICATION LANGUAGE SUPPORTING ARBITRARY MAPPING FUNCTIONS FOR CONFIGURATION CONSTRUCTS - A method is disclosed of associating a mapping function with a configuration construct of a digital design defined by one or more hardware description language (HDL) files. According to the method, in the HDL files, a configuration latch is specified within a design entity forming at least a portion of the digital design. In addition, a Dial is specified that defines a relationship between each of a plurality of input values and a respective one of a plurality of different output values. The HDL files also include a statement that instantiates an instance of the Dial in association with the configuration latch such that a one-to-one correspondence exists between a value contained within the configuration latch and an input value of the instance of the Dial. The HDL files further include a statement associating the Dial with a mapping function that applies a selected transformation to values read from or written to the instance of the Dial. | 09-25-2008 |
20080249758 | PROGRAM PRODUCT FOR DEFINING AND RECORDING MINIMUM AND MAXIMUM EVENT COUNTS OF A SIMULATION UTILIZING A HIGH LEVEL LANGUAGE - According to one method of simulation processing, instrumentation code, such as an runtime executive (rtx), receives one or more statements describing an count event and identifying the count event as an outlying count event. While simulating a design utilizing the HDL simulation model, occurrences of the outlying count event are counted to obtain a count event value. Simulation result data obtained from simulating the design is then received and processed. In the processing, the count event value is recorded within a data storage subsystem responsive to a determination of whether or not the count event value of the outlying count event exceeds a previously recorded count event value. | 10-09-2008 |
20080255821 | CONTROLLING OPERATION OF A DIGITAL SYSTEM UTILIZING REGISTER ENTITIES - In at least one hardware definition language (HDL) file, at least one design entity containing a functional portion of a digital system is specified. The design entity logically contains first and second latches each having a respective plurality of different possible latch values. With one or more statements, a first Dial instance is associated with the first latch and a second Dial instance is associated with the second latch. A setting of the first Dial instance thus controls which of the plurality of different possible values is loaded in the first latch, and a setting of the second Dial instance controls which of the plurality of different possible values is loaded in the second latch. With a statement, a Register instance is concurrently associated with both the first and the second latches, such that a setting of the Register instance controls the latch values loaded in both the first and second latches. | 10-16-2008 |
20080256135 | PROGRAM PRODUCT FOR PROVIDING A CONFIGURATION SPECIFICATION LANGUAGE SUPPORTING INCOMPLETELY SPECIFIED CONFIGURATION ENTITIES - In a hardware definition language (HDL) file among one or more files, one or more design entities containing a functional portion of a digital system are specified. The one or more design entities logically contain a plurality of latches having a respective plurality of different possible latch values that each corresponds to a different configuration of the functional portion of the digital system. With one or more statements in the one or more files, a multi-level Dial tree is defined that includes a selective control Dial (SCDial) entity at an upper level that is associated with at least one design entity. The SCDial entity has a Dial input, a plurality of Dial outputs coupled to inputs of the plurality of lower level Dials, and a mapping table indicating a mapping between each of a plurality of possible input values of the Dial input and a respective one of a plurality of sets of output values for the plurality of Dial outputs. At least one set of output values in the mapping table specifies output values for fewer than all of the plurality of Dial outputs. Each specified output value reflects a setting of at least one lower level Dial, and settings of the lower level Dials reflect which of the plurality of different possible configuration values is loaded in the plurality of configuration latches. | 10-16-2008 |
20080281571 | METHOD, SYSTEM AND PROGRAM PRODUCT SUPPORTING SEQUENTIAL LOGIC IN SIMULATION INSTRUMENTATION OF AN ELECTRONIC SYSTEM - According to a method of simulation processing, a collection of files including one or more HDL source files describing design entities collectively representing a digital design to be simulated is received. The HDL source file(s) include a statement specifying inclusion of an instrumentation entity not forming a portion of the digital design but enabling observation of its operation during simulation. The instrumentation entity includes sequential logic containing at least one storage element, where the instrumentation entity has an output signal indicative of occurrence of a simulation event. The collection of files is processed to obtain an instrumented simulation executable model. The processing includes instantiating at least one instance of each of the plurality of design entities and instantiating the instrumentation entity. The processing further includes instantiating external instrumentation logic, logically coupled to each instance of the instrumentation entity, to record occurrences of the event. | 11-13-2008 |
20080288234 | METHOD, SYSTEM AND PROGRAM PRODUCT SUPPORTING USER TRACING IN A SIMULATOR - According to a method of specifying a trace array for simulation of a digital design, one or more entities within a simulation model are specified with one or more statements in one or more hardware description language (HDL) files. In addition, a trace array for storing data generated through simulation of the simulation model is specified in one or more statements in the one or more HDL files. The HDL files may subsequently be processed to create a simulation model containing at least one design entity and a trace array within the design entity for storing trace data regarding specified signals of interest. | 11-20-2008 |
20080294413 | PROGRAM PRODUCT SUPPORTING PHASE EVENTS IN A SIMULATION MODEL OF A DIGITAL SYSTEM - According to a method of simulation processing, an instrumented simulation executable model of a design is built by compiling one or more hardware description language (HDL) files specifying one or more design entities within the design and one or more instrumentation entities and instantiating instances of the one or more instrumentation entities within instances of the one or more design entities. Operation of the design is then simulated utilizing the instrumented simulation executable model. Simulating operation includes each of multiple instantiations of the one or more instrumentation entities generating a respective external phase signal representing an occurrence of a particular phase of operation and instrumentation combining logic generating from external phase signals of the multiple instantiations of the one or more instrumentation entities an aggregate phase signal representing an occurrence of the particular phase. | 11-27-2008 |
20080295073 | PROGRAM PRODUCT PROVIDING A CONFIGURATION SPECIFICATION LANGUAGE HAVING CLONE LATCH SUPPORT - Methods, data processing systems, and program products supporting the insertion of clone latches within a digital design are disclosed. According to one method, a parent latch within the digital design is specified in an HDL statement in one of the HDL files representing a digital design. In addition, a clone latch is specified within the digital design utilizing an HDL clone latch declaration. An HDL attribute-value pair is associated with the HDL clone latch declaration to indicate a relationship between the clone latch and the parent latch according to which the clone latch is automatically set to a same value as the parent latch when the parent latch is set. Thereafter, when a configuration compiler receives one or more design intermediate files containing the clone latch declaration, the configuration compiler creates at least one data structure in a configuration database representing the clone latch and the relationship between the clone latch and the parent latch. | 11-27-2008 |
20080301603 | CLOCK-GATED MODEL TRANSFORMATION FOR ASYNCHRONOUS TESTING OF LOGIC TARGETED FOR FREE-RUNNING, DATA-GATED LOGIC - Asynchronous behavior of a circuit is modeled by modifying latches in a netlist to add an extra port to the latches, e.g., a single-port latch is transformed into a dual-port latch. Each input port has an enable line and a data input. The data input in the added port is a feedback line from the latch output, and the enable line in the added port is the logical NOR of all of the original enable lines. By adding this extra latch port in the higher-level model, it becomes possible to introduce assertion logic to ensure that one and only one latch port for a given latch is ever active during the same simulation cycle. The model can then be tested earlier in the design methodology prior to the availability of the post-synthesis netlist. The model can also be used in both simulation and formal or semi-formal verification. | 12-04-2008 |
20090192778 | TRACKING CONVERGE RESULTS IN A BATCH SIMULATION FARM NETWORK - A method and system for providing centralized access to count event information from testing of a hardware simulation model within a batch simulation farm which includes simulation clients and an instrumentation server. Count event data for said hardware simulation model is received by the instrumentation server from one or more simulation clients. A first and a second counter report are generated for the hardware simulation model, in which the first and second counter reports are derived from the count event data received by the instrumentation server. The first counter report is compared to the second counter report, and responsive to this comparison, a counter difference report is generated within the instrumentation server that conveys count event trends associated with the simulation model under different simulation testcases. | 07-30-2009 |
20090193390 | TECHNIQUES FOR MODELING VARIABLES IN SUBPROGRAMS OF HARDWARE DESCRIPTION LANGUAGE PROGRAMS - A method, system and computer program product for modeling variables in subprograms of a HDL program. A subprogram is provided with an initial value of a variable of an element being modeled and the subprogram is stored in memory of a data processing system. In response to a subprogram call, a copy of the stored subprogram is provided to the requesting HDL program. During execution, the initial value of the variable in the provided copy of the subprogram may be modified by the HDL program, but the value retains unchanged in the stored subprogram. | 07-30-2009 |
20100153083 | SELECTIVE COMPILATION OF A SIMULATION MODEL IN VIEW OF UNAVAILABLE HIGHER LEVEL SIGNALS - In response to receiving HDL file(s) that specify a plurality of hierarchically arranged design entities defining a design to be simulated and that specify an instrumentation entity for monitoring simulated operation of the design, an instrumented simulation executable model of the design is built. Building the model includes compiling the HDL file(s) specifying the plurality of hierarchically arranged design entities defining the design and instantiating at least one instance of each of the plurality of hierarchically arranged design entities, and further includes instantiating an instance of the instrumentation entity within an instance of a particular design entity among the plurality of design entities and, based upon a reference in an instrumentation statement in the one or more HDL files, logically attaching an input of the instance of the instrumentation entity to an input source within the design that is outside the scope of the particular design entity. | 06-17-2010 |
20100153898 | MODEL BUILD IN THE PRESENCE OF A NON-BINDING REFERENCE - One or more hardware description language (HDL) files describe a plurality of hierarchically arranged design entities defining a digital design to be simulated and a plurality of configuration entities not belonging to the digital design that logically control settings of a plurality of configuration latches in the digital design. The HDL file(s) are compiled to obtain a simulation executable model of the digital design and an associated configuration database. The compiling includes parsing a configuration statement that specifies an association between an instance of a configuration entity and a specified configuration latch, determining whether or not the specified configuration latch is described in the HDL file(s), and if not, creating an indication in the configuration database that the instance of the configuration latch had a specified association to a configuration latch to which it failed to bind. | 06-17-2010 |