Patent application number | Description | Published |
20090312338 | Novel Tricyclic Compounds - The invention provides a compound of Formula (I) | 12-17-2009 |
20110190489 | Novel Tricyclic Compounds - The invention provides a compound of Formula (Ia), (Ib), (Ic), (Id), (Ie), (If), (Ig), (Ih), (Ii), (Ij), (Ik), or (Il) as defined herein, pharmaceutically acceptable salts, pro-drugs, biologically active metabolites, stereoisomers and isomers thereof wherein the variable are defined herein. The compounds of the invention are useful for treating immunological and oncological conditions. | 08-04-2011 |
20110207704 | Novel Oxadiazole Compounds - Novel oxadiazole compounds, pharmaceutical compositions containing such compounds and the use of those compounds or compositions as agonists or antagonists of the S1P family of G protein-coupled receptors for treating diseases associated with modulation of S1P family receptor activity, in particular by affording a beneficial immunosuppressive effect are disclosed. | 08-25-2011 |
20110311474 | Novel Tricyclic Compounds - The invention provides compounds of Formula (I) and Formula (II) | 12-22-2011 |
20120015963 | NOVEL PYRAZOLO[3,4-d]PYRIMIDINE COMPOUNDS - The present disclosure is directed to novel compounds of Formula (I) | 01-19-2012 |
Patent application number | Description | Published |
20100317568 | Anti-Viral Compounds - Compounds effective in inhibiting replication of Hepatitis C virus (“HCV”) are described. This invention also relates to processes of making such compounds, compositions comprising such compounds, and methods of using such compounds to treat HCV infection. | 12-16-2010 |
20110092415 | Anti-Viral Compounds - Compounds effective in inhibiting replication of Hepatitis C virus (“HCV”) are described. This invention also relates to processes of making such compounds, compositions comprising such compounds, and methods of using such compounds to treat HCV infection. | 04-21-2011 |
20110207699 | Anti-Viral Compounds - Compounds effective in inhibiting replication of Hepatitis C virus (“HCV”) are described. This invention also relates to processes of making such compounds, compositions comprising such compounds, and methods of using such compounds to treat HCV infection. | 08-25-2011 |
20120004196 | Anti-Viral Compounds - Compounds effective in inhibiting replication of Hepatitis C virus (“HCV”) are described. This invention also relates to processes of making such compounds, compositions comprising such compounds, and methods of using such compounds to treat HCV infection. | 01-05-2012 |
20120122842 | NAMPT AND ROCK INHIBITORS - Disclosed are compounds which inhibit the activity of NAMPT, compositions containing the compounds and methods of treating diseases during which NAMPT is expressed. Disclosed are compounds which inhibit the activity of ROCK, compositions containing the compounds and methods of treating diseases during which ROCK is expressed. | 05-17-2012 |
20120220562 | Anti-Viral Compounds - Compounds effective in inhibiting replication of Hepatitis C virus (“HCV”) are described. This invention also relates to processes of making such compounds, compositions comprising such compounds, and methods of using such compounds to treat HCV infection. | 08-30-2012 |
20120245124 | TRPV3 Modulators - Disclosed herein are modulators of TRPV3 of formula (I) | 09-27-2012 |
20130085141 | SUBSTITUTED OCTAHYDROPYRROLO[1,2-a]PYRAZINE SULFONAMIDES AS CALCIUM CHANNEL BLOCKERS - The present application relates to: (a) compounds of Formula (I): | 04-04-2013 |
20130085142 | SUBSTITUTED OCTAHYDROPYRROLO[1,2-a]PYRAZINES AS CALCIUM CHANNEL BLOCKERS - The present application relates to: (a) compounds of Formula (I): | 04-04-2013 |
20130158067 | TRPV1 Antagonists - Disclosed herein are compounds of formula (I): | 06-20-2013 |
20130172334 | TRPV1 ANTAGONISTS - Disclosed herein are compounds of formula (I): | 07-04-2013 |
20130216497 | NOVEL TRICYCLIC COMPOUNDS - The invention provides compounds of Formula (I) and Formula (II) | 08-22-2013 |
20130345255 | TRPV1 ANTAGONISTS - Disclosed herein are compounds of formula (I) or pharmaceutically acceptable salts, prodrugs, or combinations thereof, | 12-26-2013 |
20140256705 | BROMODOMAIN INHIBITORS - The present invention provides for compounds of formula (I) | 09-11-2014 |
20140315792 | ANTI-VIRAL COMPOUNDS - Compounds effective in inhibiting replication of Hepatitis C virus (“HCV”) are described. This invention also relates to processes of making such compounds, compositions comprising such compounds, and methods of using such compounds to treat HCV infection. | 10-23-2014 |
20140349970 | NOVEL TRICYCLIC COMPOUNDS - The invention provides a compound of Formula (Ia), (Ib), (Ic), (Id), (Ie), (If), (Ig), (Ih), (Ii), (Ij), (Ik), or (Il) as defined herein, pharmaceutically acceptable salts, pro-drugs, biologically active metabolites, stereoisomers and isomers thereof wherein the variable are defined herein. The compounds of the invention are useful for treating immunological and oncological conditions. | 11-27-2014 |
20150087618 | Anti-Viral Compounds - Compounds effective in inhibiting replication of Hepatitis C virus (“HCV”) are described. This invention also relates to processes of making such compounds, compositions comprising such compounds, and methods of using such compounds to treat HCV infection. | 03-26-2015 |
Patent application number | Description | Published |
20110161619 | SYSTEMS AND METHODS IMPLEMENTING NON-SHARED PAGE TABLES FOR SHARING MEMORY RESOURCES MANAGED BY A MAIN OPERATING SYSTEM WITH ACCELERATOR DEVICES - Systems and methods are provided that utilize non-shared page tables to allow an accelerator device to share physical memory of a computer system that is managed by and operates under control of an operating system. The computer system can include a multi-core central processor unit. The accelerator device can be, for example, an isolated core processor device of the multi-core central processor unit that is sequestered for use independently of the operating system, or an external device that is communicatively coupled to the computer system. | 06-30-2011 |
20110161620 | SYSTEMS AND METHODS IMPLEMENTING SHARED PAGE TABLES FOR SHARING MEMORY RESOURCES MANAGED BY A MAIN OPERATING SYSTEM WITH ACCELERATOR DEVICES - Systems and methods are provided that utilize shared page tables to allow an accelerator device to share physical memory of a computer system that is managed by and operates under control of an operating system. The computer system can include a multi-core central processor unit. The accelerator device can be, for example, an isolated core processor device of the multi-core central processor unit that is sequestered for use independently of the operating system, or an external device that is communicatively coupled to the computer system. | 06-30-2011 |
20120188259 | Mechanisms for Enabling Task Scheduling - Embodiments described herein provide a method including receiving a command to schedule a first process and selecting a command queue associated with the first process. The method also includes scheduling the first process to run on an accelerated processing device and preempting a second process running on the accelerated processing device to allow the first process to run on the accelerated processing device. | 07-26-2012 |
20120198458 | Methods and Systems for Synchronous Operation of a Processing Device - Embodiments of the present invention provide a method of synchronous operation of a first processing device and a second processing device. The method includes executing a process on the first processing device, responsive to a determination that execution of the process on the first device has reached a serial-parallel boundary, passing an execution thread of the process from the first processing device to the second processing device, and executing the process on the second processing device. | 08-02-2012 |
20120200576 | Preemptive context switching of processes on ac accelerated processing device (APD) based on time quanta - Methods, systems, and computer readable media for preemptive context-switching of processes on an accelerated processing device are based upon a comparison of the running time of the process and a threshold time quanta. A method includes preempting a process running on an accelerated processing device based upon a running time of the process and a threshold time quanta. | 08-09-2012 |
20130135327 | Saving and Restoring Non-Shader State Using a Command Processor - Provided is a system including a command processor configured for interrupting processing of a first set of instructions executing within a shader core. | 05-30-2013 |
20130141447 | Method and Apparatus for Accommodating Multiple, Concurrent Work Inputs - A method of accommodating more than one compute input is provided. The method creates an APD arbitration policy that dynamically assigns compute instructions from a sequence of instructions awaiting processing to the APD compute units for execution of a run list. | 06-06-2013 |
20130147816 | Partitioning Resources of a Processor - Embodiments describe herein provide an apparatus, a computer readable medium and a method for simultaneously processing tasks within an APD. The method includes processing a first task within an APD. The method also includes reducing utilization of the APD by the first task to facilitate simultaneous processing of the second task, such that the utilization remains below a threshold. | 06-13-2013 |
20130155077 | Policies for Shader Resource Allocation in a Shader Core - A method of determining priority within an accelerated processing device is provided. The accelerated processing device includes compute pipeline queues that are processed in accordance with predetermined criteria. The queues are selected based on priority characteristics and the selected queue is processed until a time quantum lapses or a queue having a higher priority becomes available for processing. | 06-20-2013 |
Patent application number | Description | Published |
20110161955 | HYPERVISOR ISOLATION OF PROCESSOR CORES - Techniques for utilizing processor cores include sequestering processor cores for use independently from an operating system. In at least one embodiment of the invention, a method includes executing an operating system on a first subset of cores including one or more cores of a plurality of cores of a computer system. The operating system executes as a guest under control of a virtual machine monitor. The method includes executing work for an application on a second subset of cores including one or more cores of the plurality of cores. The first and second subsets of cores are mutually exclusive and the second subset of cores is not visible to the operating system. In at least one embodiment, the method includes sequestering the second subset of cores from the operating system. | 06-30-2011 |
20120194524 | Preemptive Context Switching - Methods, systems, and computer readable media embodiments are disclosed for preemptive context-switching of processes running on a accelerated processing device. Embodiments include, detecting by an accelerated processing device a memory exception, and preempting a process from running on the accelerated processing device based upon the detected exception. | 08-02-2012 |
20120194525 | Managed Task Scheduling on a Graphics Processing Device (APD) - Provided herein is a method including receiving a run list including one or more processes to run on an accelerated processing device, wherein each of the one or more processes is associated with a corresponding independent job command queue. The method also includes scheduling each of the one or more processes to run on the accelerated processing device based on a criteria associated with each process. | 08-02-2012 |
20120194527 | Method for Preempting Graphics Tasks to Accommodate Compute Tasks in an Accelerated Processing Device (APD) - Embodiments described herein provide a method of arbitrating a processing resource. The method includes receiving a command to preempt a task and preventing additional wavefronts associated with the task from being processed. The method also includes evicting currently executing wavefronts associated with the task from being processed based upon predetermined criteria | 08-02-2012 |
20120194528 | Method and System for Context Switching - Embodiments of the present invention provide a method of preempting a task. The method includes removing the task from the parallel processors via a scheduling mechanism. Responsive to the removing, the method also includes ceasing (i) retrieval of commands from a buffer associated with the task, (ii) dispatch of groups of work-items associated with the task, (iii) dispatch of wavefronts associated with the task, and (iiii) execution of the wavefronts. State information related to the task is saved. | 08-02-2012 |
20120200579 | Process Device Context Switching - Methods, systems, and computer readable media embodiments are disclosed for preemptive context-switching of processes running on an accelerated processing device. A method includes, responsive to an exception upon access to a memory by a process running on a accelerated processing device, whether to preempt the process based on the exception, and preempting, based upon the determining, the process from running on the accelerated processing device. | 08-09-2012 |
20130141446 | Method and Apparatus for Servicing Page Fault Exceptions - A method, apparatus and computer readable media for servicing page fault exceptions in a accelerated processing device (APD). A page fault related to a wavefront is detected. A fault handling request to a translation mechanism is sent when the page fault is detected. A fault handling response corresponding to the detected page fault from the translation mechanism is received. Confirmation that the detected page fault has been handled through performing page mapping based on the fault handling response is received. | 06-06-2013 |
20130145202 | Handling Virtual-to-Physical Address Translation Failures - A method tolerates virtual to physical address translation failures. A translation request is sent from a graphics processing device to a translation mechanism. The translation request is associated with a first wavefront. A fault notification is received within an accelerated processing device (APD) from the translation mechanism that a request cannot be acknowledged. The first wavefront is, stored within a shader core of the APD if the fault notification is received. The first wavefront is replaced with a second wavefront if the fault notification is received, the second wavefront being ready to be executed. | 06-06-2013 |
20130155079 | Saving and Restoring Shader Context State - Provided is a method for processing a command in a computing system including an accelerated processing device (APD) having a command processor. The method includes executing an interrupt routine to save one or more contexts related to a first set of instructions on a shader core in response to an instruction to preempt processing of the first set of instructions. | 06-20-2013 |
20130160019 | Method for Resuming an APD Wavefront in Which a Subset of Elements Have Faulted - A method resumes an accelerated processing device (APD) wavefront in which a subset of elements have faulted. A restore command for a job including a wavefront is received. A list of context states for the wavefront is read from a memory associated with a APD. An empty shell wavefront is created for restoring the list of context states. A portion of not acknowledged data is masked over a portion of acknowledged data within the restored wavefronts. | 06-20-2013 |
20140181461 | REPORTING ACCESS AND DIRTY PAGES - A method and apparatus for reporting events into at least one event log are presented. An “access” event entry may be added to an event log stored in memory when a peripheral device accesses an address of a memory page described by a page table entry (PTE). A “dirty” event entry may be added to an event log stored in memory when a page writes to a memory page. The event log may reside in an input/output memory management unit (IOMMU) that includes a translation lookaside buffer (TLB). The IOMMU may report the event log entries to system memory. When there is no entry in the TLB and a direct memory access (DMA) read operation enters the IOMMU, a PTE may be loaded into the TLB after updating an access log to calculate an address. If the DMA operation is not a read operation, both dirty and access logs may be updated. | 06-26-2014 |
20140344489 | VARIABLE-SIZED BUFFERS MAPPED TO HARDWARE REGISTERS - An interface includes a first hardware register field to store respective chunks of a command directed to a device and respective chunks of a response to the command from the device. The interface also includes a second hardware register field to store a size of the command and a size of the response. The first and second hardware register fields are accessible by the device and by a processor external to the device that generates the command, in response to memory not being available to buffer the command and the response. | 11-20-2014 |
Patent application number | Description | Published |
20130159664 | Infrastructure Support for Accelerated Processing Device Memory Paging Without Operating System Integration - In a CPU of the combined CPU/APD architecture system, the CPU having multiple CPU cores, each core having a first machine specific register for receiving a physical page table/page directory base address, a second machine specific register for receiving a physical address pointing to a location controlled by an IOMMUv2 that is communicatively coupled to an APD, and microcode which when executed causes a write notification to be issued to the physical address contained in the second machine specific register; receiving in the first machine specific register of a CPU core, a physical page table/page directory base address, receiving in the second machine specific register of the CPU core, a physical address pointing to a location controlled by the IOMMUv2, determining that a control register of the CPU core has been updated, and responsive to the determination that the control register has been updated, executing microcode in the CPU core that causes a write notification to be issued to the physical address contained in the second machine specific register, wherein the physical address is able to receive writes that affect IOMMUv2 page table invalidations. | 06-20-2013 |
20130160017 | Software Mechanisms for Managing Task Scheduling on an Accelerated Processing Device (APD) - Embodiments describe herein provide a method of for managing task scheduling on a accelerated processing device. The method includes executing a first task within the accelerated processing device (APD), monitoring for an interruption of the execution of the first task, and switching to a second task when an interruption is detected. | 06-20-2013 |