Patent application number | Description | Published |
20120025327 | SEMICONDUCTOR DEVICE WITH METAL GATES AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a gate insulation layer formed over a substrate and having a high dielectric constant, a gate electrode formed over the gate insulation layer and a work function control layer formed between the substrate and the gate insulation layer and inducing a work function shift of the gate electrode. | 02-02-2012 |
20120153406 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming a gate dielectric layer over a substrate, forming a dipole capping layer over the gate dielectric layer, stacking a metal gate layer and a polysilicon layer over the dipole capping layer, and forming a gate pattern by etching the polysilicon layer, the metal gate layer, the dipole capping layer, and the gate dielectric layer. | 06-21-2012 |
20120273921 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a dielectric layer, where the dielectric layer includes a metal oxide layer, a metal nitride carbide layer including hydrogen therein, and a reduction prevention layer inserted between the metal nitride carbide layer and the dielectric layer. | 11-01-2012 |
20130069166 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate including a first region and a second region, a gate dielectric layer formed on the substrate, and a metal electrode layer formed on the gate dielectric layer and including a compound of carbon and nitrogen, wherein a metal electrode formed from the metal electrode layer in the first region has a work function lower than a work function of a metal electrode formed from the metal electrode layer in the second region and a nitrogen concentration of the metal electrode of the first region is smaller than a nitrogen concentration of the metal electrode of the second region. | 03-21-2013 |
20130105901 | SEMICONDUCTOR DEVICE WITH METAL GATE ELECTRODE AND HIGH-K DIELECTRIC MATERIAL AND METHOD FOR FABRICATING THE SAME | 05-02-2013 |
20130161710 | SEMICONDUCTOR DEVICE HAVING BURIED BIT LINE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes: forming an insulation layer over a semiconductor substrate; forming a first conductive layer over the insulation layer; forming a plurality of buried bit lines and insulation layer patterns isolated by a plurality of trenches, wherein the plurality of trenches are formed by etching the first conductive layer and the insulation layer; forming a sacrificial layer to gap-fill the trenches; forming a second conductive layer over the buried bit lines and the sacrificial layer; and forming a plurality of pillars over each of the buried bit lines by etching the second conductive layer. | 06-27-2013 |
20130171797 | METHOD FOR FORMING MULTI-COMPONENT LAYER, METHOD FOR FORMING MULTI-COMPONENT DIELECTRIC LAYER AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method of forming a multi-component dielectric layer on the surface of a substrate by atomic layer deposition includes injecting a cocktail source of a plurality of sources at least having a cyclopentadienyl ligand, wherein the cocktail source is adsorbed on a surface of a substrate by injecting the cocktail source, performing a first purge process to remove a non-adsorbed portion of the cocktail source, injecting a reactant to react with the adsorbed cocktail source, wherein a multi-component layer is formed by the reaction between the reactant and the absorbed cocktail source, and performing a second purge process to remove reaction byproducts and an unreacted portion of the reactant. | 07-04-2013 |
20130244394 | METHOD FOR FABRICATING CAPACITOR WITH HIGH ASPECT RATIO - A method for fabricating a capacitor includes: forming a first silicon layer over a semiconductor substrate, where the first silicon layer is doped with a dopant; forming an undoped second silicon layer over the first silicon layer; forming an opening by etching the second silicon layer and the first silicon layer; forming a storage node in the opening; and removing the first silicon layer and the second silicon layer. | 09-19-2013 |
20130277636 | VARIABLE RESISTANCE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a variable resistance memory device includes forming a first electrode, forming a first metal oxide layer which satisfies chemical stoichiometry over the first electrode, forming a second metal oxide layer which is lower in oxygen content than the first metal oxide layer by reducing a part of the first metal oxide layer, and forming a second electrode over the second metal oxide layer. | 10-24-2013 |
20140162448 | SEMICONDUCTOR DEVICE WITH METAL GATES AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a gate insulation layer formed over a substrate and having a high dielectric constant, a gate electrode formed over the gate insulation layer and a work function control layer formed between the substrate and the gate insulation layer and inducing a work function shift of the gate electrode. | 06-12-2014 |
20150028424 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate including a first region and a second region, a gate dielectric layer formed on the substrate, and a metal electrode layer formed on the gate dielectric layer and including a compound of carbon and nitrogen, wherein a metal electrode formed from the metal electrode layer in the first region has a work function lower than a work function of a metal electrode formed from the metal electrode layer in the second region and a nitrogen concentration of the metal electrode of the first region is smaller than a nitrogen concentration of the metal electrode of the second region. | 01-29-2015 |