Patent application number | Description | Published |
20140379978 | REFRESH SCHEME FOR MEMORY CELLS WITH WEAK RETENTION TIME - A memory refresh method within a memory controller includes checking a first retention state corresponding to a first memory address and a second retention state corresponding to a second memory address. The memory refresh method also includes performing a refresh operation on a row corresponding to the second memory address when the second retention state indicates a weak retention state. The first memory address corresponds to a refresh counter address, and the second memory address corresponds to a complementary address of the refresh counter address. | 12-25-2014 |
20150016203 | DRAM SUB-ARRAY LEVEL AUTONOMIC REFRESH MEMORY CONTROLLER OPTIMIZATION - A method of refreshing a dynamic random access memory (DRAM) includes detecting an open page of the DRAM at a row of a DRAM bank within an open sub-array of the DRAM bank. The method also includes delaying issuance of a refresh command to a target refresh row of the DRAM bank when the target refresh row of the DRAM bank is within the open sub-array of the DRAM bank. | 01-15-2015 |
20150016204 | INSERTION-OVERRIDE COUNTER TO SUPPORT MULTIPLE MEMORY REFRESH RATES - A memory refresh method includes determining positions at which to insert refresh operations of weak rows of a memory block among regularly scheduled refresh operations of normal rows of the memory block. The refresh operations occur at a substantially constant refresh rate. The positions at which to insert are based on an actual weak page address. The method also includes performing inserted refresh operations at the determined positions to coordinate distribution of the inserted refresh operations among the regularly scheduled refresh operations. | 01-15-2015 |
20150085594 | METHOD AND APPARATUS FOR REFRESHING A MEMORY CELL - Memory devices may send information related to refresh rates to a memory controller. The memory controller may instruct the memory devices to refresh based on the received information. | 03-26-2015 |
20150092479 | RESISTANCE-BASED MEMORY CELLS WITH MULTIPLE SOURCE LINES - In a particular embodiment, a device includes a resistance-based memory cell having multiple source lines and multiple access transistors. A coupling configuration of the multiple access transistors to multiple source lines encodes a data value. | 04-02-2015 |
20150121006 | SPLIT WRITE OPERATION FOR RESISTIVE MEMORY CACHE - A method of reading from and writing to a resistive memory cache includes receiving a write command and dividing the write command into multiple write sub-commands. The method also includes receiving a read command and executing the read command before executing a next write sub-command. | 04-30-2015 |
20150134897 | METHOD AND APPARATUS FOR REFRESHING A MEMORY CELL - A method includes sending a first signal from a memory device to a memory controller. The first signal indicates to the memory controller that particular memory cells of the memory device are to be refreshed by the memory device. | 05-14-2015 |
20150149865 | CACHE STRUCTURE WITH PARITY-PROTECTED CLEAN DATA AND ECC-PROTECTED DIRTY DATA - A method includes generating error detection information associated with data to be stored at a cache in response to determining that the data is clean. The method also includes storing the clean data at a first region of the cache. The method further includes generating error correction information associated with data to be stored at the cache in response to determining that the data is dirty. The method also includes storing the dirty data at a second region of the cache. | 05-28-2015 |