Patent application number | Description | Published |
20110292754 | MEMORY WORD-LINE DRIVER HAVING REDUCED POWER CONSUMPTION - A word-line driving circuit for driving a word-line in a memory array includes a NAND circuit having a pair of address inputs and an output, an output inverter circuit having an inverter power supply node, an input coupled to the output of the NAND circuit and an output for providing a word line signal, a power gate coupled between a first power supply node and the inverter power supply node, and a control circuit coupled to the power gate. The control circuit controls the power gate to place the word line driver circuit in active or standby mode in response to the output of the NAND circuit. | 12-01-2011 |
20120110530 | COMPUTER SYSTEM AND METHOD OF PREPARING A LAYOUT - The present application discloses a method of preparing a layout for manufacturing an integrated circuit chip according to a circuit design. In at least one embodiment, a pattern for the layout based on the circuit design is generated. After the generation of the pattern, it is determined if at least one layout rule is violated in the layout, the at least one layout rule being specified according to a predetermined maximum value for at least one of an estimated voltage drop along a signal path in the layout or an estimated current density on the signal path. If the at least one layout rule is violated, a violation is indicated. | 05-03-2012 |
20120236675 | Methods and Apparatus for Memory Word Line Driver - A word line driver circuit and corresponding methods are disclosed. An apparatus, comprising a decoder circuit coupled to receive address inputs, and having a decoder output; and a word line clock gating circuit coupled to the decoder output and to a word line clock signal, configured to selectively output a word line signal responsive to an edge on the word line clock signal; wherein the address inputs have a set up time requirement relative to the edge of the word line clock signal, and the address inputs have a zero or less hold time requirement relative to the edge of the word line clock signal. Methods for providing a word line signal from a word line driver are disclosed. | 09-20-2012 |
20130094308 | NEGATIVE WORD LINE DRIVER FOR SEMICONDUCTOR MEMORIES - A semiconductor memory includes a word line driver and a negative voltage generator. The word line driver includes a first inverter configured to drive a word line at one of a first voltage supplied by a first voltage source and a second voltage supplied by a second voltage source. The negative voltage generator is configured to provide a negative voltage with respect to the second voltage to an input of the first inverter in response to a control signal for performing at least one of a read or a write operation of a memory bit cell coupled to the word line. | 04-18-2013 |
20130329505 | Far End Resistance Tracking Design with Near End Pre-Charge Control for Faster Recovery Time - A wordline tracking circuit and corresponding method are disclosed, and include a tracking wordline having an impedance characteristic associated therewith that models a row of memory cells in a memory device, wherein the tracking wordline row has a near end that receives a wordline pulse signal having a near end rising pulse edge and a near end falling pulse edge. The tracking wordline also has a far end. A tracking cell component is coupled to the far end of the tracking wordline that receives the wordline pulse signal. Lastly, the circuit includes a tracking bitline pre-charge circuit coupled to the tracking cell that is configured to pre-charge a tracking bitline associated with the tracking cell using the near end wordline pulse signal. | 12-12-2013 |
20140092695 | HEADER CIRCUIT FOR CONTROLLING SUPPLY VOLTAGE OF A CELL - One or more techniques or systems for controlling a supply voltage of a cell are provided herein. Additionally, one or more techniques or systems for mitigating leakage of the cell are provided. In some embodiments, a header circuit is provided, including a first pull-up p-type metal-oxide-semiconductor (PMOS) transistor including a first gate, a first source, and a first drain. Additionally, the header circuit includes a second pull-down PMOS transistor including a second gate, a second source, and a second drain. In some embodiments, the first drain of the first pull-up PMOS transistor is connected to the second source of the second pull-down PMOS transistor and a supply voltage line for one or more cells. In this manner, a pull-down PMOS is configured to control the supply voltage of the cell, thus facilitating voltage control for a write assist, for example. | 04-03-2014 |
20140269115 | Integrated Write Mux and Driver Systems and Methods - An integrated driver system is disclosed. The driver system includes decoding logic and a driver portion. The decoding logic is configured to receive select signals and data signals. The driver portion is configured to generate driver signals according to the decoded signals. | 09-18-2014 |
20140269141 | WORDLINE DOUBLER - A memory includes a clock generator for providing a first clock signal responsive to a second clock signal and a feedback signal. A feedback loop provides the feedback signal and includes a tracking wordline, a tracking bitline, a tracking bit cell, and a tracking wordline driver for driving the tracking wordline responsive to the first clock signal. The memory includes a tracking wordline level tuner for reducing a voltage level of a tracking wordline signal on the tracking wordline responsive to a weak bit control signal. | 09-18-2014 |
20140307502 | Far End Resistance Tracking Design with Near End Pre-Charge Control for Faster Recovery Time - A wordline tracking circuit and corresponding method are disclosed, and include a tracking wordline having an impedance characteristic associated therewith that models a row of memory cells in a memory device, wherein the tracking wordline row has a near end that receives a wordline pulse signal having a near end rising pulse edge and a near end falling pulse edge. The tracking wordline also has a far end. A tracking cell component is coupled to the far end of the tracking wordline that receives the wordline pulse signal. Lastly, the circuit includes a tracking bitline pre-charge circuit coupled to the tracking cell that is configured to pre-charge a tracking bitline associated with the tracking cell using the near end wordline pulse signal. | 10-16-2014 |
20150161325 | METHOD OF PREPARING A LAYOUT AND SYSTEM FOR PERFORMING THE SAME - A method of preparing a layout for manufacturing an integrated circuit chip according to a circuit design, the method includes generating a pattern for the layout based on the circuit design, determining, by a processor, if at least one layout rule is violated by including the generated pattern in the layout and modifying the layout if the at least one layout rule is violated. The at least one layout rule includes a constraint on a relationship between a power line pattern and a device pattern in the layout. The at least one layout rule is specified by comparing a predetermined threshold value with one of an estimated voltage drop along a signal path in a second layout different than the layout or an estimated current density on the signal path in the second layout. The constraint includes a minimum number of contacts per device or power vias per device. | 06-11-2015 |
20150277770 | MEMORY DEVICE WITH TRACKING MECHANISM - A memory device includes storage layers each comprising memory cells arranged in a plurality of rows, bit lines coupled to the memory cells in the corresponding rows, tracking cells arranged in at least one row, at least one tracking bit line coupled to the tracking cells, and at least one sense amplifier coupled to the bit lines. The sense amplifier is configured to detect data stored in the memory cells, and has an enabling terminal coupled to the at least one tracking bit line. The memory device further comprises word lines and tracking word lines extending through the storage layers. The word lines are coupled to the corresponding memory cells in the storage layers. The tracking word lines are coupled to the corresponding tracking cells in the storage layers. | 10-01-2015 |
20160111142 | MEMORY WITH BIT LINE CONTROL - A memory comprises a first set of memory cells coupled between a first data line and a second data line. The memory also includes a first input/output (I/O) circuit coupled to the first data line and the second data line. The first I/O circuit is also coupled to a first control line to receive a first control signal and coupled to a first select line to receive a first select signal. The first I/O circuit is configured to selectively decouple the first data line and the second data line from the first I/O circuit during a sleep mode based on the first control signal and the first select signal. | 04-21-2016 |
Patent application number | Description | Published |
20140167842 | POWER CIRCUIT AND METHOD THEREOF - A power circuit and a method thereof are provided. The method includes: determining, by a power controller, a first signal is to be transmitted in the continuous mode or the burst mode; when the first signal is to be transmitted in the continuous mode, activating, by a power controller, a continuous mode converter; when activated, converting, by the continuous mode converter, a first voltage down to a second voltage and supplying the second voltage to the first power amplifier; when the first signal is to be transmitted in the burst mode, activating, by a power controller, a burst mode converter; when activated and the first power amplifier is inactive, receiving, by a burst mode converter, a first current to accumulate a burst energy; and when activated and the first power amplifier is active, supplying, by the burst mode converter, the burst energy to the first power amplifier. | 06-19-2014 |
Patent application number | Description | Published |
20150102861 | SHORT CURRENT-FREE EFFECTIVE CAPACITANCE TEST CIRCUIT AND METHOD - A method of determining an effective capacitance of a ring oscillator free of short current. The method comprises determining a frequency of an oscillator signal communicated from a ring oscillator to an inverter via a first communication path. The first communication path has connectivity to a first voltage source, a ground path and the inverter. The first communication path is divided into a second communication path and a third communication path. The method further comprises determining a voltage line current. The method additionally comprises determining an effective capacitance of the ring oscillator based on a first voltage of the first voltage source, the voltage line current and the frequency of the oscillator signal communicated to the inverter along the third communication path. | 04-16-2015 |
20150177327 | In Situ on the Fly On-Chip Variation Measurement - A methodology and circuits for integrated circuit design are provided. A first electronic design file for an integrated circuit is provided. The first electronic design file for the integrated circuit has a timing measurement circuit thereon. Based on the first electronic design file, a number of integrated circuits are manufactured. These manufactured integrated circuits have respective timing measurement circuits arranged at predetermined locations thereon. The timing measurement circuits are used to measure a number of respective timing delay values, which are subject to manufacturing variation, on the integrated circuits. The measured timing delay values are used to set how an auto-place and route tool arranges blocks in a second electronic design file, which is routed after the timing delay values are measured, to account for any measured manufacturing variation. | 06-25-2015 |
20150370946 | METHOD OF DENSITY-CONTROLLED FLOORPLAN DESIGN FOR INTEGRATED CIRCUITS AND INTEGRATED CIRCUITS - A method of density-controlled floorplan design for integrated circuits having a plurality of blocks includes positioning decoupling capacitor (DCAP) cells at least partially around a pattern density sensitive block. The method also includes changing at least a portion of a pattern density insensitive block adjacent to the pattern density sensitive block according to at least one pattern density rule. | 12-24-2015 |
Patent application number | Description | Published |
20120293454 | METHOD OF IDENTIFYING PALM AREA FOR TOUCH PANEL AND METHOD FOR UPDATING THE IDENTIFIED PALM AREA - A method of identifying a palm area for a touch panel has steps of: receiving sensing frame information having multiple touching sensing points from the touch panel; selecting one of the touching sensing points; outwardly extending a distance from an outline of the selected touching sensing point to define a searching range; checking whether other touching sensing points are within the searching range; marking the touching sensing points in the searching range and expanding the searching range based on the currently marked touching sensing points; sequentially selecting and checking each touching sensing point if it is within the present searching range; and finally merging all the outlines of the marked touching sensing points to form a final outline as a palm area. Other unmarked touching sensing points are defined as touching reference points. | 11-22-2012 |
20140347316 | TOUCH DEVICE AND MEASURING VOLTAGE DYNAMIC ADJUSTMENT METHOD THEREOF - A touch device and a measuring voltage dynamic adjustment method thereof are provided. The touch device comprises a touch panel, a touch sensing circuit and a processing unit. The touch sensing circuit electrically connected to the touch panel is configured to provide a first measuring voltage to the touch panel and sense capacitance variation of the touch panel to generate a plurality of sensing signals. The processing unit electrically connected to the touch sensing circuit is configured to receive the sensing signals, determine whether a touch is caused by a stylus according to the sensing signals and if yes, enable the touch sensing circuit to provide a second measuring voltage to the touch panel. The second measuring voltage is larger than the first measuring voltage. | 11-27-2014 |
20160054831 | CAPACITIVE TOUCH DEVICE AND METHOD IDENTIFYING TOUCH OBJECT ON THE SAME - A capacitive touch device and a method identifying touch object on the touch device read sensing information of multiple traces of a touch panel corresponding to a touch object, in which the sensing information includes a sensing cluster corresponding to a portion on the touch panel touched by the touch object, identify a hover cluster of the sensing information corresponding to a portion adjacent to and surrounding the sensing cluster, determine if the hover cluster meets a first characteristic, and determine that the touch object is a specific touch object when the hover cluster meets the first characteristic. Given the foregoing device and method, a palm rejection operation can be more accurately performed and is also applicable to object detection at corners of the touch panel. | 02-25-2016 |
20160110017 | METHOD OF IDENTIFYING PALM AREA OF A TOUCH PANEL AND A UPDATING METHOD THEREOF - A method of identifying a palm area for a touch panel has steps of: receiving sensing frame information having multiple touching sensing points from the touch panel; selecting one of the touching sensing points; outwardly extending a distance from an outline of the selected touching sensing point to define a searching range; checking whether other touching sensing points are within the searching range; marking the touching sensing points in the searching range and expanding the searching range based on the currently marked touching sensing points; sequentially selecting and checking each touching sensing point if it is within the present searching range; and finally merging all the outlines of the marked touching sensing points to form a final outline as a palm area. Other unmarked touching sensing points are defined as touching reference points. | 04-21-2016 |
Patent application number | Description | Published |
20110198757 | SEMICONDUCTOR STRUCTURE HAVING AN AIR-GAP REGION AND A METHOD OF MANUFACTURING THE SAME - A semiconductor structure includes a first metal-containing layer, a dielectric capping layer, a second metal-containing layer, and a conductive pad. The first metal-containing layer includes a set of metal structures, a dielectric filler disposed to occupy a portion of the first metal-containing layer, and an air-gap region defined by at least the set of metal structures and the dielectric filler and abutting at least a portion of the set of metal structures. The second metal-containing layer includes at least a via plug electrically connected to a portion of the set of metal structures. The conductive pad and the via plug do not overlap the air-gap region. | 08-18-2011 |
20110245949 | METHOD AND APPARATUS OF PATTERNING SEMICONDUCTOR DEVICE - Provided is an apparatus for fabricating a semiconductor device. The apparatus includes a first photomask and a second photomask. The first photomask has a plurality of first features thereon, and the first photomask having a first global pattern density. The second photomask has a plurality of second features thereon, and the second photomask has a second global pattern density. The plurality of first and second features collectively define a layout image of a layer of the semiconductor device. The first and second global pattern densities have a predetermined ratio. | 10-06-2011 |
20110291281 | PARTIAL AIR GAP FORMATION FOR PROVIDING INTERCONNECT ISOLATION IN INTEGRATED CIRCUITS - Partial air gap formation for providing interconnect isolation in integrated circuits is described. One embodiment is an integrated circuit (“IC”) structure includes a substrate having two adjacent interconnect features formed thereon; caps formed over and aligned with each of the interconnect features; sidewalls formed on opposing sides of each of the interconnect features and a gap formed between the interconnect features; and a dielectric material layer disposed over the substrate to cover the caps and the gap. | 12-01-2011 |
20120227018 | Method and Apparatus of Patterning Semiconductor Device - Provided is an apparatus for fabricating a semiconductor device. The apparatus includes a first photomask and a second photomask. The first photomask has a plurality of first features thereon, and the first photomask having a first global pattern density. The second photomask has a plurality of second features thereon, and the second photomask has a second global pattern density. The plurality of first and second features collectively define a layout image of a layer of the semiconductor device. The first and second global pattern densities have a predetermined ratio. | 09-06-2012 |
20130252144 | SEMICONDUCTOR STRUCTURE HAVING AN AIR-GAP REGION AND A METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor structure, the method includes removing a portion of a dielectric filler from a first metal-containing layer formed over a semiconductor substrate to define an air-gap region according to a predetermined air-gap pattern. The method further includes filling the air-gap region with a decomposable filler and forming a dielectric capping layer over the first metal-containing layer. The method further includes decomposing the decomposable filler. | 09-26-2013 |
20130260563 | Mask Treatment for Double Patterning Design - A method of forming a semiconductor device, and a product formed thereby, is provided. The method includes forming a pattern in a mask layer using, for example, double patterning or multi-patterning techniques. The mask is treated to smooth or round sharp corners. In an embodiment in which a positive pattern is formed in the mask, the treatment may comprise a plasma process or an isotropic wet etch. In an embodiment in which a negative pattern is formed in the mask, the treatment may comprise formation of conformal layer over the mask pattern. The conformal layer will have the effect of rounding the sharp corners. Other techniques may be used to smooth or round the corners of the mask. | 10-03-2013 |
20130295769 | METHODS OF PATTERNING SMALL VIA PITCH DIMENSIONS - Integrated circuit methods are described. The methods include providing a photomask that includes two main features for two via openings and further includes an optical proximity correction (OPC) feature linking the two main features; forming a hard mask layer on a substrate, the hard mask layer including two trench openings; forming a patterned resist layer over the hard mask layer using the photomask, wherein the patterned resist layer includes a peanut-shaped opening with two end portion aligned with the two trench openings of the hard mask layer, respectively; and performing a first etch process to the substrate using the hard mask layer and the patterned resist layer as a combined etch mask. | 11-07-2013 |
20150200160 | SEMICONDUCTOR STRUCTURE HAVING AN AIR-GAP REGION AND A METHOD OF MANUFACTURING THE SAME - A semiconductor structure comprises a first conductive material-containing layer. The first conductive material-containing layer comprises a dielectric material, at least two conductive structures in the dielectric material, and an air-gap region in the dielectric material between the at least two conductive structures. The semiconductor structure also comprises a capping layer over the at least two conductive structures and the air-gap region. The semiconductor structure further comprises a second conductive material-containing layer over the capping layer. The second conductive material-containing layer comprises a via plug electrically connected to one of the at least two conductive structures. The via plug is separated from the air-gap region by at least a first predetermined distance. The semiconductor structure additionally comprises a conductive pad over the second conductive material-containing layer. The conductive pad is offset from the air-gap region by at least a second predetermined distance. | 07-16-2015 |
Patent application number | Description | Published |
20090282374 | Dummy Pattern Design for Reducing Device Performance Drift - A method of forming an integrated circuit structure on a chip includes extracting an active pattern including a diffusion region; enlarging the active pattern to form a dummy-forbidden region having a first edge and a second edge perpendicular to each other; and adding stress-blocking dummy diffusion regions throughout the chip, which includes adding a first stress-blocking dummy diffusion region adjacent and substantially parallel to the first edge of the dummy-forbidden region; and adding a second stress-blocking dummy diffusion region adjacent and substantially parallel to the second edge of the dummy-forbidden region. The method further includes, after the step of adding the stress-blocking dummy diffusion regions throughout the chip, adding general dummy diffusion regions into remaining spacings of the chip. | 11-12-2009 |
20110204449 | Dummy Pattern Design for Reducing Device Performance Drift - A method of forming an integrated circuit structure on a chip includes extracting an active pattern including a diffusion region; enlarging the active pattern to form a dummy-forbidden region having a first edge and a second edge perpendicular to each other; and adding stress-blocking dummy diffusion regions throughout the chip, which includes adding a first stress-blocking dummy diffusion region adjacent and substantially parallel to the first edge of the dummy-forbidden region; and adding a second stress-blocking dummy diffusion region adjacent and substantially parallel to the second edge of the dummy-forbidden region. The method further includes, after the step of adding the stress-blocking dummy diffusion regions throughout the chip, adding general dummy diffusion regions into remaining spacings of the chip. | 08-25-2011 |
20110291197 | INTEGRATED CIRCUITS AND MANUFACTURING METHODS THEREOF - An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is spaced from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. The first metallic layer is electrically coupled with the first source region. The first metallic layer and the first diffusion area overlap with a first distance. A second metallic layer is electrically coupled with the first drain region and the second drain region. The second metallic layer and the first diffusion area overlap with a second distance. The first distance is larger than the second distance. | 12-01-2011 |
20130130456 | INTEGRATED CIRCUITS AND MANUFACTURING METHODS THEREOF - A method of forming an integrated circuit including forming a first diffusion area and a second diffusion area on a substrate, wherein the first diffusion area is configured for a first type transistor, the second diffusion area is configured for a second type transistor. The method further includes forming first source and drain regions in the first diffusion area. The method further includes forming second source and drain regions in the second diffusion area. The method further includes forming a gate electrode extending across the first diffusion area and the second diffusion area. The method further includes forming a first metallic layer, a second metallic layer, and a third metallic layer. The first metallic layer is electrically coupled with the first source region. The second metallic layer is electrically coupled with the first and second drain regions. The third metallic layer is electrically coupled with the second source region. | 05-23-2013 |
Patent application number | Description | Published |
20140246751 | Integrated Circuit Using Deep Trench Through Silicon (DTS) - An embodiment radio frequency area of an integrated circuit includes a substrate having a first resistance, the substrate including an implant region, a buried oxide layer disposed over the substrate, an interface layer between the substrate and the buried oxide layer, the interface layer having a second resistance lower than the first resistance, a silicon layer disposed over the buried oxide layer, and an interlevel dielectric disposed in a deep trench, the deep trench extending through the silicon layer, the buried oxide layer, and the interface layer over the implant region. In an embodiment, the deep trench extends through a polysilicon layer disposed over the silicon layer. | 09-04-2014 |
20150115301 | ELECTRODE STRUCTURE AND LIGHT EMITTING DIODE STRUCTURE HAVING THE SAME - An electrode structure includes at least one reflection layer, a barrier layer, and a conductive pad. The barrier layer includes a first barrier layer and a second barrier layer. The first and second barrier layers are stacked on the reflection layer in sequence. The first and second barrier layers are made of different materials. The conductive pad is located on the barrier layer. | 04-30-2015 |
20150115381 | MECHANISMS FOR FORMING RADIO FREQUENCY (RF) AREA OF INTEGRATED CIRCUIT STRUCTURE - Embodiments of mechanisms of forming a radio frequency area of an integrated circuit are provided. The radio frequency area of an integrated circuit structure includes a substrate, a buried oxide layer formed over the substrate, and an interface layer formed between the substrate and the buried oxide layer. The radio frequency area of an integrated circuit structure also includes a silicon layer formed over the buried oxide layer and an interlayer dielectric layer formed in a deep trench. The radio frequency area of an integrated circuit structure further includes the interlayer dielectric layer extending through the silicon layer, the buried oxide layer and the interface layer. The radio frequency area of an integrated circuit structure includes an implant region formed below the interlayer dielectric layer in the deep trench and a polysilicon layer formed below the implant region. | 04-30-2015 |
20150132918 | Integrated Circuit Using Deep Trench Through Silicon (DTS) - An embodiment radio frequency area of an integrated circuit is disclosed. The radio frequency area includes a substrate having an implant region. The substrate has a first resistance. A buried oxide layer is disposed over the substrate and an interface layer is disposed between the substrate and the buried oxide layer. The interface layer has a second resistance lower than the first resistance. A silicon layer is disposed over the buried oxide layer and an interlevel dielectric is disposed in a deep trench. The deep trench extends through the silicon layer, the buried oxide layer, and the interface layer over the implant region. The deep trench may also extend through a polysilicon layer disposed over the silicon layer. | 05-14-2015 |
20150206902 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - Embodiments for forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a buried oxide layer formed over the substrate. An interface layer is formed between the substrate and the buried oxide layer. The semiconductor device structure also includes a silicon layer formed over the buried oxide layer; and a polysilicon layer formed over the substrate and in a deep trench. The polysilicon layer extends through the silicon layer, the buried oxide layer and the interface layer. | 07-23-2015 |
20150270143 | HANDLE WAFER FOR HIGH RESISTIVITY TRAP-RICH SOI - The present disclosure relates to a silicon-on-insulator (SOI) substrate having a trap-rich layer, with crystal defects, which is disposed within a handle wafer, and an associated method of formation. In some embodiments, the SOI substrate has a handle wafer. A trap-rich layer, having a plurality of crystal defects that act to trap carriers, is disposed within the handle wafer at a position abutting a top surface of the handle wafer. An insulating layer is disposed onto the handle wafer. The insulating layer has a first side abutting the top surface of the handle wafer and an opposing second side abutting a thin layer of active silicon. By forming the trap-rich layer within the handle wafer, fabrication costs associated with depositing a trap-rich material (e.g., polysilicon) onto a handle wafer are reduced and thermal instability issues are prevented. | 09-24-2015 |
20160099169 | MECHANISMS FOR FORMING RADIO FREQUENCY (RF) AREA OF INTEGRATED CIRCUIT STRUCTURE - The methods for forming a radio frequency area of an integrated circuit are provided. The method includes forming a buried oxide layer over a substrate, and an interface layer is formed between the substrate and the buried oxide layer. The method also includes etching through the buried oxide layer and the interface layer to form a deep trench, and a bottom surface of the deep trench is level with a bottom surface of the interface layer. The method further includes forming an implant region directly below the deep trench and forming an interlayer dielectric layer in the deep trench. | 04-07-2016 |