Yates, Jr.
Benjamin Harrison Yates, Jr., Santa Clara, CA US
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20140103637 | COUPLERS - A coupler (for coupling a plug with a gas supply) may include a body having a first through hole and a second through hole. The coupler may further include a ring having a first cavity and a second cavity. The first cavity may be pneumatically disconnected from the second through hole when the ring is disposed at a first position with respect to the body. The first cavity may be pneumatically connected to both the first through hole and the second through hole when the ring is disposed at a second position with respect to the body. The second cavity may be pneumatically connected to the second through hole when the ring is disposed at the first position with respect to the body. The second cavity may be pneumatically disconnected from the second through hole when the ring is disposed at the second position with respect to the body. | 04-17-2014 |
John S. Yates, Jr., Needham, MA US
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20090204785 | Computer with two execution modes - A computer. A processor pipeline alternately executes instructions coded for first and second different computer architectures or coded to implement first and second different processing conventions. A memory stores instructions for execution by the processor pipeline, the memory being divided into pages for management by a virtual memory manager, a single address space of the memory having first and second pages. A memory unit fetches instructions from the memory for execution by the pipeline, and fetches stored indicator elements associated with respective memory pages of the single address space from which the instructions are to be fetched. Each indicator element is designed to store an indication of which of two different computer architectures and/or execution conventions under which instruction data of the associated page are to be executed by the processor pipeline. The memory unit and/or processor pipeline recognizes an execution flow from the first page, whose associated indicator element indicates the first architecture. or execution convention, to the second page, whose associated indicator element indicates the first architecture or execution convention. In response to the recognizing, a processing mode of the processor pipeline or a storage content of the memory adapts to effect execution of instructions in the architecture and/or under the convention indicated by the indicator element corresponding to the instruction's page. | 08-13-2009 |
John S. Yates, Jr., Concord, MA US
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20120144167 | APPARATUS FOR EXECUTING PROGRAMS FOR A FIRST COMPUTER ARCHITECTURE ON A COMPUTER OF A SECOND ARCHITECTURE - A multi-instruction set architecture (ISA) computer system includes a computer program, a first processor, a second processor, a profiler, and a translator. The computer program includes instructions of a first ISA, the first ISA having a first complexity. The first processor is configured to execute instructions of the first ISA. The second processor is configured to execute instructions of a second ISA, the second ISA being different than the first ISA and having a second complexity, wherein the second complexity is less than the first complexity. The profiler is configured to select a block of the computer program for translation to instructions of the second ISA, wherein the block includes one or more instructions of the first ISA. The translator is configured to translate the block of the first ISA into instructions of the second ISA for execution by the second processor. | 06-07-2012 |
20130346428 | PROCESSING COLUMNS IN A DATABASE ACCELERATOR WHILE PRESERVING ROW-BASED ARCHITECTURE - Database processing using columns to present to a processing unit decompressed column data without changing the underlying row-based database architecture. For some embodiments, a database accelerator is used to efficiently process the columns of a database and output tuples to a processing unit's memory, such that the columns can be quickly processed (with the advantages of a column-based architecture) to create tuples of requested data, but without having to depart from a row-based architecture at the processing unit level or having decompressed data scattered throughout the processing unit's memory. | 12-26-2013 |
20150234871 | PROCESSING COLUMNS IN A DATABASE ACCELERATOR WHILE PRESERVING ROW-BASED ARCHITECTURE - Database processing using columns to present to a processing unit decompressed column data without changing the underlying row-based database architecture. For some embodiments, a database accelerator is used to efficiently process the columns of a database and output tuples to a processing unit's memory, such that the columns can be quickly processed (with the advantages of a column-based architecture) to create tuples of requested data, but without having to depart from a row-based architecture at the processing unit level or having decompressed data scattered throughout the processing unit's memory. | 08-20-2015 |
Travis Yates, Jr., Lakeside, TX US
Patent application number | Description | Published |
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20150275998 | Spring Tension Adjustment Mechanism - According to one embodiment, a spring tension adjustment device for adjusting tension in a spring includes a rotation feature and a plurality of spring-attachment features. The rotation feature defines a first axis of rotation. Each spring-attachment feature is configured to receive one end of a spring, each spring-attachment feature being located at a different distance from the rotation feature. | 10-01-2015 |