Patent application number | Description | Published |
20090043947 | MANAGING PROCESSING DELAYS IN AN ISOCHRONOUS SYSTEM - Command cycles incorporate mechanisms to inform a host processor in advance of a need to service the memory so that the host can respond when it suits the host, but in time for the service to be performed before a catastrophic failure. The regular host cycle need not be interrupted for such notification. | 02-12-2009 |
20090044190 | URGENCY AND TIME WINDOW MANIPULATION TO ACCOMMODATE UNPREDICTABLE MEMORY OPERATIONS - The variable latency associated with flash memory due to background data integrity operations is managed in order to allow the flash memory to be used in isochronous systems. A system processor is notified regularly of the nature and urgency of requests for time to ensure data integrity. Minimal interruptions of system processing are achieved and operation is ensured in the event of a power interruption. | 02-12-2009 |
20090070529 | DATA PROTECTION AFTER POSSIBLE WRITE ABORT OR ERASE ABORT - A portion of a nonvolatile memory array that is likely to contain, partially programmed data may be identified from a high sensitivity read, by applying stricter than usual ECC requirements, or using pointers to programmed sectors. The last programmed data may be treated as likely to be partially programmed data. Data in the identified portion may be copied to another location, or left where it is with an indicator to prohibit further programming to the same cells. To avoid compromising previously stored data during subsequent programming, previously stored data may be backed up. Backing up may be done selectively, for example, only for nonsequential data, or only when the previously stored data contains an earlier version of data being programmed. If a backup copy already exists, another backup copy is not created. Sequential commands are treated as a single command if received within a predetermined time period. | 03-12-2009 |
20150149694 | Adaptive Context Disbursement for Improved Performance in Non-Volatile Memory Systems - A controller circuit for a non-volatile memory of one or more memory circuits is described. The controller is connectable by a port with the memory circuits through a bus structure and can operate the memory circuits according to one or more threads. The controller includes a command processing section to issue high level commands for execution in the memory circuits and a memory circuit interface module to issue in sequence by the port to the memory circuits a series of instruction derived from the high level commands. A queue manager on the controller derives the series of instructions from the high level commands. When deriving a series of instruction from a set of high level data access commands, the queue manager can modify the timing for the issuance to the memory circuit interface module of memory circuit check status instructions based upon feedback from the memory circuit interface module and the state of earlier instruction in the series. | 05-28-2015 |
20150154132 | SYSTEM AND METHOD OF ARBITRATION ASSOCIATED WITH A MULTI-THREADED SYSTEM - A data storage device includes a controller coupled to a non-volatile memory via a data path element. The controller includes a first queue that includes a first set of requests and a second queue that includes a second set of requests. The controller further includes logic configured to assign a particular request from the first queue or from the second queue to have access to the data path element. When the logic is in a first mode, the logic selects a particular request is selected based on an arbitration scheme applied to the first queue and the second queue. When the logic is in a second mode, the logic selects a prioritized request from the first set of requests or the second set of requests independently of the arbitration scheme. | 06-04-2015 |
20150261613 | Storage Module and Method for Improving Boot Time During Block Binary Searches - A storage controller is configured to find a last-written page in a block in a memory by sending a command to the memory to read a page of data, receiving at least some of the data from that page, and analyzing the at least some of the data from that page to determine if that page is a written page. In one embodiment, the storage controller instructs the memory to read the page of data using a sense time that is shorter than a sense time used to read a page of data in response to a read request from a host controller. Additionally or alternatively, the amount of the data received by the storage controller can be less than the amount of data received when reading a page of data in response to a read request from a host controller. | 09-17-2015 |
20150262714 | Finding Read Disturbs on Non-Volatile Memories - In non-volatile memory devices, the accessing of data on word line can degrade the data quality on a neighboring word line, in what is called a read disturb. Techniques are presented for determining word lines likely to suffer read disturbs by use of a hash tree for tracking the number of reads. Read counters are maintained for memory units at a relatively coarse granularity, such as a die or block. When the counter for one of these units reaches a certain level, it is subdivided into sub-units, each with their own read counter, in a process that be repeated to determine frequently read word lines with a fine level of granularity while only using a relatively modest amount of RAM on the controller to store the counters. | 09-17-2015 |