Patent application number | Description | Published |
20150249209 | SELF-ALIGNED TOP CONTACT FOR MRAM FABRICATION - Systems and methods for forming precise and self-aligned top metal contact for a Magnetoresistive random-access memory (MRAM) device include forming a magnetic tunnel junction (MTJ) in a common interlayer metal dielectric (IMD) layer with a logic element. A low dielectric constant (K) etch stop layer is selectively retained over an exposed top surface of the MTJ. Etching is selectively performed through a top IMD layer formed over the low K etch stop layer and the common IMD layer, based on a first chemistry which prevents etching through the low K etch stop layer. By switching chemistry to a second chemistry which precisely etches through the low K etch stop layer, an opening is created for forming a self-aligned top contact to the exposed top surface of the MTJ. | 09-03-2015 |
20150280112 | MAGNETIC TUNNEL JUNCTION AND METHOD FOR FABRICATING A MAGNETIC TUNNEL JUNCTION - An improved magnetic tunnel junction device and methods for fabricating the improved magnetic tunnel junction device are provided. The provided two-etch process reduces etching damage and ablated material redeposition. In an example, provided is a method for fabricating a magnetic tunnel junction (MTJ). The method includes forming a buffer layer on a substrate, forming a bottom electrode on the substrate, forming a pin layer on the bottom electrode, forming a barrier layer on the pin layer, and forming a free layer on the barrier layer. A first etching includes etching the free layer, without etching the barrier layer, the pin layer, and the bottom electrode. The method also includes forming a top electrode on the free layer, as well as forming a hardmask layer on the top electrode. A second etching includes etching the hardmask layer; the top electrode layer, the barrier layer, the pin layer, and the bottom electrode. | 10-01-2015 |
20150287910 | REPLACEMENT CONDUCTIVE HARD MASK FOR MULTI-STEP MAGNETIC TUNNEL JUNCTION (MTJ) ETCH - A multi-step etch technique for fabricating a magnetic tunnel junction (MTJ) apparatus includes forming a first conductive hard mask on a first electrode of the MTJ apparatus for etching the first electrode during a first etching step. The method also includes forming a second conductive hard mask on the first conductive hard mask for etching magnetic layers of the MTJ apparatus during a second etching step. A spacer layer is conformally deposited on sidewalls of the first conductive hard mask. The second conductive hard mask is deposited on the first conductive hard mask and aligned with the spacer layer on the sidewalls of the first conductive hard mask. | 10-08-2015 |
20150311429 | MAGNETIC TUNNEL JUNCTION AND METHOD FOR FABRICATING A MAGNETIC TUNNEL JUNCTION - An improved magnetic tunnel junction device and methods for fabricating the improved magnetic tunnel junction device are provided. The provided two-etch process reduces etching damage and ablated material redeposition. In an example, provided is a method for fabricating a magnetic tunnel junction (MTJ). The method includes forming a buffer layer on a substrate, forming a bottom electrode on the substrate, forming a pin layer on the bottom electrode, forming a barrier layer on the pin layer, and forming a free layer on the barrier layer. A first etching includes etching the free layer, without etching the barrier layer, the pin layer, and the bottom electrode. The method also includes forming a top electrode on the free layer, as well as forming a hardmask layer on the top electrode. A second etching includes etching the hardmask layer; the top electrode layer, the barrier layer, the pin layer, and the bottom electrode. | 10-29-2015 |
20150340593 | ETCH-RESISTANT PROTECTIVE COATING FOR A MAGNETIC TUNNEL JUNCTION DEVICE - A method of forming a magnetic tunnel junction (MTJ) device includes forming a spacer on an exposed side portion of the MTJ device. The method further includes forming an etch-resistant protective coating associated with the MTJ device. The etch-resistant protective coating provides greater etch resistance than the spacer. | 11-26-2015 |
20160043137 | RESISTIVE MEMORY DEVICE WITH ZERO-TRANSISTOR, ONE-RESISTOR BIT CELLS INTEGRATED WITH ONE-TRANSISTOR, ONE-RESISTOR BIT CELLS ON A DIE - A resistive memory array includes an array of one-transistor, one-resistor (1T1R) bit cells on a die. The resistive memory array also includes an array of zero-transistor, one-resistor (0T1R) bit cells arranged with the array of 1T1R bit cells on the same die. | 02-11-2016 |
20160043304 | SELF-COMPENSATION OF STRAY FIELD OF PERPENDICULAR MAGNETIC ELEMENTS - A perpendicular magnetic tunnel junction (pMTJ) device includes a perpendicular reference layer, a tunnel barrier layer on a surface of the perpendicular reference layer, and a perpendicular free layer on a surface of the tunnel barrier layer. The pMTJ device also includes a dielectric passivation layer on the tunnel barrier layer and surrounding the perpendicular free layer. The pMTJ device further includes a high permeability material on the dielectric passivation layer that is configured to be magnetized by the perpendicular reference layer and to provide a stray field to the perpendicular free layer that compensates for a stray field from the perpendicular reference layer. | 02-11-2016 |
20160049185 | DIFFERENTIAL MAGNETIC TUNNEL JUNCTION PAIR INCLUDING A SENSE LAYER WITH A HIGH COERCIVITY PORTION - An apparatus includes a first magnetic tunnel junction (MTJ) device of a differential MTJ pair. The apparatus further includes a second MTJ device of the differential MTJ pair. The first MTJ device includes a sense layer having a high coercivity portion. | 02-18-2016 |
20160079307 | SUB-LITHOGRAPHIC PATTERNING OF MAGNETIC TUNNELING JUNCTION DEVICES - A method for fabricating a magnetic tunnel junction (MTJ) device includes creating a recess within a second patterning layer, in which a first patterning layer overhangs the recessed second patterning layer. Such a method further includes depositing a film into the recess to create a keyhole pattern within the deposited film. The method further includes transferring the keyhole pattern through a hard mask layer to an MTJ stack. The method also includes depositing a conductive material into the transferred keyhole pattern and on an MTJ stack. The method also includes removing the hard mask layer to create a conductive hard mask pillar. | 03-17-2016 |
20160093668 | MRAM INTEGRATION WITH LOW-K INTER-METAL DIELECTRIC FOR REDUCED PARASITIC CAPACITANCE - Systems and methods of integration of resistive memory elements with logic elements in advanced nodes with improved mechanical stability and reduced parasitic capacitance include a resistive memory element and a logic element formed in a common integration layer extending between a bottom cap layer and a top cap layer. At least a first intermetal dielectric (IMD) layer of high-K value is formed in the common integration layer and surrounding at least the resistive memory element, to provide high rigidity and mechanical stability. A second IMD layer of low-K value to reduce parasitic capacitance of the logic element is formed in either the common integration layer, a top layer above the top cap layer or an intermediate layer in between the top and bottom cap layers. Air gaps may be formed in one or more IMD layers to further reduce capacitance. | 03-31-2016 |