Patent application number | Description | Published |
20100291888 | MULTI-MODE MULTI-BAND POWER AMPLIFIER MODULE - A multi-mode multi-band power amplifier (PA) module is described. In an exemplary design, the PA module includes multiple power amplifiers, multiple matching circuits, and a set of switches. Each power amplifier provides power amplification for its input signal when selected. Each matching circuit provides impedance matching and filtering for its power amplifier and provides a respective output signal. The switches configure the power amplifiers to support multiple modes, with each mode being for a particular radio technology. Each power amplifier supports at least two modes. The PA module may further include a driver amplifier and an additional matching circuit. The driver amplifier amplifies an input signal and provides an amplified signal to the power amplifiers. The additional matching circuit combines the outputs of other matching circuits and provides an output signal with higher output power. The driver amplifier and the power amplifiers can support multiple output power levels. | 11-18-2010 |
20100327976 | INTEGRATED POWER AMPLIFIER WITH LOAD INDUCTOR LOCATED UNDER IC DIE - A compact integrated power amplifier is described herein. In an exemplary design, an apparatus includes (i) an integrated circuit (IC) die having at least one transistor for a power amplifier and (ii) an IC package having a load inductor for the power amplifier. The IC die is mounted on the IC package with the transistor(s) located over the load inductor. In an exemplary design, the IC die includes a transistor manifold that is placed over the load inductor on the IC package. The transistor(s) are fabricated in the transistor manifold, have a drain connection in the center of the transistor manifold, and have source connections on two sides of the transistor manifold. The IC die and the IC package may include one or more additional power amplifiers. The transistor(s) for each power amplifier may be located over the load inductor for that power amplifier. | 12-30-2010 |
20110018632 | POWER AMPLIFIER WITH SWITCHED OUTPUT MATCHING FOR MULTI-MODE OPERATION - Exemplary embodiments are directed to a transmitter with a power amplifier and a switched output matching circuit implementing a plurality of output paths for a plurality of operating modes is described. The power amplifier receives an input RF signal and provides an amplified RF signal. An output matching network performs impedance transformation from low impedance at the power amplifier output to higher impedance at the matching network output. The plurality of output paths are coupled to the output matching network. Each output path provides a different target output impedance for the power amplifier and routes the amplified RF signal from the power amplifier to an antenna when that output path is selected. Each output path may include a matching network coupled in series with a switch. The matching network provides the target output impedance for the power amplifier when the output path is selected. The switch couples or decouples the output path to/from the power amplifier. | 01-27-2011 |
20110037516 | MULTI-STAGE IMPEDANCE MATCHING - Exemplary techniques for performing impedance matching are described. In an exemplary embodiment, the apparatus may include an amplifier (e.g., a power amplifier) coupled to first and second matching circuits. The first matching circuit may include multiple stages coupled to a first node and may provide input impedance matching for the amplifier. The second matching circuit may include multiple stages coupled to a second node and may provide output impedance matching for the amplifier. At least one switch may be coupled between the first and second nodes and may bypass or select the amplifier. The first and second nodes may have a common impedance. The apparatus may further include a second amplifier coupled in parallel with the amplifier and further to the matching circuits. The second matching circuit may include a first input stage coupled to the amplifier, a second input stage coupled to the second amplifier, and a second stage coupled to the two input stages via switches. | 02-17-2011 |
20110037519 | AMPLIFIER WITH VARIABLE MATCHING CIRCUIT TO IMPROVE LINEARITY - Techniques for reducing distortion and improving linearity of amplifiers are described. In an exemplary design, an apparatus includes a driver amplifier, a variable matching circuit, and a power amplifier. The driver amplifier amplifies a first RF signal and provides a second RF signal. The variable matching circuit receives the second RF signal and provides a third RF signal. The power amplifier amplifies the third RF signal and provides a fourth RF signal. The variable matching circuit matches a fixed impedance at the output of the driver amplifier to a variable impedance at the input of the power amplifier in order to improve the linearity of the amplifiers. In an exemplary design, the power amplifier includes a first transistor (e.g., an NMOS transistor) of a first type, and the variable matching circuit includes a second transistor (e.g., a PMOS transistor) of a second type that is different from the first type. | 02-17-2011 |
20110043284 | STACKED AMPLIFIER WITH DIODE-BASED BIASING - Techniques for improving linearity of amplifiers are described. In an exemplary design, an amplifier (e.g., a power amplifier) may include a plurality of transistors coupled in a stack and at least one diode. The plurality of transistors may receive and amplify an input signal and provide an output signal. The at least one diode may be operatively coupled to at least one transistor in the stack. Each diode may provide a variable bias voltage to an associated transistor in the stack. Each diode may have a lower voltage drop across the diode at high input power and may provide a higher bias voltage to the associated transistor at high input power. The at least one transistor may have higher gain at high input power due to the higher bias voltage from the at least one diode. The higher gain may improve the linearity of the amplifier. | 02-24-2011 |
20110043285 | DIGITAL TUNABLE INTER-STAGE MATCHING CIRCUIT - A tunable inter-stage matching circuit that can improve performance is described. In an exemplary design, an apparatus includes a first active circuit (e.g., a driver amplifier), a second active circuit (e.g., a power amplifier), and a tunable inter-stage matching circuit coupled between the first and second active circuits. The tunable inter-stage matching circuit includes a tunable capacitor that can be varied in discrete steps to adjust impedance matching between the first and second active circuits. In an exemplary design, the tunable capacitor includes (i) a plurality of capacitors coupled in parallel and (ii) a plurality of switches coupled to the plurality of capacitors, one switch for each capacitor. Each switch may be turned on to select an associated capacitor or turned off to unselect the associated capacitor. The tunable capacitor may further include a fixed capacitor coupled in parallel with the plurality of capacitors. | 02-24-2011 |
20110316636 | DIGITAL TUNABLE INTER-STAGE MATCHING CIRCUIT - A tunable inter-stage matching circuit that can improve performance is described. In an exemplary design, an apparatus comprises a driver amplifier and a power amplifier. The apparatus may further include an inter-stage matching circuit tunable in discrete steps for matching impedances between the driver amplifier and the power amplifier. The tunable inter-stage matching circuit may include a bank of capacitors, each capacitor of the bank coupled in series with a switch for coupling the capacitor to a ground voltage. | 12-29-2011 |
20130084915 | MULTI-ANTENNA WIRELESS DEVICE WITH POWER AMPLIFIERS HAVING DIFFERENT CHARACTERISTICS - A wireless device with power amplifiers having different characteristics to support transmission on multiple antennas is disclosed. These power amplifiers may have different gain, different maximum output power levels, etc. in order to meet requirements of different wireless systems. In an exemplary design, an apparatus includes first and second power amplifiers having different characteristics. The first power amplifier amplifies a first input signal and provides a first output signal for a first antenna. The second power amplifier amplifies the first input signal or a second input signal and provides a second output signal for a second antenna, e.g., in a MIMO mode or a transmit diversity mode. Only the first or second power amplifier amplifies another input signal and provides another output signal to the first antenna, e.g., in a CDMA mode or a GSM mode. | 04-04-2013 |
20130190036 | MULTI-MODE BYPASS DRIVER AMPLIFIER WITH TUNABLE LOAD MATCHING - A multi-mode driver amplifier with tunable load matching is disclosed. In an exemplary design, an apparatus includes a multi-mode driver amplifier and a tunable impedance matching circuit. The driver amplifier amplifies an input radio frequency (RF) signal and provides an amplified RF signal. The tunable impedance matching circuit matches an output impedance of the driver amplifier. The apparatus may include a main transmit path and a bypass transmit path. The bypass transmit path may include the driver amplifier and the tunable impedance matching circuit and no power amplifier. The main transmit path may include a second driver amplifier and a power amplifier. The main transmit path may be selected for transmit power levels higher than a threshold level, and the bypass transmit path may be selected for transmit power levels lower than the threshold level. | 07-25-2013 |
20140266448 | ADAPATIVE POWER AMPLIFIER - Exemplary embodiments are related to an envelope-tracking power amplifier. A device may include a first transistor of a plurality of transistors in a stacked configuration configured to receive a supply voltage varying with an envelope of a radio-frequency (RF) input signal. The device may further include a second transistor of the plurality in the stacked configuration coupled to a reference voltage and configured to receive a dynamic bias voltage varying inversely proportional to the supply voltage. | 09-18-2014 |
Patent application number | Description | Published |
20100229009 | Applying power to a network interface - A host device capable of communicating with an external network. The host device may comprise a power-application unit and a network interface. The power-application unit may receive from a power-supply unit a first power-supply output having a first voltage level and a second power-supply output having a second voltage level. The power-application unit may be controllable for producing selectively a first power-application output having a third voltage level from the first power-supply output and a second power-application output having a fourth voltage level from the second power-supply output. The network interface may transmit data to and receive data from an external network, and may be powered at least in part by the first and second power-application outputs. | 09-09-2010 |
20100241505 | INK CARTRIDGE VENDING MACHINE - A vending machine capable of refilling used ink cartridges as well as dispensing filled ink cartridges is closed. The vending machine includes at least one cartridge receptacle for receiving an ink cartridge, a user interface, a display unit, a nozzle health check module, a printhead servicing module, an ink reservoir, an ink refilling unit, a compartment containing new ink cartridges, a compartment containing filled, second-hand ink cartridges, and a recycle compartment for receiving discarded ink cartridges. The user is presented by the display unit with the option of (a) refilling a used cartridge, (b) purchasing a filled cartridge, or (c) returning a used cartridge in exchange for a purchase rebate or a discount voucher. When the user selects the option of refilling, the vending machine executes a refilling subroutine which includes checking the nozzle health. | 09-23-2010 |
20130027724 | PRINTER - Printer including a controller and a communication circuit for receiving a communication in a low power mode. In an example, the communication activates a deactivated controller and/or transmits content of the communication to the controller. | 01-31-2013 |
20130033532 | PRINTER HAVING ENERGY STORAGE DEVICE - A printer includes an energy storage device and a charger for charging the energy storage device and for providing a first DC voltage. The printer includes a first DC-to-DC voltage converter for converting the first DC voltage to a second DC voltage. The printer includes first printer electronics powered by the second DC voltage. | 02-07-2013 |
20140334197 | POWER SUPPLY - The present disclosure describes a power supply with multiple operating modes, to detect a load condition of an electronic device, and to automatically change between the multiple operating modes to supply an output direct current (DC) signal to the electronic device based on the load condition detected by the load detection mechanism. The power supply includes multiple control topologies that are each associated with one of the operating modes. Changing from a first operation mode to a second operation mode includes changing from a first control topology associated with the first operation mode to a second control topology associated with the second operating mode to supply the output DC signal at a predetermined voltage level. | 11-13-2014 |
Patent application number | Description | Published |
20090070761 | System and method for data communication with data link backup - According to one embodiment of the invention, there is provided a data communication device for processing a data stream, including a runtime virtual machine (VM) and a mirror VM. The two VMs are independently running on the same physical hardware of the data communication device. The runtime VM is operable for receiving the data stream and establishing a plurality of data links to process the data stream. The mirror VM is operable for backing up the data links established by the runtime VM. The data stream is switched from the runtime VM to the mirror VM for processing if a predetermined condition occurs in the runtime VM. | 03-12-2009 |
20100090831 | Electronic device with radio frequency identification (RFID) technology - An electronic device includes a radio frequency identification (RFID) reader and a controller coupled to the RFID reader. The RFID reader is used for detecting an RFID tag when a distance between the RFID tag and the RFID reader is within a predetermined range. The controller is used for enabling the electronic device to operate at an emergency mode when the distance between the RFID tag and the RFID reader is beyond the predetermined range. In the emergency mode, the electronic device is locked. | 04-15-2010 |
20100180334 | NETWROK APPARATUS AND METHOD FOR TRANSFERING PACKETS - A network apparatus cluster for transferring multiple packets of a communication session to a network node includes a primary unit and a subordinate unit coupled together. The primary unit is operable for receiving the packets comprising a first packet and multiple subsequent packets, for generating a session data set indicating the communication session and a balance data set based on the first packet, and for determining that the subsequent packets belong to the communication session according to the session data set. The balance data set indicates whether the first packet is distributed to the primary unit or the subordinate unit. The subsequent packets are transferred from the primary unit to the network node according to the balance data set. | 07-15-2010 |
20100211544 | SYSTEM WITH SESSION SYNCHRONIZATION - A computer-readable medium having computer-executable modules is disclosed. The computer-executable modules include a first session database for storing multiple sessions indicating information interchange between at least two communicating devices. The computer-executable modules further include a controller operable for selecting a session from the first session database according to a session update rate indicating the number of sessions updated in the first session database during a given period of time and for synchronizing the session from the first session database to a second session database. | 08-19-2010 |
Patent application number | Description | Published |
20090070366 | METHOD AND SYSTEM FOR WEB DOCUMENT CLUSTERING - Method and System for web documents clustering are provided. The method for web documents clustering comprises the steps of: inputting a plurality of web documents; collecting information of the links and the directory structure of the inputted web documents; extracting, according to the collected links and directory structure, a hierarchical structure for the plurality of web documents; and generating and outputting, based on the extracted hierarchical structure, one or more clusters of the plurality of web documents. In some embodiments, the hierarchical relations of the generated clusters can also be outputted at the same time. Compared with the prior art, the method and system for web documents clustering according to the present invention can improve substantially the accuracy and efficiency of the web documents clustering. | 03-12-2009 |
20090077126 | METHOD AND SYSTEM FOR CALCULATING COMPETITIVENESS METRIC BETWEEN OBJECTS - Method and System for calculating competitiveness metric between objects are provided. The method comprises the steps of: obtaining a first object and a second object, the first and second objects having a first profile and a second profile, each composed of a plurality of attributes, respectively; normalizing the first profile and the second profile with reference to ontology information; and calculating, based on the normalized first and second profiles, a competitiveness metric between the first and second objects. In one embodiment, the ontology information is a common attribute name vocabulary, and the step of normalizing is configured for adjusting the structures of the first and second profiles to a unified profile structure, computing the sub-metrics between the corresponding attributes in the unified profile, and computing the weighed sum of the sub-metrics as the final competitiveness metric of the first and second objects. In another embodiment, the ontology information is an object category tree, and the step of normalizing is configured for mapping the first and second profiles to one or more nodes in the object category tree, computing the probabilities of mapping the profiles to different nodes, and then, based on the obtained semantic distances between the nodes, computing the final competitiveness metric according the probabilities and the semantic distances. | 03-19-2009 |
20090083244 | METHOD AND SYSTEM FOR SUBJECT RELEVANT WEB PAGE FILTERING BASED ON NAVIGATION PATHS INFORMATION - Method and system to utilize the set of navigation paths of web pages as the contextual information for subject relevant web page filtering with high accuracy are provided. The method comprises the steps of: obtaining all web pages in one or more web pages collections; collecting information of the links among the obtained web pages; extracting, based on the collected links, a set of navigation paths of each of the obtained web pages; and filtering the obtained web pages based on the extracted set of navigation paths to obtain desired web pages. In some embodiments, the extraction of the navigation paths is preferably performed on the navigation links of the web pages. Therefore, the method also comprises the process for deleting non-navigation links from all the links of the web pages. Compared with the prior art, the present invention can utilize the contextual information of the web pages for web page filtering in a more sufficient way, thereby improving the accuracy and objectivity of the web page filtering. | 03-26-2009 |
20090125549 | METHOD AND SYSTEM FOR CALCULATING COMPETITIVENESS METRIC BETWEEN OBJECTS - Method and System for calculating competitiveness metric between objects are provided. The method comprises the steps of: obtaining a first object and a second object; selecting, from all the relation instances stored in a relation instance repository, associated relation instances related to the first and second objects; and calculating, based on the selected associated relation instances, an extensional competitiveness metric S | 05-14-2009 |
20090327338 | HIERARCHY EXTRACTION FROM THE WEBSITES - The present invention provides methods and systems for building object hierarchy. The method includes: obtaining a set of web pages from a website; conducting an inter-page analysis on the obtained web pages to extract a hierarchy of the web pages; conducting an intra-page analysis on each of the obtained web pages to identify the semantic blocks within the web page and extract a hierarchy of the semantic blocks for all the web pages; and fusing the hierarchy of the semantic blocks with the hierarchy of the web pages to generate a coordinated hierarchy. In one embodiment, the nodes on the generated coordinated hierarchy are then mapped into corresponding objects to generate the coordinated object hierarchy. Compared with the prior arts, the object hierarchy building systems and methods according to the present invention can build the object hierarchy in a more accurate and efficient way by fusing the inter-page analysis result and the intra-page analysis result. | 12-31-2009 |
20100114855 | METHOD AND SYSTEM FOR AUTOMATIC OBJECTS CLASSIFICATION - The present invention provides a method and system for automatic objects classification. The method comprises: acquiring a set of objects; classifying the objects based on query log to generate a first classification result; classifying the objects based on ontological information to generate a second classification result; and semantically fusing the first and second classification results to generate a final classification result. According to the present invention, compared with the prior arts, by semantically fusing the query log-based classification result and the ontology-based classification result, the accuracy and user-friendness of the object classification can be improved. | 05-06-2010 |
20150322380 | CLEANING COMPOSITIONS COMPRISING ALKOXYLATED POLYALKYLENEIMINE, ORGANOMODIFIED SILICONE AND SILIXANE-BASED DILUENT - The present invention relates to cleaning compositions with improved rinse suds profile, which comprise an alkoxylated polyalkyleneimine, an organomodified silicone and a siloxane-based diluent. | 11-12-2015 |
20150372018 | ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF AND DISPLAY PANEL - The invention provides an array substrate, a method for manufacturing the array substrate, and a display panel, the array substrate includes a plurality of thin film transistors, and the method includes: S1. preparing a base substrate on which sources and drains of the thin film transistors are formed; S2. forming an insulation layer on the base substrate such that the insulation layer includes spacer regions and a plurality of strip-shaped electrode regions, and every two adjacent strip-shaped electrode regions are separated from each other by the spacer region; S3. forming a spacer layer on the spacer regions of the insulation layer; S4. forming a pattern including strip-shaped electrodes on the strip-shaped electrode regions of the insulation layer; S5. peeling off the spacer layer on the spacer region. The invention can prevent every two adjacent strip-shaped electrodes from interconnecting due to etching residues, so as to improve product performance. | 12-24-2015 |
20160060582 | METHOD OF LAUNDERING FABRIC - The present invention relates to a method of laundering fabric using a laundry washing liquor containing a relatively low Through-The-Wash (TTW) dosage of a diphenyl ether anti-microbial agent. Such relatively low TTW ranges from about 0.25 to about 1 ppm, but it surprisingly and unexpectedly exhibits antimicrobial effect that is comparable with higher TTW dosage. The present invention also relates to anti-microbial laundry detergent compositions designed for delivering, or laundry washing liquors that contain, such a low TTW dosage of the diphenyl ether anti-microbial agent. | 03-03-2016 |
Patent application number | Description | Published |
20110143493 | METHOD OF MAKING PHOTOVOLTAIC CELL - Methods of making a photovoltaic (PV) cell are disclosed. The methods comprise at least the steps of, providing a first component comprising a cadmium telluride (CdTe) layer comprising an interfacial region, and subjecting the first component to a functionalizing treatment in the presence of a material comprising copper. | 06-16-2011 |
20120103261 | APPARATUS AND SYSTEMS FOR INTERMIXING CADMIUM SULFIDE LAYERS AND CADMIUM TELLURIDE LAYERS FOR THIN FILM PHOTOVOLTAIC DEVICES - An apparatus for sequential deposition of an intermixed thin film layer and a sublimated source material on a photovoltaic (PV) module substrate is provided, along with associated processes. The process can include introducing a substrate into a deposition chamber, wherein a window layer (e.g., a cadmium sulfide layer) is on a surface of the substrate. A sulfur-containing gas can be supplied to the deposition chamber. In addition, a source vapor can be supplied to the deposition chamber, wherein the source material comprises cadmium telluride. The sulfur-containing gas and the source vapor can be present within the deposition chamber to form an intermixed layer on the window layer. In one particular embodiment, for example, the intermixed layer generally can have an increasing tellurium concentration and decreasing sulfur concentration extending away from the window layer. | 05-03-2012 |
20120325298 | METHODS OF MAKING PHOTOVOLTAIC DEVICES AND PHOTOVOLTAIC DEVICES - One aspect of the present invention includes method of making a photovoltaic device. The method includes disposing an absorber layer on a window layer, wherein the absorber layer includes a first region and a second region. The method includes disposing the first region adjacent to the window layer in a first environment including oxygen at a first partial pressure; and disposing the second region on the first region in a second environment including oxygen at a second partial pressure, wherein the first partial pressure is greater than the second partial pressure. One aspect of the present invention includes a photovoltaic device. | 12-27-2012 |
20140083505 | VARYING CADMIUM TELLURIDE GROWTH TEMPERATURE DURING DEPOSITION TO INCREASE SOLAR CELL RELIABILITY - A method for forming thin films or layers of cadmium telluride (CdTe) for use in photovoltaic modules or solar cells. The method includes varying the substrate temperature during the growth of the CdTe layer by preheating a substrate (e.g., a substrate with a cadmium sulfide (CdS) heterojunction or layer) suspended over a CdTe source to remove moisture to a relatively low preheat temperature. Then, the method includes directly heating only the CdTe source, which in turn indirectly heats the substrate upon which the CdTe is deposited. The method improves the resulting CdTe solar cell reliability. The resulting microstructure exhibits a distinct grain size distribution such that the initial region is composed of smaller grains than the bulk region portion of the deposited CdTe. Resulting devices exhibit a behavior suggesting a more n-like CdTe material near the CdS heterojunction than devices grown with substrate temperatures held constant during CdTe deposition. | 03-27-2014 |
20150285761 | SYSTEM AND METHOD FOR FLAT PANEL DETECTOR GEL AND BLOT IMAGING - A system and method for generating a digital image in fluorescence gel imaging is disclosed. The method includes providing a gel sample and placing the gel sample on a flat panel detector having array of photodiodes and transistors that collect light generated from the gel sample. The gel sample is illuminated using a light source integrated into the flat panel imaging system and light emitted by the gel sample responsive to an excitation of the gel sample by light provided by the light source is then collected, with the light emitted by the gel sample being collected by the array of photodiodes of the flat panel detector and converted to electric charges to generate light data. The light data is then processed to generate a digital image of the gel sample. | 10-08-2015 |
20150285762 | SYSTEM AND METHOD FOR FLAT PANEL DETECTOR GEL AND BLOT IMAGING - A system and method for generating a digital image in fluorescence gel imaging is disclosed. The method includes providing a gel sample and placing the gel sample on a flat panel detector having array of photodiodes and transistors that collect light generated from the gel sample. The gel sample is illuminated using a light source integrated into the flat panel imaging system and light emitted by the gel sample responsive to an excitation of the gel sample by light provided by the light source is then collected, with the light emitted by the gel sample being collected by the array of photodiodes of the flat panel detector and converted to electric charges to generate light data. The light data is then processed to generate a digital image of the gel sample. | 10-08-2015 |
20150285763 | SYSTEM AND METHOD FOR FLAT PANEL DETECTOR GEL AND BLOT IMAGING - A system and method for generating a digital image in fluorescence gel imaging is disclosed. The method includes providing a gel sample and placing the gel sample on a flat panel detector having array of photodiodes and transistors that collect light generated from the gel sample. The gel sample is illuminated using a light source integrated into the flat panel imaging system and light emitted by the gel sample responsive to an excitation of the gel sample by light provided by the light source is then collected, with the light emitted by the gel sample being collected by the array of photodiodes of the flat panel detector and converted to electric charges to generate light data. The light data is then processed to generate a digital image of the gel sample. | 10-08-2015 |
20160034745 | HIGH SENSITIVITY FLAT PANEL MICROBIOLOGY DETECTION AND ENUMERATION SYSTEM - A flat panel imaging system for imaging cells provided on a cell medium is disclosed. The system includes a housing having a base portion and a lid that collectively form a closed environment to exclude external sources of light, and a flat panel detector encased in the base portion and having an array of pixels each including a photodiode and transistor. The system also includes a first light source that illuminates cells on the cell medium to excite at least a portion of the cells and cause those cells to generate photons that are captured by the array of pixels and a second light source to illuminate cells on the cell medium with a light different from the light from the first light source and that provides for a capturing of photons representative of photons transmitted through the cells on the cell medium. | 02-04-2016 |
Patent application number | Description | Published |
20130253051 | CONTROLLED CHEMICAL RELEASE OF HYDROGEN SULFIDE - Agents of formula: where R1 and R2 vary independently and are acyl, sulfonyl, phosphoryl, alkyl, substituted alkyl, halogen, aryl, arylalkyl, substituted aryl, heteroaryl, alkenyl, substituted alkenyl, alkynyl, substituted alkynyl, cycloalkyl, heterocycle, or heteroatoms; and R3 is H or a member of a ring structure which includes R2, are provided; as are agents of formula: where R1, R2 and R3 vary independently and: R1=OH, OR′, NHR′, NR′R″ (with R′ R″=alkyl, aryl, heteroaryl, etc); R | 09-26-2013 |
Patent application number | Description | Published |
20130146511 | JIG ASSEMBLY FOR ORIENTING, SORTING AND SELECTING FASTENER NUTS - A jig assembly for selecting and presenting fastener nuts in the correct orientation, each fastener nut including a nut cap and an assembling portion formed on an end of the fastener nut. The diameter of the nut cap is larger than the diameter of the assembling portion. The jig assembly includes an electric cabinet, a jig bracket, a feed container, and a sorting tray. The feed container includes a selector with an opening. The width of the opening is equal to the height of the fastener nut, the first sidewall of the selector forms a plurality of restricting protrusions, and each two adjacent restricting protrusions cooperatively define a restricting groove therebetween. The width of each restricting groove is equal to the diameter of the assembling portion, thus only fastener nuts in the correct orientation are capable of passing through the selector to be collected in the sorting tray. | 06-13-2013 |
20130300492 | SWITCHING POWER CAPABLE OF AVOIDING COUPLING EFFECTS - A switching power capable of avoiding coupling effects is provided. The switching power comprises a driving loop. The driving loop comprises the substrate end and the gate end of a power Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and a controlling gate, and the controlling gate is connected to the gate end of the power MOSFET and the substrate end of the power MOSFET is connected to the controlling gate. The switching power provided by the present can avoid the coupling effect of the driving loop and the power stage loop at the common source pin, thereby reducing the switching power losses and improving the efficiency of the switching power. | 11-14-2013 |
20140002304 | METHOD AND APPARATUS FOR LOCATING TERMINAL DEVICE | 01-02-2014 |
20140132235 | CIRCUIT BOARD AND POWER SOURCE MANAGEMENT SYSTEM OF CIRCUIT BOARD - A power source management system of a circuit board that comprises: a processor, comprising a core voltage input terminal; and a core voltage feedback terminal; and a voltage regulating member, comprising a setting terminal with a fixed reference voltage provided thereto; a detecting terminal connected to the core voltage feedback terminal to detect a feedback core voltage from the core voltage feedback terminal; and a core voltage output terminal connected to the core voltage input terminal to provide a core voltage thereto, wherein the core voltage is regulated by the voltage regulating member based on the feedback core voltage, such that the feedback core voltage is equal to the fixed reference voltage, wherein an offset voltage equal to a difference between a desired core voltage of the processor and the fixed reference voltage is provided between the core voltage input terminal and the core voltage feedback terminal by the processor. | 05-15-2014 |
20140136862 | PROCESSOR AND CIRCUIT BOARD INCLUDING THE PROCESSOR - The present invention provides a processor and a circuit board including the processor. The processor includes a data processing unit, and an external power supply component that is coupled to the data processing unit; wherein the data processing unit includes a power management unit that is integrated into the data processing unit, and the power management unit is used for performing power management for the data processing unit; and the power management unit further includes a pulse signal output terminal which is used for outputting a pulse-width modulation signal, and the pulse-width modulation signal controls the external power supply component to supply a stable operating voltage to the data processing unit. The present invention provides a processor with the improved performance, the improved stability and the simplified structure. | 05-15-2014 |
20140191735 | DIGITAL DUTY CYCLE CONTROLLER FOR A SWITCHING MODE POWER SUPPLY - Disclosed are methods, devices, and systems to digitally control a duty cycle of a switching mode power supply. In one embodiment, a method comprises calculating a base duty cycle using a power management unit of a high-speed processing unit, calculating a dynamic offset duty cycle using the power management unit to apply a transfer function to a sampled feedback voltage signal, and adding the base duty cycle to the dynamic offset duty cycle to obtain a duty cycle of the switching mode power supply. A system comprises a switching mode power supply, a power management unit, a voltage sensor, and an analog to digital converter all embedded within a high-speed processing unit, and a pulse-width modulator coupled between the switching mode power supply and the high-speed processing unit to modulate the duty cycle of the switching mode power supply. | 07-10-2014 |
20140327643 | DISPLAY PANEL PROTECTION WITH OVERPRESSURE SENSOR ON MOBILE DEVICE - An overpressure sensing mechanism protecting display panels on mobile computing devices from inadvertent external overpressures. The sensing mechanism comprises a pressure sensor coupled to a display panel and operable to trigger a warning alarm to a user upon detection of an overpressure exerted on the touchscreen. The user receiving the warning alarm may withdraw the overpressure promptly and prevent the display panel from being damaged. | 11-06-2014 |
20150058678 | METHOD AND SYSTEM FOR TESTING A MEMORY - A method and system for testing a memory is provided in the present invention. The method includes the following steps. Each of at least one address bit to be tested of the memory is set to a fixed value. Current test data is written into memory unit(s) of the memory which the set address bit(s) correspond(s) to. Current read back data is read from the memory unit(s) which the set address bit(s) correspond(s) to. The current test data is compared with the current read back data. It is judged whether there is any signal integrity problem in unset address bit(s) of the memory according to the comparison result of the current test data and the current read back data, in order to determine fault address bit(s). The method and system for testing a memory provided by the present invention may determine fault address bit(s) of the memory simply and quickly. | 02-26-2015 |
20160088548 | Circuit, Method, and Related Apparatus for Avoiding Channel Interference - A circuit for avoiding channel interference, including a Wireless Fidelity (Wi-Fi) chip and at least one first single-pole multi-throw switch, where a movable end of the first single-pole multi-throw switch is connected to a signal transmit pin of the Wi-Fi chip; one non-movable end of the first single-pole multi-throw switch is connected to a first signal transmit tributary while another is connected to a second signal transmit tributary; and when the Wi-Fi chip determines that a first channel and a second channel interfere with each other, the movable end of the first single-pole multi-throw switch is controlled to connect to the second non-movable end of the first single-pole multi-throw switch, where the first channel is a wireless local area network channel, and the second channel is different from the wireless local area network channel. | 03-24-2016 |
Patent application number | Description | Published |
20130254499 | INTERLEAVING AND DE-INTERLEAVING METHOD, INTERLEAVER AND DE-INTERLEAVER - The present invention relates to an interleaving and de-interleaving method, an interleaver and a de-interleaver. The interleaving method includes: receiving N×M frames of data, and sequentially storing, with each frame as a unit, the N×M frames of data in storage space indicated by N×M addresses of a first storage unit; transferring the data stored in the storage space indicated by an ((X−1)×M+Y+1) | 09-26-2013 |
20130254603 | DECODING METHOD AND DECODING DEVICE - Embodiments of the present invention provide a decoding method and a decoding device. The method includes: performing iterative decoding on a multidimensional code to obtain incorrigible code words; determining locations of error bits in the incorrigible code words that are obtained by performing the iterative decoding on the multidimensional code, where the locations of error bits in the incorrigible code words are multidimensional coordinate locations of the error bits in the multidimensional code; correcting error bits of a part of the incorrigible code words in the multidimensional code according to the determined locations of the error bits in the incorrigible code words; and after the error bits of a part of the incorrigible code words in the multidimensional code are corrected, performing iterative decoding on the multidimensional code The embodiments of the present invention are applicable to the field of decoding technologies. | 09-26-2013 |
20150160991 | METHOD AND DEVICE FOR PERFORMANCE EVALUATION OF FORWARD ERROR CORRECTION CODES - The invention relates to a method for evaluating a performance of a forward error correction code used for coding a sequence of known transmit data symbols, the method comprising: receiving a sequence of receive data symbols responsive to a transmission of the known sequence of transmit data symbols over a communications channel, wherein the known sequence of transmit data symbols is transmitted over the communications channel without being coded by the forward error correction code; providing a sequence of extended parity bits based on the known transmit data symbols and based on a parity check matrix of the forward error correction code; and providing the performance of the forward error correction code based on the sequence of extended parity check bits. | 06-11-2015 |