Patent application number | Description | Published |
20080220007 | EHRLICHIA CANIS GENES AND VACCINES - This invention provides the sequence of 5,299 nucleotides from the | 09-11-2008 |
20090099083 | COMPOSITIONS FOR ELICITING AN IMMUNE RESPONSE AGAINST MYCOBACTERIUM AVIUM SUBSPECIES PARATUBERCULOSIS - Provided are compositions and methods for stimulating an immune response against | 04-16-2009 |
20100034855 | Compositions For Eliciting An Immune Response Against Mycobacterium Avium Subspecies Paratuberculosis - The invention provides compositions and method for stimulating an immunological response against | 02-11-2010 |
20110110966 | NOVEL IMMUNOGENIC PROTEINS OF LEPTOSPIRA - The invention provides novel immunogenic proteins LigA and LigB from | 05-12-2011 |
20120100143 | IMMUNOGENIC PROTEINS FROM GENOME-DERIVED OUTER MEMBRANE OF LEPTOSPIRA AND COMPOSITIONS AND METHODS BASED THEREON - outer membrane proteins (OMPs) LP1454, LP1118, LP1939, MCEII, CADF-like1, CADF-like2, CADF-like3, Lp0022, Lp1499, Lp4337, Lp328 or L21 are provided. The OMPS can be used as tools for developing effective vaccines or diagnostic methods for leptospirosis. Expression vectors for the OMP genes are further provided. The antigenic properties of the | 04-26-2012 |
20130183331 | IMMUNOGENIC PROTEINS FROM GENOME-DERIVED OUTER MEMBRANE OF LEPTOSPIRA AND COMPOSITIONS AND METHODS BASED THEREON - outer membrane proteins (OMPs) LP1454, LP1118, LP1939, MCEII, CADF-like1, CADF-like2, CADF-like3, Lp0022, Lp1499, Lp4337, Lp328 or L21 are provided. The OMPS can be used as tools for developing effective vaccines or diagnostic methods for leptospirosis. Expression vectors for the OMP genes are further provided. The antigenic properties of the | 07-18-2013 |
20140186860 | NOVEL IMMUNOGENIC PROTEINS OF LEPTOSPIRA - The invention provides novel immunogenic proteins LigA and LigB from | 07-03-2014 |
20160103128 | NOVEL IMMUNOGENIC PROTEINS OF LEPTOSPIRA - The invention provides novel immunogenic proteins LigA and LigB from | 04-14-2016 |
Patent application number | Description | Published |
20100164766 | DAC Variation-Tracking Calibration - A method of calibrating a digital-to-analog converter (DAC) is provided. The DAC includes a least-significant bit (LSB) block, and dummy LSB block adjacent to the LSB block. The DAC has a most-significant bit (MSB) block, which includes MSB thermometer macros. The method includes measuring the dummy LSB block to obtain a dummy LSB sum; and calibrating the MSB block so that each of the MSB thermometer macros provides a substantially same current as the dummy LSB sum. | 07-01-2010 |
20110012763 | Background Calibration of Analog-to-Digital Converters - A method of operating an analog-to-digital converter (ADC) includes providing the ADC including a plurality of stages, each including an operational amplifier, and a first capacitor and a second capacitor including a first input end and a second input end, respectively. Each of the first capacitor and the second capacitor includes an additional end connected to a same input of the operational amplifier. The method further includes performing a plurality of signal conversions. Each of the signal conversions includes, in an amplifying phase of one of the plurality of stages, applying a first voltage to the first input end of the one of the plurality of stages, randomly selecting a second voltage from two different voltages; and applying the second voltage to the second input end of the one of the plurality of stages. | 01-20-2011 |
20120212359 | ADC Calibration Apparatus - An analog-to-digital (ADC) calibration apparatus comprises a calibration buffer, a comparator and a digital calibration block. Each reference voltage is sent to a track-and-hold amplifier as well as the calibration buffer. The comparator compares the output from the track-and-hold amplifier and the output from the calibration buffer and generates a binary number. Based upon a successive approximation method, the digital calibration block finds a correction voltage for ADC offset and nonlinearity compensation. By employing the ADC calibration apparatus, each reference voltage can be calibrated and the corresponding correction voltage can be used to modify the reference voltage during an ADC process. | 08-23-2012 |
Patent application number | Description | Published |
20110037631 | DAC CALIBRATION - Mechanisms to calibrate a digital to analog converter (DAC) of an SDM (sigma delta modulator) are disclosed. An extra DAC element in addition to the DAC is used to function in place of a DAC element under calibration. A signal (e.g., a random sequence of −1 and +1) is injected to the DAC element under calibration, and the estimated error and compensation are acquired. | 02-17-2011 |
20110037632 | ADC CALIBRATION - An analog to digital convertor (ADC) includes a plurality of comparators one of which is referred to as an auxiliary comparator (e.g., comparator “Aux”). This comparator Aux is calibrated in the background while other comparators function as usual. Once having been calibrated, the comparator Aux replaces a first comparator, which becomes a new comparator Aux, is calibrated, and replaces the second comparator. This second comparator becomes the new comparator Aux, is calibrated, and replaces the third comparator, etc., until all comparators are calibrated. In effect, at any one point in time, a comparator may be calibrated as desire while other comparators and thus the ADC are operating as usual. | 02-17-2011 |
20120133536 | DAC CALIBRATION - Mechanisms to calibrate a digital to analog converter (DAC) of an SDM (sigma delta modulator) are disclosed. An extra DAC element in addition to the DAC is used to function in place of a DAC element under calibration. A signal (e.g., a random sequence of −1 and +1) is injected to the DAC element under calibration, and the estimated error and compensation are acquired. | 05-31-2012 |
20120212361 | SWITCHED-CAPACITOR CIRCUIT WITH LOW SIGNAL DEGRADATION - A switched-capacitor circuit is disclosed. The switched-capacitor circuit includes a comparator having a first and second input, a first and second sampling capacitor, and a first and second switching circuitry. The first switching circuitry charges the first and second sampling capacitor with an input signal. The second switching circuitry selectively couples the first sampling capacitor with a reference voltage and selectively couples the second sampling capacitor and the first and second input of the comparator to a common voltage. The comparator performs a compare of the input signals against the reference voltage, and outputs a signal. | 08-23-2012 |
20120249351 | ADC CALIBRATION - An analog-to-digital converter (ADC) including a plurality of comparators connected to the ADC. The ADC further includes a first pair of terminals and a second pair of terminals connected to each of the plurality of comparators. The ADC further includes a first pair of switches coupled to each of the first pair of terminals and a second pair of switches coupled to each of the second pair of terminals, where the first and second pair of switches are configured to alternate a corresponding comparator between normal operation and a calibration configuration. Comparators other than the corresponding comparator are configured for normal operation if the corresponding comparator is configured to be calibrated. | 10-04-2012 |
20130015876 | APPARATUS AND METHOD FOR MEASURING DEGRADATION OF CMOS VLSI ELEMENTSAANM LAI; Fang-Shi JordanAACI Chia YiAACO TWAAGP LAI; Fang-Shi Jordan Chia Yi TWAANM LU; Chih-ChengAACI Tainan CityAACO TWAAGP LU; Chih-Cheng Tainan City TWAANM LIN; Yung-FuAACI Hsinchu CityAACO TWAAGP LIN; Yung-Fu Hsinchu City TWAANM HSUEH; Hsu-FengAACI Tainan CityAACO TWAAGP HSUEH; Hsu-Feng Tainan City TWAANM CHANG; Chin-HaoAACI Hsinchu CityAACO TWAAGP CHANG; Chin-Hao Hsinchu City TWAANM WENG; Cheng YenAACI Hsinchu CityAACO TWAAGP WENG; Cheng Yen Hsinchu City TWAANM MHALA; Manoj M.AACI HsinchuAACO TWAAGP MHALA; Manoj M. Hsinchu TW - The reliability of an integrated circuit is inferred from the operational characteristics of sample metal oxide semiconductor (MOS) devices switchably coupled to drain/source bias and gate input voltages that are nominal, versus voltage and current conditions that elevate stress and cause temporary or permanent degradation, e.g., hot carrier injection (HCI), bias temperature instability (BTI, NBTI, PBTI), time dependent dielectric breakdown (TDDB). The MOS devices under test (preferably both PMOS and NMOS devices tested concurrently or in turn) are configured as current sources in the supply of power to a ring oscillator having cascaded inverter stages, thereby varying the oscillator frequency as a measure of the effects of stress on the devices under test, but without elevating the stress applied to the inverter stages. | 01-17-2013 |
20130141260 | PIPELINE ANALOG-TO-DIGITAL CONVERTER - A pipelined ADC includes a first, second, and third pairs of comparators. The first pair of comparators compare an input voltage to a first positive reference voltage and to a first negative reference voltage. The second pair of comparators compare the input voltage to a second positive reference voltage and to a second negative reference voltage. Each comparator of the first and second pairs of comparators outputs a digital signal to an encoder. A third pair of comparators compares the input voltage to a third positive reference voltage and to a third negative reference voltage, and a comparator compares the input voltage to ground. The comparator and each comparator of the third pair of comparators is configured to output respective digital signals to an encoder. A multiplying digital-to-analog converter outputs a voltage based on the input voltage, an output from the encoder, and an output of the random number generator. | 06-06-2013 |
20150097710 | ADC CALIBRATION - An analog-to-digital converter (ADC) includes a plurality of comparators connected to the ADC. The ADC further includes a plurality of switches, wherein switches connected to a corresponding comparator of the plurality of comparators are configured to alternate the corresponding comparator between normal operation and a calibration configuration. The ADC further includes at least one comparator of the plurality of comparators other than the corresponding comparator is configured for normal operation if the corresponding comparator is configured for calibration. | 04-09-2015 |
Patent application number | Description | Published |
20110227105 | Multi-Layer LED Array Engine - A multi-layer LED array engine is provided. The multi-layer LED array engine includes a base plate frame, a molded platform, two lead frames, a lighting element, a dome, a protection layer, and a phosphorous layer. The molded platform is disposed on and secured to the base plate frame. The two lead frames are combined with two lead frame grooves of the base plate frame. The lighting element is disposed on a lighting area of the base plate frame. The protection layer is provided on the lighting element, and the phosphorous layer is provided on the protection layer. The dome is secured to the molded platform for covering the molded platform and the lighting element. | 09-22-2011 |
20120074837 | OPTICAL LENS HAVING FLUORESCENT LAYER ADAPTED FOR LED PACKAGING STRUCTURE - An optical lens having a fluorescent layer is provided. The optical lens is adapted for being employed in an LED packaging structure. The optical lens includes a substrate, at least one lens body, a lens shade, and a packaging member. The substrate is positioned at a bottommost side of the packaging structure, and the lens shade is positioned at a topmost side of the packaging structure. The lens body is positioned over the substrate and beneath the lens shade. A plurality of light emitting units are disposed on the substrate. The packaging member is adapted for packaging the substrate and the lens shade. The lens body is secured by the packing member so as to be positioned over the light emitting units. The lens body includes a fluorescent layer buried inside the lens body, and the lens body is positioned apart from the light emitting units for a certain distance. | 03-29-2012 |
20120133268 | AIRTIGHT MULTI-LAYER ARRAY TYPE LED - An airtight multi-layer array type LED is disclosed, which comprises a metal substrate with an airtight metal frame formed thereon, and the metal substrate is integrally formed with the airtight metal frame, and an airtight sealing frame slot is formed around the upper surface of the airtight metal frame, the airtight metal frame is installed with two sets of sealing through hole pairs accommodating the lead frames. The interior of the airtight metal frame can be installed with packaging materials or optical components. The sealing holes are sealed with a glass or ceramic material. A fluorescent layer is formed on a silica gel layer, wherein the fluorescent layer can also be installed inside a silica glass package cover. The silica glass package cover is installed on the top surface of the airtight metal frame, and the silica glass package cover is engaged and sealed to a sealing rack. Nitrogen is filled in a space defined between the silica glass package cover and the fluorescent layer, so that moisture is prevented from permeating through the airtight metal frame and a dice protection layer. As such, a sealed-type LED packaging structure is formed and is suitable to be used in extreme or severe environments. | 05-31-2012 |
20120186077 | Method For Packaging Airtight Multi-Layer Array Type LED - A method for packaging an airtight multi-layer array type LED is disclosed. The method includes: integrally forming a metal substrate with an airtight metal frame surrounding an accommodating space; forming a light outlet platform surrounding a light outlet opening on a bottom of the accommodating space; forming two sets of sealing through hole pairs in the airtight metal frame, wherein each set of the sealing through hole pairs has one lead frame inserted therethrough, and all interstitial space in the two sets of the sealing through hole pairs is completely sealed with a sealing material; disposing the optical units and optical components in the accommodating space; sequentially forming a dice protection layer, a fluorescent layer, and a silicone layer on the LED dices; and installing an optical glass cover on the top surface of the airtight metal frame to seal the packaging structure of the present invention. | 07-26-2012 |
20120186726 | Method Of Filling And Sealing A Fluorescent Layer In A Slot Space Defined By Two Optical Lenses And A Partition Ring - A method of filling and sealing a fluorescent layer in a slot space defined by two optical lenses and a partition ring is disclosed, in which a slot space is defined by two optical glasses and a partition frame having a partition ring on the inner wall surface. The partition frame is installed with two slots diametrically opposite to each other, and the slot space is evacuated to allow filling of a fluorescent material, and then the two slots are sealed so that the moisture is prevented from permeating into the fluorescent layer, and thus the optical performance can be maintained over a long period. | 07-26-2012 |
20120218627 | OPTICAL LENS ASSEMBLY HAVING FLUORESCENT LAYER - An optical lens assembly having a fluorescent layer is disclosed, which includes a partition frame with a partition ring protruding inwardly from an inner wall surface of the partition frame, two optical lenses, and a fluorescent layer, wherein a slot space is defined by the two optical lenses and the partition ring of the partition frame, and the fluorescent layer is accommodated within the slot space. The top optical lens can be a flat slab lens, or a convex lens. When the optical lens assembly having a fluorescent layer is used in the optical device, the moisture can be prevented from entering the fluorescent layer, and thus the optical performance of the fluorescent layer can be maintained over a long period. | 08-30-2012 |
20130126913 | THIN MULTI-LAYER LED ARRAY ENGINE - A thin multi-layer LED array engine is provided, which includes a substrate having a phosphor layer and a silica gel protection layer formed thereon. The phosphor layer is disposed on LED dices and makes direct contact with the substrate, and the silica gel protection layer is disposed on the phosphor layer. The LED dices are covered with the phosphor layer, and thereby the phosphor particles in the phosphor layer can be uniformly dispersed around the LED dices, so that the narrow color temperature distribution can be achieved. Furthermore, the phosphor layer makes direct contacts with the substrate, and thereby heat generated in the phosphor layer can be effectively dissipated through the substrate, and thereby the reliability of the optical components can be increased. | 05-23-2013 |
20130187175 | MULTI-LAYER ARRAY TYPE LED DEVICE - A multi-layer array type LED device is provided, which includes a substrate, an encapsulation body, two lead frames, a plurality of LED dices, and a set of optical lens. The outer circumferential edge and the upper and lower periphery of the substrate are completely encapsulated by the encapsulation body so that the multi-layer array type LED device can be tightly packaged. In the present invention, a fluorescent layer is disposed between an optical grease layer and a silica gel protection layer, and thereby the fluorescent layer is protected, and is capable of preventing moisture from permeating therein. On the other hand, in the present invention, the reflection coefficient of the optical grease layer is at least larger than a certain value so that the probability of the light emitted out of the optical chamber can be increased. | 07-25-2013 |
20130223061 | MULTI-LAYER ARRAY TYPE LED DEVICE HAVING A MULTI-LAYER HEAT DISSIPATION STRUCTURE - A multi-layer array type LED device having a multi-layer heat dissipation structure includes a heat dissipation seat, an optical module, a housing, a power supply module, a wireless transmission module, a diffusion cover and a lamp head. In the present invention, the heat-generating components include the optical module, the power supply module and the wireless transmission module, and the heat-generating components are separately installed so that the heat accumulation effect can be decreased. In the present invention, the heat dissipation seat is used together with the housing having a plurality of the heat dissipation holes. The heat dissipation seat having excellent heat conductivity is used for rapidly absorbing heat and transferring it to the surrounding environment, and the surrounding air can be introduced into the housing via the heat dissipation holes for further increasing the heat dissipation efficiency. | 08-29-2013 |
20130235574 | INTEGRALLY FORMED MULTI-LAYER LIGHT-EMITTING DEVICE - An integrally formed multi-layer light-emitting device is provided, which includes a seat, a plurality of light-emitting elements, and two lead frames. The seat is integrally formed in such a manner that the light-emitting elements can fit in the chamber which is formed on the top portion of the central main body. The seat is made of metal, and thereby the seat can effectively absorb heat from the light-emitting elements, and rapidly transmit it to the surrounding environment. Therefore, the packing module is not needed to be used in the present invention so that the consumption of the package material is reduced, and the manufacturing process is simplified. | 09-12-2013 |
20130283604 | METHOD FOR MANUFACTURING INTEGRALLY FORMED MULTI-LAYER LIGHT-EMITTING DEVICE - A method for manufacturing an integrally formed multi-layer light-emitting device is provided, in which a seat is integrally formed in such a manner that the light-emitting elements can be directly disposed in the chamber. The lens mask is used to seal the light-emitting elements in the chamber of the seat so that some packaging steps can be omitted, and the manufacturing process is simplified. The seat is made of metal having good thermal conductivity instead of plastic materials. The consumption of the package material is reduced, and the heat-dissipation efficiency is increased in the present invention. | 10-31-2013 |