Patent application number | Description | Published |
20090292935 | Method, System and Apparatus for Power Management of a Link Interconnect - A proposal for power management control of an interconnect structure based on power state transition control. The power state transition is based on generating early warning signals and an idle timeout value setting based on response time and detection of subsequent requests. | 11-26-2009 |
20090327611 | DOMAIN-BASED CACHE MANAGEMENT, INCLUDING DOMAIN EVENT BASED PRIORITY DEMOTION - Domain-based cache management methods and systems, including domain event based priority demotion (“EPD”). In EPD, priorities of cached data blocks are demoted upon one or more domain events, such as upon encoding of one or more macroblocks of a video frame. New data blocks may be written over lowest priority cached data blocks. New data blocks may initially be assigned a highest priority. Alternatively, or additionally, one or more new data blocks may initially be assigned one of a plurality of higher priorities based on domain-based information, such as a relative position of a requested data block within a video frame, and/or a relative direction associated with a requested data block. Domain-based cache management may be implemented with one or more other cache management techniques, such as least recently used techniques. Domain-based cache management may be implemented in associative caches, including set associative caches and fully associative caches, and may be implemented with indirect indexing. | 12-31-2009 |
20100191920 | Providing Address Range Coherency Capability To A Device - In one embodiment, the present invention includes a method for receiving a memory request from a device coupled to an input/output (IO) interconnect, accessing a mapping table associated with the IO interconnect to determine if an address range including an address of the memory request is coherent, and if so, sending the memory request and a coherency indicator to indicate the coherent state of data at the address, otherwise sending the memory request and the coherency indicator to indicate a non-coherent state. Other embodiments are described and claimed. | 07-29-2010 |
20100250889 | CONTROL OF ON-DIE SYSTEM FABRIC BLOCKS - Methods and apparatus for control of On-Die System Fabric (OSF) blocks are described. In one embodiment, a shadow address corresponding to a physical address may be stored in response to a user-level request and a logic circuitry (e.g., present in an OSF) may determine the physical address from the shadow address. Other embodiments are also disclosed. | 09-30-2010 |
20100318693 | Delegating A Poll Operation To Another Device - In one embodiment, the present invention includes a method for handling a registration message received from a host processor, where the registration message delegates a poll operation with respect to a device from the host processor to another component. Information from the message may be stored in a poll table, and the component may send a read request to poll the device and report a result of the poll to the host processor based on a state of the device. Other embodiments are described and claimed. | 12-16-2010 |
20100332788 | AUTOMATICALLY USING SUPERPAGES FOR STACK MEMORY ALLOCATION - In one embodiment, the present invention includes a page fault handler to create page table entries and TLB entries in response to a page fault, the page fault handler to determine if a page fault resulted from a stack access, to create a superpage table entry if the page fault did result from a stack access, and to create a TLB entry for the superpage. Other embodiments are described and claimed. | 12-30-2010 |
20110078536 | Using Motion Change Detection to Reduce Power Consumption of Display Systems - Image data, such as graphics, text, and video may be conveyed from a host to a remote display. In some cases, an analysis of successive frames may be undertaken to determine whether motion exists between those frames. In one embodiment, this motion detection may involve the use of an error correction code, such as a cyclic recovery check. This may enable a relatively efficient, low cost determination of whether motion is occurring. If motion is not occurring, motion estimation may be simplified in some cases and, in some cases, refreshing of the display may be curtailed, for example, using a local frame buffer associated with the display. | 03-31-2011 |
20110113198 | Selective searching in shared cache - The present invention discloses a method comprising: sending request for data to a memory controller; arranging the request for data by order of importance or priority; identifying a source of the request for data; if the source is an input/output device, masking off P ways in a cache; and allocating ways in filling the cache. The method further includes extending cache allocation logic to control a tag comparison operation by using a bit to provide a hint from IO devices that certain ways will not have requested data. | 05-12-2011 |
20110153926 | Controlling Access To A Cache Memory Using Privilege Level Information - In one embodiment, a cache memory includes entries each to store a ring level identifier, which may indicate a privilege level of information stored in the entry. This identifier may be used in performing read accesses to the cache memory. As an example, a logic coupled to the cache memory may filter an access to one or more ways of a selected set of the cache memory based at least in part on a current privilege level of a processor and the ring level identifier of the one or more ways. Other embodiments are described and claimed. | 06-23-2011 |
20110161595 | CACHE MEMORY POWER REDUCTION TECHNIQUES - Methods and apparatus to provide for power consumption reduction in memories (such as cache memories) are described. In one embodiment, a virtual tag is used to determine whether to access a cache way. The virtual tag access and comparison may be performed earlier in the read pipeline than the actual tag access or comparison. In another embodiment, a speculative way hit may be used based on pre-ECC partial tag match to wake up a subset of data arrays. Other embodiments are also described. | 06-30-2011 |
20110235531 | Performance And Traffic Aware Heterogeneous Interconnection Network - In one embodiment, a method includes comparing an occupancy level of a buffer of a port of a router to a threshold, and controlling the port to operate at a first voltage and frequency based at least in part on the comparison, and at least one other port of the router is controlled to operate at a second voltage and frequency. Other embodiments are described and claimed. | 09-29-2011 |
20120191896 | CIRCUITRY TO SELECT, AT LEAST IN PART, AT LEAST ONE MEMORY - An embodiment may include circuitry to select, at least in part, from a plurality of memories, at least one memory to store data. The memories may be associated with respective processor cores. The circuitry may select, at least in part, the at least one memory based at least in part upon whether the data is included in at least one page that spans multiple memory lines that is to be processed by at least one of the processor cores. If the data is included in the at least one page, the circuitry may select, at least in part, the at least one memory, such that the at least one memory is proximate to the at least one of the processor cores. Many alternatives, variations, and modifications are possible. | 07-26-2012 |
20120284486 | CONTROL OF ON-DIE SYSTEM FABRIC BLOCKS - Methods and apparatus for control of On-Die System Fabric (OSF) blocks are described. In one embodiment, a shadow address corresponding to a physical address may be stored in response to a user-level request and a logic circuitry (e.g., present in an OSF) may determine the physical address from the shadow address. Other embodiments are also disclosed. | 11-08-2012 |
20130138843 | DELEGATING A POLL OPERATION TO ANOTHER DEVICE - In one embodiment, the present invention includes a method for handling a registration message received from a host processor, where the registration message delegates a poll operation with respect to a device from the host processor to another component. Information from the message may be stored in a poll table, and the component may send a read request to poll the device and report a result of the poll to the host processor based on a state of the device. Other embodiments are described and claimed. | 05-30-2013 |
20130326101 | INTERRUPT RETURN INSTRUCTION WITH EMBEDDED INTERRUPT SERVICE FUNCTIONALITY - An instruction pipeline implemented on a semiconductor chip is described. The semiconductor chip includes an execution unit having the following to execute an interrupt handling instruction. Storage circuitry to hold different sets of micro-ops where each set of micro-ops is to handle a different interrupt. First logic circuitry to execute a set of said sets of micro-ops to handle an interrupt that said set is designed for. Second logic circuitry to return program flow to an invoking program upon said first logic circuitry having handled said interrupt. | 12-05-2013 |
20140019736 | Embedded Branch Prediction Unit - In accordance with some embodiments of the present invention, a branch prediction unit for an embedded controller may be placed in association with the instruction fetch unit instead of the decode stage. In addition, the branch prediction unit may include no branch predictor. Also, the return address stack may be associated with the instruction decode stage and is structurally separate from the branch prediction unit. In some cases, this arrangement reduces the area of the branch prediction unit, as well as power consumption. | 01-16-2014 |
20140095799 | DIFFERENTIATING CACHE RELIABILITY TO REDUCE MINIMUM ON-DIE VOLTAGE - Systems and methods may provide for determining whether a memory access request is error-tolerant, and routing the memory access request to a reliable memory region if the memory access request is error-tolerant. Moreover, the memory access request may be routed to an unreliable memory region if the memory access request is error-tolerant. In one example, use of the unreliable memory region enables a reduction in the minimum operating voltage level for a die containing the reliable and unreliable memory regions. | 04-03-2014 |
20140223145 | Configurable Reduced Instruction Set Core - A processor may be built with cores that only execute some partial set of the instructions needed to be fully backwards compliant. Thus, in some embodiments power consumption may be reduced by providing partial cores that only execute certain instructions and not other instructions. The instructions not supported may be handled in other, more energy efficient ways, so that, the overall processor, including the partial core, may be fully backwards compliant. | 08-07-2014 |