| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438197000 |
Having insulated gate (e.g., IGFET, MISFET, MOSFET, etc.)
| 3498 |
| 438149000 |
On insulating substrate or layer (e.g., TFT, etc.)
| 922 |
| 438167000 |
Having Schottky gate (e.g., MESFET, HEMT, etc.)
| 110 |
| 438186000 |
Having junction gate (e.g., JFET, SIT, etc.)
| 55 |
| 438144000 |
Charge transfer device (e.g., CCD, etc.) | 1 |
| 20100197083 | FABRICATION METHODS OF THIN FILM TRANSISTOR SUBSTRATES - Methods for manufacturing thin film transistor arrays utilizing three steps of lithography and one step of laser ablation while the lithography procedure is used four to five times in conventional processes are disclosed. The use of the disclosed methods assists in improving throughput and saving of manufacturing cost. | 08-05-2010 |
| 438143000 |
Gettering of semiconductor substrate | 1 |
| 20090075434 | METHOD OF REMOVING DEFECTS FROM A DIELECTRIC MATERIAL IN A SEMICONDUCTOR - A method of forming a semiconductor device includes forming a high dielectric constant material over a semiconductor substrate, forming a conductive material over the high dielectric constant material, and performing an anneal in a non-oxidizing ambient using ultraviolet radiation to remove defects in the high dielectric constant material. Examples of a non-oxidizing ambient include for example nitrogen, deuterium, a deuterated forming gas (N | 03-19-2009 |
| Entries |
| Document | Title | Date |
|---|
| 20080280400 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A field effect transistor having a T-shaped gate electrode is formed on a GaAs substrate, and the T-shaped gate electrode of the field effect transistor is coated with a SiO | 11-13-2008 |
| 20080286908 | Method of Producing a Semiconductor Element in a Substrate - A method of producing a semiconductor element in a substrate includes forming a plurality of micro-cavities in a substrate, creating an amorphization of the substrate to form crystallographic defects and a doping of the substrate with doping atoms, depositing an amorphous layer on top of the substrate, and annealing the substrate, such that at least a part of the crystallographic defects is eliminated using the micro-cavities. The semiconductor element is formed using the doping atoms. | 11-20-2008 |
| 20080299710 | Carbon Nanotube Transistor Fabrication - During fabrication of single-walled carbon nanotube transistor devices, a porous template with numerous parallel pores is used to hold the single-walled carbon nanotubes. The porous template or porous structure may be anodized aluminum oxide or another material. A gate region may be provided one end or both ends of the porous structure. The gate electrode may be formed and extend into the porous structure. | 12-04-2008 |
| 20080318366 | METHOD FOR PRODUCING A SUPPORT FOR THE GROWTH OF LOCALISED ELONGATED NANOSTRUCTURES - The invention relates to a method for producing a support comprising nanoparticles ( | 12-25-2008 |
| 20090124050 | METHOD OF MANUFACTURING NANOWIRES PARALLEL TO THE SUPPORTING SUBSTRATE - A method of manufacturing at least one nanowire, the nanowire being parallel to its supporting substrate, the method comprising:
| 05-14-2009 |
| 20090148985 | Method for Fabricating a Nitride FET Including Passivation Layers - A method for fabricating a nitride-based FET device that provides reduced electron trapping and gate current leakage. The fabrication method provides a device that includes a relatively thick passivation layer to reduce traps caused by device processing and a thin passivation layer below the gate terminal to reduce gate current leakage. Semiconductor device layers are deposited on a substrate. A plurality of passivation layers are deposited on the semiconductor device layers, where at least two of the layers are made of a different dielectric material to provide an etch stop. One or more of the passivation layers can be removed using the interfaces between the layers as an etch stop so that the distance between the gate terminal and the semiconductor device layers can be tightly controlled, where the distance can be made very thin to increase device performance and reduce gate current leakage. | 06-11-2009 |
| 20090258463 | METHODS OF FABRICATING DIFFERENT THICKNESS SILICON-GERMANIUM LAYERS ON SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES FABRICATED THEREBY - Methods of fabricating semiconductor integrated circuit devices are provided. A substrate is provided with gate patterns formed on first and second regions. Spaces between gate patterns on the first region are narrower than spaces between gate patterns on the second region. Source/drain trenches are formed in the substrate on opposite sides of the gate patterns on the first and second regions. A first silicon-germanium (SiGe) epitaxial layer is formed that partially fills the source/drain trenches using a first silicon source gas. A second SiGe epitaxial layer is formed directly on the first SiGe epitaxial layer to further fill the source/drain trenches using a second silicon source gas that is different from the first silicon source gas. | 10-15-2009 |
| 20100029048 | Field Effect Semiconductor Diodes and Processing Techniques - Field effect semiconductor diodes and improved processing techniques for forming the field effect semiconductor diodes having semiconductor layers forming a source, a body and a drain of a field effect device, the semiconductor layers forming pedestals having an insulating layer and a gate on sides thereof vertically spanning the body and a part of the source and drain layers, and a conductive contact layer over the pedestals making electrical contact with the drain and the gate, the conductive layer being in contact with the body at least one position on each pedestal. The conductive layer may be in contact with the body through at least one opening in the source layer, or the source layer may be a discontinuous doped layer, the body layer extending between the discontinuous doped layer forming the source layer to be in electrical contact with the conductive layer. Other aspects and variations of the invention are disclosed. | 02-04-2010 |
| 20100035387 | Method for fabricating a CMOS-compatible MEMS device - A method for fabricating a CMOS-compatible MEMS device is disclosed. In particular, disclosed is a method of ordering the acts in the fabrication process of the two device types such that one device type will not be damaged by the fabrication process of the other device type. One aspect of the method involves first depositing a masking layer over a portion of a substrate layer to isolate areas for the formation of a second device type. The first device type is then fabricated on the unmasked portion of the substrate. A first device is then protected by depositing a masking layer over the first device. Next, a portion of the masking layer over the substrate is removed to expose areas to form a second device type. The second device type is then fabricated on the unmasked portion of the substrate. Finally, the masking layer over the first device type is removed. | 02-11-2010 |
| 20100041185 | METHOD OF PRODUCING A FIELD EFFECT TRANSISTOR ARRANGEMENT - A method of producing a field effect transistor arrangement. A substrate having a first crystal surface orientation is provided. A first layer is formed above a first portion of the substrate, the first layer having a second crystal surface orientation different from the first crystal surface orientation. A second layer is formed on at least a second portion of the substrate and adjacent to the first layer, the second layer having the first crystal surface orientation. A first buried oxide layer is formed between the substrate and the first layer. Micro-cavities are formed in the second layer and oxidizing the micro-cavities, thereby forming a second buried oxide layer between the substrate and the second layer. A first field effect transistor of a first conductivity type is formed in or on the first layer. A second field effect transistor of a second conductivity type is formed in or on the second layer. | 02-18-2010 |
| 20100167472 | IMPLANTATION SHADOWING EFFECT REDUCTION USING THERMAL BAKE PROCESS - A method of forming a resist feature includes forming a resist layer over a semiconductor body, and selectively exposing the resist layer. The method further includes performing a first bake of the selectively exposed resist layer, and developing the selectively exposed resist layer to form a resist feature having a corner edge associated therewith, thereby exposing a portion of the semiconductor body. A second bake of the developed selectively exposed resist layer is then performed, thereby rounding the corner edge of the resist feature. | 07-01-2010 |
| 20100167473 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SEMICONDUCTOR DEVICE - A semiconductor device and a fabrication method for the semiconductor device which can remove the sacrifice layer deposited on the semiconductor device surface in a short time and whose manufacturing yield can be improved are provided. The semiconductor device and the fabrication method for the semiconductor device includes a field effect transistor | 07-01-2010 |
| 20100261319 | N-type carrier enhancement in semiconductors - A method for generating n-type carriers in a semiconductor is disclosed. The method includes supplying a semiconductor having an atomic radius. Implanting an n-type dopant species into the semiconductor, which n-type dopant species has a dopant atomic radius. Implanting a compensating species into the semiconductor, which compensating species has a compensating atomic radius. Selecting the n-type dopant species and the compensating species in such manner that the size of the semiconductor atomic radius is inbetween the dopant atomic radius and the compensating atomic radius. A further method is disclosed for generating n-type carriers in germanium (Ge). The method includes setting a target concentration for the carriers, implanting a dose of an n-type dopant species into the Ge, and selecting the dose to correspond to a fraction of the target carrier concentration. Thermal annealing the Ge in such manner as to activate the n-type dopant species and to repair a least a portion of the implantation damage. Repeating the implantation and the thermal annealing until the target n-type carrier concentration has been reached. | 10-14-2010 |
| 20120309135 | Through-Substrate Vias - A method of etching through-substrate vias comprising depositing a layer of embossable material on a first side and a second side of a thin-film stack, the thin-film stack including a base substrate, embossing the embossable material deposited on the first side and the second side of the thin-film stack with a pattern, hardening the embossable material, and etching the first and second sides of the thin-film stack, the etching of the second side of the thin-film stack forming vias through the base substrate. | 12-06-2012 |
| 20140242759 | REDUCING WAFER DISTORTION THROUGH A HIGH CTE LAYER - Provided is a method of fabricating a semiconductor device. The method includes providing a silicon substrate having opposite first and second sides. At least one of the first and second sides includes a silicon ( | 08-28-2014 |
| 20150044825 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Two layers of protection films are formed such that a sheet resistance at a portion directly below the protection film is higher than that at a portion directly below the protection film. The protection films are formed, for example, of SiN film, as insulating films. The protection film is formed to be higher, for instance, in hydrogen concentration than the protection film so that the protection film is higher in refractive index the protection film. The protection film is formed to cover a gate electrode and extend to the vicinity of the gate electrode on an electron supplying layer. The protection film is formed on the entire surface to cover the protection film. According to this configuration, the gate leakage is significantly reduced by a relatively simple configuration to realize a highly-reliable compound semiconductor device achieving high voltage operation, high withstand voltage, and high output. | 02-12-2015 |
| 20150072480 | IMPLANT REGION DEFINITION - Among other things, one or more systems and techniques for defining one or more implant regions or for doping a semiconductor arrangement are provided. A first implant region is defined based upon a first implant mask overlaying a first active region of a semiconductor arrangement. A second implant region is defined based upon the first implant mask and a second implant mask overlaying a second active region of the semiconductor arrangement. A third implant region is defined based upon the second implant mask overlaying a third active region of the semiconductor arrangement. One or more doping processes are performed through the first implant mask and the second implant mask to dope the semiconductor arrangement. Because the first implant mask and the second implant mask overlap the second active region, doping area coverage is improved thus mitigating undesirable voltage threshold variations otherwise resulting from inadequate doping area coverage. | 03-12-2015 |
