03rd week of 2012 patent applcation highlights part 39 |
Patent application number | Title | Published |
20120015434 | EXPANSION OF NK CELLS AND THERAPEUTIC USES THEREOF - The present invention relates to novel methods for preferentially activating and expanding NK cells. The methods utilize the stimulatory effects of IL-15 and CD137 ligand to preferentially expand and activate NK cells in a mixed cell culture comprising NK cells. | 2012-01-19 |
20120015435 | PCSK9 ANTAGONISTS - The present invention provides antagonizing antibodies, antigen-binding portions thereof, and aptamers that bind to proprotein convertase subtilisin kexin type 9 (PCSK9). Also provided are antibodies directed to peptides, in which the antibodies bind to PCSK9. The invention further provides a method of obtaining such antibodies and antibody-encoding nucleic acid. The invention further relates to therapeutic methods for use of these antibodies and antigen-binding portions thereof to reduce LDL-cholesterol levels and/or for the treatment and/or prevention of cardiovascular disease, including treatment of hypercholesterolemia. | 2012-01-19 |
20120015436 | DEGRADED TPO AGONIST ANTIBODY - The invention relates to a modified antibody which contains two or more H chain V regions and two or more L chain V regions of monoclonal antibody and can transduce a signal into cells by crosslinking TPO receptor to thereby exert TPO agonist action. The modified antibody can be used as a TPO signal transduction agonist and, therefore, useful as a remedy for various diseases such as platelet-reduction-related blood diseases, thrombopenia following chemotherapy for cancer or leukemia, etc. | 2012-01-19 |
20120015437 | LONG-ACTING POLYPEPTIDES AND METHODS OF PRODUCING SAME - A polypeptide and polynucleotides encoding same comprising one carboxy-terminal peptide (CTP) of chorionic gonadotrophin attached to an amino terminus of a cytokine and two carboxy-terminal peptides (CTP) of chorionic gonadotrophin attached to a carboxy terminus of a cytokine are disclosed. Pharmaceutical compositions comprising the polypeptide and polynucleotides of the invention and methods of using same are also disclosed. | 2012-01-19 |
20120015438 | Mammallian cell culture process for protein production - The present invention describes methods and processes for the production of proteins, particularly glycoproteins, by animal cell or mammalian cell culture, preferably, but not limited to, fed-batch cell cultures. In one aspect, the methods comprise at least two temperature shifts performed during the culturing period, in which the temperature is lower at the end of the culturing period than at the time of initial cell culture. Throughout their duration, the culturing processes of the invention involving two or more downward shifts in temperature sustain a high viability of the cultured cells, and can yield an increased end titer of protein product, and a high quality of protein product, as determined, e.g., by sialic acid content of the produced protein. In another aspect, the methods comprise the delayed addition of polyanionic compound during the culturing period. The delayed addition of polyanionic compound sustains a high viability of the cultured cells, and can extend the growth phase, delay the onset of the death phase, and arrest the death phase. | 2012-01-19 |
20120015439 | METHOD FOR THE RECONSTRUCTION OF A TISSUE-ENGINEERED HUMAN CORNEAL ENDOTHELIUM - This invention relates to a method for the reconstruction of a tissue-engineered human corneal endothelium. Human corneal endothelial cells are cultured in vitro to logarithmic growth phase using 20% calf bovine serum-containing DMEM/F12 medium. Trypsin is used to digest epithelial layer of the freeze-dried human amniotic membrane in order to produce denuded human amniotic membrane as scaffold carriers. The scaffold carriers are tiled on the bottom of culture plate wells until they are dried and completely adhered to the bottom of wells. Human corneal endothelial cells at logarithmic growth phase are re-suspended in DMEM/F12 medium containing type-IV collagen and 20% calf bovine serum. Human corneal endothelial cell suspension is subsequently inoculated to amniotic membrane scaffold carriers that are tiled on the bottom of wells in culture plate to launch in vitro culture as well as in vitro reconstruction of tissue-engineered human corneal endothelium. This invention is scientific and rational. The reconstructed tissue-engineered human corneal endothelium can be produced on large scale to satisfy the great demand of tissue-engineered human corneal endothelium in clinical cornea transplantation for primary corneal endotheliopathy therapy. Meanwhile, costs for in vitro reconstruction of tissue-engineered human corneal endothelium and clinical therapy are low. | 2012-01-19 |
20120015440 | SPHEROID COMPOSITE, SPHEROID-CONTAINING HYDROGEL AND PROCESSES FOR PRODUCTION OF SAME - A spheroid composite includes: a substrate including a cell-adhesive porous base material and plural hydrophilic regions and hydrophobic regions that are disposed on the porous base material and formed by curing a photosensitive composition, wherein the photosensitive composition includes a branched polyalkylene glycol derivative having three or more polyalkylene glycol groups, each having a polymerizable substituent at a terminal thereof, and a tri- or higher-valent linking group that binds to the polyalkylene glycol groups; and spheroids formed in the hydrophobic regions on the substrate, the plural spheroids having a uniform size. A spheroid-containing hydrogel, which includes a hydrogel and two or more spheroids having a uniform size with a diameter of from 70 μm to 400 μm that are disposed in the hydrogel in such a manner that the two or more spheroids do not contact each other, can favorably maintain the function of the plural spheroids contained within the hydrogel. | 2012-01-19 |
20120015441 | APPARATUS FOR MEASURING CHOLESTEROL AND METHOD THEREOF - A microfluidic device and method for measuring a level of cholesterol therewith are provided. The cholesterol measurement apparatus includes a microfluidic device including a plurality of chambers and at least one channel through which the plurality of chambers are interconnected. The plurality of chambers include a reaction chamber which contains a capture binder, a buffer chamber which contains an elution buffer and is connected to the reaction chamber, and at least one detection chamber which contains a cholesterol measurement reagent and is connected to the reaction chamber. | 2012-01-19 |
20120015442 | MICROFLUIDIC SYSTEM INCLUDING A BUBBLE VALVE FOR REGULATING FLUID FLOW THROUGH A MICROCHANNEL - A microfluidic system includes a bubble valve for regulating fluid flow through a microchannel. The bubble valve includes a fluid meniscus interfacing the microchannel interior and an actuator for deflecting the membrane into the microchannel interior to regulate fluid flow. The actuator generates a gas bubble in a liquid in the microchannel when a sufficient pressure is generated on the membrane. | 2012-01-19 |
20120015443 | NOVEL CHIRAL SELECTORS AND STATIONARY PHASES FOR SEPARATING ENANTIOMER MIXTURES - Chiral selectors having α-unsubstituted β-amino acid derivatives of the structure: | 2012-01-19 |
20120015444 | Sensor Housing and Reagent Chemistry - A sensor comprises a sensor housing, having a channel; a porous substrate, in the channel; an analysis chemistry reagent, on the porous substrate; and a nozzle, in fluid connection with the channel. The porous substrate fills a cross section of the channel, and the cross-sectional area of the channel at the porous substrate is greater than the cross-sectional area at the nozzle. | 2012-01-19 |
20120015445 | Portable Fluorimetric Apparatus, Method and System - A fluorimetric system, apparatus and method are disclosed to measure an analyte concentration in a sample. A sensor reagent housing is also disclosed which comprises a channel and a porous medium having an analysis chemistry reagent, such as a nucleic acid analysis chemistry reagent. The apparatus and system are portable for field use, with an apparatus housing having a size adapted to fit into a user's hand. An apparatus also includes a sensing chamber and cover, a user interface, a light source, a photomultiplier tube, an amplifier, an A/D converter, a memory, and a processor. In various embodiments, the processor performs a data fitting, determines a sample reaction rate parameter, and determines the analyte concentration from a comparison of the sample reaction rate parameter with stored calibration data. The processor may also generate the calibration data and site-specific offset factors, and modify the calibration data using an offset factor. | 2012-01-19 |
20120015446 | Chemiluminescent Compositions, Enhancing Reagents for Chemiluminescence and Methods for the Preparation and Use Thereof - A enhancing reagent for enhancing chemiluminescence of 1,2-dioxetane compounds and a method for using the enhancing reagent to enhance the chemiluminescence are provided, in which the enhancing reagent contains an alkyl bis-quaternary ammonium salt of Formula I. A chemiluminescent composition with a 1,2-dioxetane compound as a substrate and a kit thereof are further provided, which contain a 1,2-dioxetane compound and an alkyl bis-quaternary ammonium salt of Formula I. | 2012-01-19 |
20120015447 | Method for operating an analytical apparatus - A method for operating an analytical apparatus for determining concentration of an analyte, especially an oxidizable substance, in a sample liquid, comprises the steps of: placing the analytical apparatus in maintenance operation; operating a metering system, which includes a pump, especially a peristaltic pump, and a supply line, for metering single volume units of a sample liquid from a source via the supply line into a reactor, wherein there exists in the reactor a temperature, which is greater than the boiling temperature of the sample liquid, so that a volume unit of the sample liquid metered into the reactor transforms at least partially into the gas phase following entry into the reactor, especially due to heat transfer from contact with a surface within the reactor, especially directly after contact with the surface within the reactor, and wherein a carrier gas is flowing through the reactor; registering at least one measuring transducer signal for detection of the transforming of the volume unit of the sample liquid into the gas phase, and deriving, with application of the measuring transducer signal, a signal correlated with an instantaneous operating state of the metering system. | 2012-01-19 |
20120015448 | ASSAY DEVICE WITH SHARED ZONES - Disclosed is an assay device for determining the presence and/or extent of one or more analytes in liquid sample containing a) first and second assays each comprising a flow-path having a detection zone for immobilising a labelled binding reagent, wherein detection of a labelled binding reagent at one or both detection zones is indicative of the presence and/or extent of one or more analytes; b) a shared reference zone; c) one or more light sources to illuminate the detection zones and the reference zone; d) one or more photodetectors to detect light from the detection zones and the reference zone, which photodetector/s generate a signal, the magnitude of which signal is related to the amount of light detected; and e) signal processing means for processing signals from the photodetector/s. | 2012-01-19 |
20120015449 | METHOD AND DEVICE FOR DETERMINING A FOREIGN SUBSTANCE CONTENT IN A MATRIX - A method and a device are provided for determining a content of at least one foreign substance in a matrix of a solid or liquid food. At least one reagent area for providing at least one reagent has a receptacle for a replaceable reagent container for replaceably connecting a sample container including at least the matrix; a transfer line is provided between the reagent area and the reaction area, by which the at least one reagent can be fed to the reaction area; a sensor area is provided for demonstrating the foreign substance released from the matrix; a carrier gas line is provided between the reaction area and the sensor area, by which the released foreign substance can be fed to the sensor area; and an output line is provided through which the dissolved foreign substance can be fed outward from the sensor area. | 2012-01-19 |
20120015450 | Method for Detecting Prozone Phenomenon, Analysis Method, Device for Detecting Prozone Phenomenon, and Analysis Device - Provided is a prozone phenomenon detecting method, by which generation of a prozone phenomenon can be detected even when a conventional specimen analysis tool is used, and examinations using an immunochromatography method and the like can be performed efficiently. In the method, a specimen analysis tool containing substances that specifically bind to a target component contained in a sample is used. The specimen analysis tool is obtained by arranging a sample supplying portion, a reagent portion, and a detection portion on the porous base material from upstream to downstream in a sample moving direction in this order. The reagent portion contains a labeled substance that specifically binds to the target component. The detection portion contains an immobilized substance that specifically binds to the target component. The target component is detected by detecting a complex of the target component, the labeled substance, and the immobilized substance through detection of a label of the labeled substance in the detection portion. The method includes at least one of the following processes A and B: the process A: a process in which detection results obtained in the detection portion are plotted along the sample moving direction, and generation of a prozone phenomenon is detected on the basis of a position of a peak in plots thus obtained; and the process B: a process in which the label is detected at two or more different time points in the detection portion, and generation of a prozone phenomenon is detected on the basis of a magnitude relationship between two or more detection results thus obtained. | 2012-01-19 |
20120015451 | FLUID SENSOR PREVENTING GENERATION OF AIR BUBBLES - Provided herein is a fluid sensor, which includes a closed reaction unit in which reaction of a fluid sample takes place. The reaction unit is tapered on a side through which the fluid is injected so as to prevent generation of air bubbles during the injection of the fluid. Thus, the sensor has improved sensitivity. | 2012-01-19 |
20120015452 | Information storage devices using magnetic domain wall movement and methods of manufacturing the same - In an information storage device, a writing magnetic layer is formed on a substrate and has a magnetic domain wall. A connecting magnetic layer is formed on the writing magnetic layer, and an information storing magnetic layer is formed on an upper portion of side surfaces of the connecting magnetic layer. A reader reads information stored in the information storing magnetic layer. | 2012-01-19 |
20120015453 | PHOTOVOLTAIC CELL MANUFACTURING METHOD AND PHOTOVOLTAIC CELL MANUFACTURING APPARATUS - A photovoltaic cell manufacturing method includes: forming a photoelectric converter which has a plurality of compartment elements that are separated by a scribing line and in which adjacent compartment elements are electrically connected; detecting a structural defect existing in the compartment element; specifying a position in which the structural defect exists, as distance data indicating a distance between the structural defect and the scribing line that is closest to the structural defect; and removing a region in which the structural defect exists based on the distance data. | 2012-01-19 |
20120015454 | METHOD OF MANUFACTURING EPITAXIAL SILICON WAFER AND APPARATUS THEREFOR - A method of forming an epitaxial layer to increase flatness of an epitaxial silicon wafer is provided. In particular, a method of controlling the epitaxial layer thickness in a peripheral part of the wafer is provided. An apparatus for manufacturing an epitaxial wafer by growing an epitaxial layer with reaction of a semiconductor wafer and a source gas in a reaction furnace comprising: a pocket in which the semiconductor wafer is placed; a susceptor fixing the semiconductor; orientation-dependent control means dependent on a crystal orientation of the semiconductor wafer and/or orientation-independent control means independent from the crystal orientation of the semiconductor wafer, wherein the apparatus may improve flatness in a peripheral part of the epitaxial layer. | 2012-01-19 |
20120015455 | Method and Apparatus for Calibrating Optical Path Degradation Useful for Decoupled Plasma Nitridation Chambers - Methods for matching semiconductor processing chambers using a calibrated spectrometer are disclosed. In one embodiment, plasma attributes are measured for a process in a reference chamber and a process in an aged chamber. Using a calibrated light source, an optical path equivalent to an optical path in a reference chamber and an optical path in an aged chamber can be compared by determining a correction factor. The correction factor is applied to adjust a measured intensity of plasma radiation through the optical path in the aged chamber. Comparing a measured intensity of plasma radiation in the reference chamber and the adjusted measured intensity in the aged chamber provide an indication of changed chamber conditions. A magnitude of change between the two intensities can be used to adjust the process parameters to yield a processed substrate from the aged chamber which matches that of the reference chamber. | 2012-01-19 |
20120015456 | SYSTEM AND METHOD FOR PROVIDING ACCESS TO AN ENCAPSULATED DEVICE - A method for providing access to a feature on a device wafer, and located outside an encapsulation region is described. The method includes forming a cavity in the lid wafer, aligning the lid wafer with the device wafer so that the cavity is located substantially above the feature, and removing material substantially uniformly from the bottom surface of the lid wafer, until an aperture is formed at the cavity, over the feature on the device wafer. By removing material from the lid wafer in a substantially uniform manner, difficulties with the prior art procedure of saw cutting, such as alignment and debris generation, are avoided. | 2012-01-19 |
20120015457 | PCB-MOUNTED INTEGRATED CIRCUITS - A method and apparatus ( | 2012-01-19 |
20120015458 | MOUNTING APPARATUS AND MOUNTING METHOD - Provided is a mounting apparatus which mounts a chip component on a circuit pattern on a circuit board having a plurality of circuit patterns formed thereon. The mounting apparatus is provided with a plurality of bonding tools each of which mounts the chip component on each of the circuit patterns on the circuit board. Each bonding tool is provided with, within a region on the circuit board where the chip component is to be mounted, an exclusive mounting region where only each bonding tool can mount the chip component, and a common mounting region where both the bonding tool and the adjacent bonding tool can mount the chip component. A mounting method is also provided. The mounting tact time of the chip components can be shortened even in case where a plurality of circuit patterns are formed on the circuit board and a failure circuit pattern is included among the circuit patterns which have been formed. | 2012-01-19 |
20120015459 | Thermal Leveling for Semiconductor Devices - A semiconductor device and a method of manufacturing are provided. In some embodiments, a backside annealing process such that a first heat source is placed along a backside of the substrate. In other embodiments, the first heat source is used in combination with an anti-reflection dielectric (ARD) layer is deposited over the substrate. In yet other embodiments, a second heat source is placed along a front side of the substrate in addition to the first heat source placed on the backside of the substrate. In yet other embodiments, a heat shield may be placed between the substrate and the second heat source on the front side of the substrate. In yet further embodiments, a single heat source may be used on the front side of the substrate in combination with the ARD layer. A reflectivity scan may be performed to determine which anneal stage (RTA or MSA or both) to place thermal leveling solution. | 2012-01-19 |
20120015460 | System and Method for Estimating Field Curvature - Projection systems and methods with mechanically decoupled metrology plates according to embodiments of the present invention can be used to characterize and compensate for misalignment and aberration in production images due to thermal and mechanical effects. Sensors on the metrology plate measure the position of the metrology plate relative to the image and to the substrate during exposure of the substrate to the production image. Data from the sensors are used to adjust the projection optics and/or substrate dynamically to correct or compensate for alignment errors and aberration-induced errors. Compared to prior art systems and methods, the projection systems and methods described herein offer greater design flexibility and relaxed constraints on mechanical stability and thermally induced expansion. In addition, decoupled metrology plates can be used to align two or more objectives simultaneously and independently. | 2012-01-19 |
20120015461 | System Metrology Core - Projection systems and methods with mechanically decoupled metrology plates according to embodiments of the present invention can be used to characterize and compensate for misalignment and aberration in production images due to thermal and mechanical effects. Sensors on the metrology plate measure the position of the metrology plate relative to the image and to the substrate during exposure of the substrate to the production image. Data from the sensors are used to adjust the projection optics and/or substrate dynamically to correct or compensate for alignment errors and aberration-induced errors. Compared to prior art systems and methods, the projection systems and methods described herein offer greater design flexibility and relaxed constraints on mechanical stability and thermally induced expansion. In addition, decoupled metrology plates can be used to align two or more objectives simultaneously and independently. | 2012-01-19 |
20120015462 | METHOD OF MANUFACTURING LED MODULE - A method for manufacturing an LED module, including steps of: providing a heat conductive plate and an LED die, the heat conductive plate defining a concave groove therein; forming an electrode circuit layer on the heat conductive plate around the concave groove; plating one metal layer on a bottom of the concave groove of the heat conductive plate, and plating another metal layer on the LED die; eutectically bonding the metal layer of the heat conducting plate and the metal layer of the LED die together to form into an eutectic layer; forming electrodes on the LED die, and connecting the electrodes with the electrode circuit layer; and encapsulating the LED die in the concave groove. | 2012-01-19 |
20120015463 | METHOD FOR MANUFACTURING LIGHT-EMITTING DEVICE - The present invention relates to a method for manufacturing a light-emitting device, the method including applying resin encapsulation to a lead frame having mounted and packaged thereon a plurality of light-emitting elements, in which the following lead frame portion (A) is used as the lead frame portion: (A) a lead frame portion that is obtained by cutting and separating a lead frame, in which the lead frame has a lattice form including a plurality of rows and a plurality of columns with a plurality of intersection points formed thereby and has a plurality of light-emitting elements disposed and packaged between the adjacent intersection points in each row, into individual column to produce a lead frame portion for each column, and that is passed a light emission test performed by flowing a current to the lead frame portion. | 2012-01-19 |
20120015464 | METHOD OF FORMING A COLOR FILTER TOUCH SENSING SUBSTRATE - A method of forming a color filter touch sensing substrate integrates touch-sensing structures/elements of a touch panel into the inner side of the color filter substrate, which faces a thin film transistor substrate, and forms patterned assistant electrodes on the surfaces of the transparent sensing pads for decreasing the equivalent resistance of the touch-sensing structures/elements. Moreover, since an adjacent transparent conductive layer and an assistant electrode layer are patterned to form the transparent sensing pads and the patterned assistant electrodes, a simplified pattern-transferring process can be applied to the transparent sensing pads and the patterned assistant electrodes, or bridge structures can be formed from the assistant electrode layer for electrically connecting between some transparent sensing pads. Therefore, the forming process is simplified. | 2012-01-19 |
20120015465 | Nitride semiconductor light emitting device, method of manufacturing nitride semiconductor light emitting device, and nitride semiconductor transistor device - Example embodiments herein relate to a nitride semiconductor light emitting device including a coat film formed at a light emitting portion and including an aluminum nitride crystal or an aluminum oxynitride crystal, and a method of manufacturing the nitride semiconductor light emitting device. Also provided is a nitride semiconductor transistor device including a nitride semiconductor layer and a gate insulating film which is in contact with the nitride semiconductor layer and includes an aluminum nitride crystal or an aluminum oxynitride crystal. | 2012-01-19 |
20120015466 | METHOD FOR FABRICATING LIGHT EMITTING DEVICE - Provided is a method for fabricating a light emitting device. The method includes forming a gallium oxide layer; forming a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer on the gallium oxide layer; forming a non-conductive substrate on the second conductive type semiconductor layer; separating the gallium oxide layer forming a conductive substrate on the first conductive type semiconductor layer; and separating the non-conductive substrate. | 2012-01-19 |
20120015467 | BIOSENSOR USING NANODOT AND METHOD OF MANUFACTURING THE SAME - A biosensor using a nanodot and a method of manufacturing the same are provided. A silicon nanowire can be formed by a CMOS process to reduce manufacturing costs. In addition, an electrically charged nanodot is coupled to a target molecule to be detected, in order to readily change conductivity of the silicon nanowire, thereby making it possible to implement a biosensor capable of providing good sensitivity and being manufactured at a low cost. | 2012-01-19 |
20120015468 | SURFACE MOUNT MEMS DEVICE STRUCTURE AND FABRICATING METHOD THEREOF FOR CRYSTAL OSCILLATORS - A method of fabricating surface mount micro electro mechanical systems (MEMS) device includes forming SMD MEMS crystal oscillator devices on wafer and forming its bonding structure, also can either use lithographic packing process or single package mount bonding crystal blanks packing process. The method further includes embedded crystal device into the integrated circuit, it effectively to eliminate the use of extra the discrete components, reduced the fabrication cost and fail rate for system in package (SIP) or chip on board (COB) packing. | 2012-01-19 |
20120015469 | High-Efficiency, Monolithic, Multi-Bandgap, Tandem, Photovoltaic Energy Converters - A monolithic, multi-bandgap, tandem solar photovoltaic converter has at least one, and preferably at least two, subcells grown lattice-matched on a substrate with a bandgap in medium to high energy portions of the solar spectrum and at least one subcell grown lattice-mismatched to the substrate with a bandgap in the low energy portion of the solar spectrum, for example, about 1 eV. | 2012-01-19 |
20120015470 | METHOD FOR ROUGHENING SUBSTRATE SURFACE AND METHOD FOR MANUFACTURING PHOTOVOLTAIC DEVICE - A method of roughening a substrate surface includes forming an opening in a protection film formed on a surface of a semiconductor substrate, performing a first etching process using an acid solution by utilizing the protection film as a mask so as to form a first concave under the opening and its vicinity area, performing an etching process by using the protection film as a mask so as to remove an oxide film formed on a surface of the first concave, performing anisotropic etching by using the protection film as a mask so as to form a second concave under the opening and its vicinity area, and removing the protection film. | 2012-01-19 |
20120015471 | MULTIPLE-PATH LASER EDGE DELETE PROCESS FOR THIN-FILM SOLAR MODULES - Embodiments of the present invention provide methods for edge film stack removal for use in fabricating photovoltaic devices. In one embodiment, the method includes providing a substrate having a film stack deposited thereon, the film stack comprising a transparent conductive layer, a silicon-containing layer, and a metal back contact layer, removing the metal back contact layer and the silicon-containing layer formed on a periphery region along a side of the substrate using an electromagnetic radiation delivered at a first energy level, and removing the transparent conductive layer formed on the periphery region along the side of the substrate using electromagnetic radiation delivered at a second energy level that is higher than the first energy level. | 2012-01-19 |
20120015472 | METHOD OF PRODUCING SOLAR CELL MODULE - On a substrate is formed a transparent and conductive front electrode layer, on which is formed a photoelectric conversion unit that generates an electric power by a light. On the photoelectric conversion unit is formed a transparent and conductive film, on which a silver-containing back electrode layer. On the back electrode layer is formed further a back electrode reinforcing film formed by UV-irradiation of, or by heating of, or by heating after UV-irradiation of a layer that is obtained by applying a composition for reinforcing film on the back electrode layer with a wet coating method. | 2012-01-19 |
20120015473 | PHOTOELECTRIC CONVERSION DEVICE MANUFACTURING METHOD, PHOTOELECTRIC CONVERSION DEVICE, PHOTOELECTRIC CONVERSION DEVICE MANUFACTURING SYSTEM, AND METHOD FOR USING PHOTOELECTRIC CONVERSION DEVICE MANUFACTURING SYSTEM - A photoelectric conversion device manufacturing method manufactures a photoelectric conversion device in which a first photoelectric conversion unit and a second photoelectric conversion unit are sequentially stacked on a transparent-electroconductive film formed on a substrate. The method includes: forming each of a first p-type semiconductor layer, a first i-type semiconductor layer, a first n-type semiconductor layer, and a second p-type semiconductor layer in a plurality of first plasma CVD reaction chambers; exposing the second p-type semiconductor layer to an air atmosphere; supplying a gas including p-type impurities to inside a second plasma CVD reaction chamber before forming of the second i-type semiconductor layer; forming the second i-type semiconductor layer on the second p-type semiconductor layer that was exposed to an air atmosphere, in the second plasma CVD reaction chamber; and forming the second n-type semiconductor layer on the second i-type semiconductor layer. | 2012-01-19 |
20120015474 | METHOD FOR FABRICATING SILICON HETEROJUNCTION SOLAR CELLS - The present invention discloses a method for fabricating a silicon heterojunction solar cell. The silicon heterojunction solar cell according to the present invention comprises a first conductive silicon substrate; a first intrinsic silicon layer and a second intrinsic silicon layer respectively formed on two sides of the first conductive silicon substrate and jointed with the first conductive silicon substrate to form silicon heterojunctions; a second conductive silicon layer and a first conductive heavily-doped silicon layer respectively formed on the first intrinsic silicon layer and the second intrinsic silicon layer, wherein the second conductive silicon layer and the first conductive heavily-doped silicon layer are formed via an ion implantation method, whereby is optimized the thickness and doped quality of the second conductive silicon layer and the first conductive heavily-doped silicon layer. | 2012-01-19 |
20120015475 | Methods Of Forming Memory Cells, And Methods Of Patterning Chalcogenide-Containing Stacks - Some embodiments include methods of forming memory cells. Chalcogenide is formed over a plurality of bottom electrodes, and top electrode material is formed over the chalcogenide. Sacrificial material is formed over the top electrode material. A plurality of memory cell structures is formed by etching through the sacrificial material, top electrode material and chalcogenide. Each of the memory cell structures has a cap of the sacrificial material thereover. The etching forms polymeric residue over the sacrificial material caps, and damages chalcogenide along sidewalls of the structures. The sacrificial material is removed with an HF-containing solution, and such removes the polymeric residue off of the memory cell structures. After the sacrificial material is removed, the sidewalls of the structures are treated with one or both of H | 2012-01-19 |
20120015476 | METHOD FOR PRODUCING SEMICONDUCTOR LAYERS AND COATED SUBSTRATES TREATED WITH ELEMENTAL SELENIUM AND/OR SULFER, IN PARTICULAR FLAT SUBSTRATES - The invention relates to a method for producing semiconductor layers and coated substrates treated with elemental selenium and/or sulphur, in particular flat substrates, containing at least one conducting, semiconducting and/or insulating layer, in which a substrate which is provided with at least one metal layer and/or with at least one layer containing metal, in particular a stack of substrates, each of which is provided with at least one metal layer and/or with at least one layer which contains metal, is inserted into a processing chamber and heated to a predetermined substrate temperature; elementary selenium and/or sulphur vapor is guided past on the or on every metal layer and/or layer containing metal, from a source located inside and/or outside the processing chamber, in particular by means of a carrier gas which is in particular inert, under rough vacuum conditions or ambient pressure conditions or overpressure conditions, in order to react chemically with said layer with selenium or sulphur in a targeted manner; the substrate is heated by means of forced convection by at least one gas conveying device and/or the elementary selenium and/or sulphur vapor is mixed and guided past on the substrate by means of forced convection by at least one gas conveying device in the processing chamber, in particular in a homogeneous manner. The invention furthermore relates to a processing device for implementing a method of this type. | 2012-01-19 |
20120015477 | STACKED SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME - A stacked semiconductor package having a unit package, cover substrates, adhesive members and connection electrodes is presented. The unit package includes a substrate, a first circuit pattern and a second circuit pattern. The first circuit pattern is disposed over an upper face of the substrate. The second circuit pattern is disposed over a lower face of the substrate. The lower and upper faces of the substrate oppose each other. The first and second semiconductor chips are respectively electrically connected to the first and second circuit patterns. The cover substrates are opposed to the first semiconductor chip and the second semiconductor chip. The adhesive members are respectively interposed between the unit package and the cover substrates. The connection electrodes pass through the unit package, the cover substrates and the adhesive members and are electrically connected to the first and second circuit patterns. | 2012-01-19 |
20120015478 | Integrated Circuit Stacked Package Precursors and Stacked Packaged Devices and Systems Therefrom - A package-on-package (POP) package precursor and packaged devices and systems therefrom includes an electronic substrate including electrically conductive layers and a top surface. A first portion of the top surface has an IC die attached thereon. A second portion of the top surface has a plurality of first attach pads on opposing sides of the IC die for electrically coupling to a first electronic device on top of the IC die. At least a third portion of the top surface is positioned laterally with respect to the first and second portion. The third portion includes a plurality of second attach pads for electrically coupling to at least a second electronic device. At least one of the electrically conductive layers includes a coupling trace that couples at least one of the plurality of second attach pads to the IC die and/or one or more of the plurality of first attach pads. | 2012-01-19 |
20120015479 | Semiconductor Package with a Mold Material Encapsulating a Chip and a Portion of a Lead Frame - Various exemplary embodiments provide components, devices, and methods of semiconductor packaging. The disclosed packaging component can include a mold material disposed around a lead frame and at least an integrated circuit (IC), wherein the IC is electrically connected with one side of the lead frame. The opposite side of the lead frame including, for example, lead segments, can be exposed from the mold material. A variety of other components, devices, and packages can then be assembled, e.g., over the disclosed packaging component, through the exposed regions so as to improve packaging densities. | 2012-01-19 |
20120015480 | SYSTEM AND METHOD FOR MULTI-CHIP MODULE DIE EXTRACTION AND REPLACEMENT - A system and method are provided in which a first chip in a stacked multi-chip module configuration is affixed via one or more adhesion layers to a first portion of a partitioned interposer unit. Planar partitions of the interposer are physically bonded via multiple solder “bumps,” which possess high tensile strength but low resistance to horizontal shear force or torque. A second chip is affixed via one or more adhesion layers to the second portion of the partitioned interposer. The chips may thus be separated by horizontally and oppositely shearing or twisting the first and second portions of the partitioned interposer away from one another. | 2012-01-19 |
20120015481 | METHOD OF MANUFACTURING STACK TYPE SEMICONDUCTOR PACKAGE - A method of manufacturing a stack type semiconductor package is provided. A lower semiconductor package including a circuit board on which a semiconductor chip and electrode pads are formed is provided. A plurality of metal pins are adhered and fixed to the electrode pads of the circuit board of the lower semiconductor package, respectively. An upper semiconductor package is vertically stacked on the lower semiconductor package via the metal pins. | 2012-01-19 |
20120015482 | ISOLATED STACKED DIE SEMICONDUCTOR PACKAGES - Semiconductor packages that contain isolated, stacked dies and methods for making such devices are described. The semiconductor package contains both a first die with a first integrated circuit and a second die with a second integrated circuit that is stacked onto the first die while also being isolated from the first die. The first and second dies are connected using an array of metal connectors containing both a base segment and a beam segment extending over the first die and supporting the second die. This configuration can provide a thinner semiconductor package since wire-bonding is not used. As well, since the integrated circuit devices in the first and second dies are isolated from each other, local heating and/or hot spots are diminished or prevented in the semiconductor package. Other embodiments are also described. | 2012-01-19 |
20120015483 | Semiconductor Device Package and Method of Assembly Thereof - A semiconductor die package includes: an assembly including a semiconductor die, a clip structure attached to an upper surface of the semiconductor die, and a heat sink attached to an upper surface of the clip structure; and a molding material partially encapsulating the assembly, wherein an upper surface of the heat sink is exposed through the molding material. | 2012-01-19 |
20120015484 | POWER SEMICONDUCTOR MODULE AND METHOD OF MANUFACTURING THE SAME - Disclosed herein is a power semiconductor module. The module includes metal plates each having a first through hole, with an anodic oxidation layer formed on a surface of metal plates and an interior of the first through hole. A cooling member has a second through hole at a position corresponding to the first through hole, and the metal plates are attached to both sides of the cooling member. A circuit layer is formed on the anodic oxidation layer and performs an interlayer connection through a via formed in the first and second through holes. A power device is connected to the circuit layer. A resin encapsulant encloses the circuit layer and the power device. A housing is installed to each of the metal plates to form a sealing space for the resin encapsulant. | 2012-01-19 |
20120015485 | LOW NOISE HIGH THERMAL CONDUCTIVITY MIXED SIGNAL PACKAGE - An improved microelectronic assembly ( | 2012-01-19 |
20120015486 | Semiconductor Constructions And Methods Of Forming Patterns - Some embodiments include methods of forming patterns. A semiconductor substrate is formed to comprise an electrically insulative material over a set of electrically conductive structures. An interconnect region is defined across the electrically conductive structures, and regions on opposing sides of the interconnect region are defined as secondary regions. A two-dimensional array of features is formed over the electrically insulative material. The two-dimensional array extends across the interconnect region and across the secondary regions. A pattern of the two-dimensional array is transferred through the electrically insulative material of the interconnect region to form contact openings that extend through the electrically insulative material and to the electrically conductive structures, and no portions of the two-dimensional array of the secondary regions is transferred into the electrically insulative material. | 2012-01-19 |
20120015487 | THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE SAME INCLUDING FORMING A TEMPERATURE DEPENDENT GATE INSULATING LAYER - The present invention provides a thin film transistor array panel comprising a substrate; a gate line containing Ag formed on the substrate at a low temperature to prevent agglomeration, a first gate insulating layer formed on the gate line, a second gate insulating layer formed on the first gate insulating layer, a data line perpendicularly intersecting the gate line, and a thin film transistor connected to the gate line and the data line, and a manufacturing method thereof. | 2012-01-19 |
20120015488 | HIGH-K GATE DIELECTRIC OXIDE - A dielectric such as a gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO2 gate oxides are provided. Gate oxides formed from elements such as zirconium are thermodynamically stable such that the gate oxides formed will have minimal reactions with a silicon substrate or other structures during any later high temperature processing stages. The process shown is performed at lower temperatures than the prior art, which further inhibits reactions with the silicon substrate or other structures. Using a thermal evaporation technique to deposit the layer to be oxidized, the underlying substrate surface smoothness is preserved, thus providing improved and more consistent electrical properties in the resulting gate oxide. | 2012-01-19 |
20120015489 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - A semiconductor device and a method of manufacturing a semiconductor device are provided. In a method of manufacturing a semiconductor device, a gate structure is formed on a substrate. An epitaxial layer is formed on a top surface of the substrate adjacent to the gate structure. An elevated source/drain (ESD) layer and an impurity region are formed by implanting impurities and carbon in the epitaxial layer and an upper portion of the substrate using the gate structure as an ion implantation mask. A metal silicide layer is formed on the ESD layer. | 2012-01-19 |
20120015490 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - A method of manufacturing a semiconductor device includes forming a gate structure on a substrate; forming a sacrificial spacer may be formed on a sidewall of the gate substrate; implanting first impurities into portions of the substrate by a first ion implantation process using the gate structure and the sacrificial spacer as ion implantation masks to form source and drain regions; removing the sacrificial spacer; and implanting second impurities and carbon atoms into portions of the substrate by a second ion implantation process using the gate structure as an ion implantation mask to form source and drain extension regions and carbon doping regions, respectively. | 2012-01-19 |
20120015491 | Method of fabricating a high-voltage transistor with an extended drain structure - A method for fabricating a high-voltage transistor with an extended drain region includes forming in a semiconductor substrate of a first conductivity type, first and second trenches that define a mesa having respective first and second sidewalls; then partially filling each of the trenches with a dielectric material that covers the first and second sidewalls. The remaining portions of the trenches are then filled with a conductive material to form first and second field plates. Source and body regions are formed in an upper portion of the mesa, with the body region separating the source from a lower portion of the mesa. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b). | 2012-01-19 |
20120015492 | INSULATED GATE TYPE SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer. | 2012-01-19 |
20120015493 | INTEGRATED METHOD FOR FORMING METAL GATE FinFET DEVICES - Provided is a high-k metal gate structure formed over a semiconductor fin. A nitride layer is formed over the gate structure and the semiconductor fin, using two separate deposition operations, the first forming a very thin nitride film. Implantation operations may be carried out in between the two nitride film deposition operations. The first nitride film may be SiN | 2012-01-19 |
20120015494 | METHOD FOR FABRICATING BOTTOM ELECTRODE OF CAPACITORS OF DRAM - A method for manufacturing a capacitor bottom electrode of a dynamic random access memory is provided. The method comprises providing a substrate having a memory cell region and forming a polysilicon template layer on the memory cell region of the substrate. A supporting layer is formed on the polysilicon template layer and plural openings penetrating through the supporting layer and the polysilicon template layer are formed and a liner layer is formed on at least a portion of the polysilicon template layer exposed by the openings A conductive layer substantially conformal to the substrate is formed on the substrate. A portion of the conductive layer on the supporting layer is removed so as to form plural capacitor bottom electrodes. Using the polysilicon template layer, the openings with relatively better profiles are formed and the dimension of the device can be decreased. | 2012-01-19 |
20120015495 | SEMICONDUCTOR DEVICE INCLUDING MIM ELEMENT AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes forming a first insulating film above a semiconductor substrate, forming a wiring to be buried in the first insulating film, forming a protruding portion in an upper surface of the wiring, forming a second insulating film above the first insulating film and the wiring including the protruding portion, planarizing a surface of the second insulating film, forming a third insulating film on the second insulating film whose surface is planarized, forming a lower electrode on the third insulating film, forming a capacitor insulating film on the lower electrode, and forming an upper electrode on the capacitor insulating film. | 2012-01-19 |
20120015496 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate having a first area and a second area, a first transistor in the first area, a second transistor in the second area, an isolation layer between the first area and the second area, and at least one buried shield structure on the isolation layer. | 2012-01-19 |
20120015497 | Preparing a Surface of a Sapphire Substrate for Fabricating Heterostructures - A method of fabricating a heterostructure comprising at least a first substrate ( | 2012-01-19 |
20120015498 | TEMPORARY SUBSTRATE, TRANSFER METHOD AND PRODUCTION METHOD - The present invention relates to a temporary substrate having a bonding surface prepared for receiving an additional substrate that will transfer a thin layer. This substrate includes a principal part or support and a surface layer thereon with the surface layer having a plurality of inserts therein. The inserts are made of a material having a coefficient of thermal expansion that is significantly different from that of the material constituting the surface layer. The present invention also relates to a processing method for transferring a selected portion of an original substrate as well as to a production method for manufacturing the temporary substrate. | 2012-01-19 |
20120015499 | METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE - A combined substrate is prepared which has a supporting portion and first and second silicon carbide substrates. Between the first and second silicon carbide substrates, a gap having an opening exists. A closing layer for the gap is formed over the opening. The closing layer at least includes a silicon layer. In order to form a cover made of silicon carbide and closing the gap over the opening, the silicon layer is carbonized. By depositing sublimates from the first and second side surfaces of the first and second silicon carbide substrates onto the cover, a connecting portion is formed to close the opening. The cover is removed. | 2012-01-19 |
20120015500 | Method of manufacturing wafer level package - A method for manufacturing a wafer level package including: forming a redistribution line connected to a top surface of a die pad on a wafer with the die pad; additionally preparing a carrier film including a metal post with a concave central portion on one surface; bonding the metal post to a top surface of the redistribution line; molding a space between the metal posts with a molding resin; and removing the carrier film. | 2012-01-19 |
20120015501 | Silicon Surface Modification for the Electrochemical Synthesis of Silicon Particles in Suspension - A process of silicon (Si) surface modification is provided for the electrochemical synthesis of Si particles in suspension. The process begins with a Si first substrate with a surface, and forms Si particles attached to the surface. Hydrogen-terminated Si particles are created and the first substrate is immersed in a hexane/1-octene (1/1 volume ratio) solution with a catalytic amount of chloroplatinic acid (H | 2012-01-19 |
20120015502 | p-GaN Fabrication Process Utilizing a Dedicated Chamber and Method of Minimizing Magnesium Redistribution for Sharper Decay Profile - Methods and systems for the fabrication of p-GaN, and related, films utilizing a dedicated chamber in a multi-chamber tool are described. Also described are methods of fabricating a magnesium doped group III-V material layer, such as a GaN layer, with a sharp magnesium decay profile. | 2012-01-19 |
20120015503 | METHOD OF FORMING SEMICONDUCTOR STRUCTURE - A method of forming a semiconductor device includes chemically cleaning a surface of a substrate to form a chemical oxide material on the surface. At least a portion of the chemical oxide material is removed at a removing rate of about 2 nanometer/minute (nm/min) or less. Thereafter, a gate dielectric layer is formed over the surface of the substrate. | 2012-01-19 |
20120015504 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - A semiconductor device includes: a first semiconductor region formed on a substrate and having an upper surface and a side surface; a first impurity region of a first conductivity type formed in an upper portion of the first semiconductor region; a second impurity region of a first conductivity type formed in a side portion of the first semiconductor region; and a gate insulating film formed so as to cover at least a side surface and an upper corner of a predetermined portion of the first semiconductor region. A radius of curvature r′ of an upper corner of a portion of the first semiconductor region located outside the gate insulating film is greater than a radius of curvature r of an upper corner of a portion of the first semiconductor region located under the gate insulating film and is less than or equal to 2r. | 2012-01-19 |
20120015505 | METHOD AND DEVICE FOR PREPARING COMPOUND SEMICONDUCTOR FILM - The present invention discloses a method and a device for preparing a compound semiconductor film. The method comprises the steps of: providing a substrate above at least an evaporation source in a vacuum condition; heating a source material contained in the evaporation source so that the source material is vapor-deposited on the substrate; and taking out the substrate under protection of an inert gas. The substrate may be rotated around an axis of a plane where the evaporation source is positioned, and the substrate is tilted by a predetermined angle with respect to the plane. The compound semi-conductive film thus prepared has a uniform thickness with a larger area. The method provides a simplified process and enhanced efficiency. | 2012-01-19 |
20120015506 | TWO TERMINAL RESISTIVE SWITCHING DEVICE STRUCTURE AND METHOD OF FABRICATING - A method of forming a two terminal device. The method includes forming a first dielectric material overlying a surface region of a substrate. A bottom wiring material is formed overlying the first dielectric material and a switching material is deposited overlying the bottom wiring material. The bottom wiring material and the switching material is subjected to a first patterning and etching process to form a first structure having a top surface region and a side region. The first structure includes at least a bottom wiring structure and a switching element having a first side region, and a top surface region including an exposed region of the switching element. A second dielectric material is formed overlying at least the first structure including the exposed region of the switching element. The method forms an opening region in a portion of the second dielectric layer to expose a portion of the top surface region of the switching element. A top wiring material including a conductive material is formed overlying at lease the opening region such that the conductive material is in direct contact with the switching element. A second etching process is performed to form at least a top wiring structure. In a specific embodiment, the side region of the first structure including a first side region of the switching element is free from a contaminant conductive material from the second etching process. | 2012-01-19 |
20120015507 | PLASMA DOPING APPARATUS AND PLASMA DOPING METHOD - A plasma doping apparatus for adding an impurity to a semiconductor substrate includes a chamber, a gas supply unit configured for supplying gas to the chamber, and a plasma source by which to cause the chamber to generate plasma of the supplied gas. The mixed gas containing material gas containing an impurity element to be added to the semiconductor substrate, hydrogen gas, and diluent gas for diluting the material gas is supplied to the chamber. | 2012-01-19 |
20120015508 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a method of manufacturing a semiconductor device capable of preventing a relative displacement of the positions between a range where impurity ions are injected and a range where charged particles are injected. The method of manufacturing the semiconductor device includes: irradiating impurity ions in a state in which a mask is disposed between an impurity ion irradiation apparatus and a semiconductor substrate; and irradiating charged particles to form a short carrier lifetime region, in a state in which the mask is disposed between a charged particle irradiation apparatus and the semiconductor substrate. A relative positional relationship between the mask and the semiconductor substrate is not changed from a beginning of one of the irradiating the impurity ions and the irradiating the charged particles to a completion of both of the irradiating the impurity ions and the irradiating the charged particles. | 2012-01-19 |
20120015509 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming junction area for a bit line contact (BLC) and a junction area for a storage node contact (SNC) by performing ion implantation in a substrate having a buried gate; forming a first insulation pattern having an opening to expose the junction areas; forming a buffer layer to fill the openings; forming a second insulation pattern over the first insulation pattern after filling the openings, wherein the second insulation pattern has openings to expose the buffer layer in an area of the buffer layer that lies over the junction area for the SNC; and forming an SNC to fill the opening of the second insulation patterns. | 2012-01-19 |
20120015510 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE INCLUDING ION IMPLANTATION AT A TILT ANGLE IN EXPOSED REGIONS - A method of fabricating a semiconductor device includes forming a mask pattern for defining a region of a semiconductor substrate. A field stop dopant layer will be formed in the defined region. Dopant ions are implanted into the defined region of the semiconductor substrate at a tilt angle of approximately 4.4° to 7°. | 2012-01-19 |
20120015511 | ON-CHIP EMBEDDED THERMAL ANTENNA FOR CHIP COOLING - An apparatus comprises a first layer within a semiconductor chip having active structures electrically connected to other active structures and having electrically isolated first inactive structures. A second layer within the semiconductor chip is physically connected to the first layer. The second layer comprises an insulator and has second inactive structures. The first inactive structures are physically aligned with the second inactive structures. | 2012-01-19 |
20120015512 | METHOD OF MANUFACTURING NON-VOLATILE MEMORY DEVICE - A non-volatile memory device includes field insulating layer patterns on a substrate to define an active region of the substrate, upper portions of the field insulating layer patterns protruding above an upper surface of the substrate, a tunnel insulating layer on the active region, a charge trapping layer on the tunnel insulating layer, a blocking layer on the charge trapping layer, first insulating layers on upper surfaces of the field insulating layer patterns, and a word line structure on the blocking layer and first insulating layers. | 2012-01-19 |
20120015513 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a recess to an AlGaN layer by etching, the AlGaN layer having an Al composition ratio of 0.2 or greater, the recess having a bottom having an RMS roughness less than 0.3 nm, forming a first Ta layer having a thickness of 4 nm to 8 nm on the bottom of the recess, and annealing the first Ta layer to make an ohmic contact in the AlGaN layer. | 2012-01-19 |
20120015514 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed. | 2012-01-19 |
20120015515 | MANUFACTURING METHOD FOR A BURIED CIRCUIT STRUCTURE - A manufacturing method for a buried circuit structure includes providing a substrate having at least a trench therein, forming a conductive layer having a top lower than an opening of the trench in the trench, performing a selective metal chemical vapor deposition (CVD) to form a metal layer having a top lower than the substrate in the trench, and forming a protecting layer filling the trench on the metal layer. | 2012-01-19 |
20120015516 | ELECTRICAL CONDUCTOR LINE HAVING A MULTILAYER DIFFUSION BARRIER FOR USE IN A SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - An electrical conductor having a multilayer diffusion barrier of use in a resultant semiconductor device is presented. The electrical conductor line includes an insulation layer, a diffusion barrier, and a metal line. The insulation layer is formed on a semiconductor substrate and having a metal line forming region. The diffusion barrier is formed on a surface of the metal line forming region of the insulation layer and has a multi-layered structure made of TaN layer, an Mo | 2012-01-19 |
20120015517 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The semiconductor device includes an insulating film that is formed using a cyclic siloxane having a six-membered ring structure as a raw material; a trench that is formed in the insulating film; and a interconnect that is configured by a metal film embedded in the trench. In the semiconductor device, a modified layer is formed on a bottom surface of the trench, in which the number of carbon atoms and/or the number of nitrogen atoms per unit volume is larger than that inside the insulating film. | 2012-01-19 |
20120015518 | METHOD FOR DEPOSITING THIN TUNGSTEN FILM WITH LOW RESISTIVITY AND ROBUST MICRO-ADHESION CHARACTERISTICS - Methods of forming low resistivity tungsten films with good uniformity and good adhesion to the underlying layer are provided. The methods involve forming a tungsten nucleation layer using a pulsed nucleation layer process at low temperature and then treating the deposited nucleation layer prior to depositing the bulk tungsten fill. The treatment operation lowers resistivity of the deposited tungsten film. In certain embodiments, the depositing the nucleation layer involves a boron-based chemistry in the absence of hydrogen. Also in certain embodiments, the treatment operations involve exposing the nucleation layer to alternating cycles of a reducing agent and a tungsten-containing precursor. The methods are useful for depositing films in high aspect ratio and/or narrow features. The films exhibit low resistivity at narrow line widths and excellent step coverage. | 2012-01-19 |
20120015519 | DAMPING POLYURETHANE CMP PADS WITH MICROFILLERS - A system for preparing a microcellular polyurethane material, includes a froth, prepared, for instance, by inert gas frothing a urethane prepolymer, preferably an aliphatic isocyanate polyether prepolymer, in the presence of a surfactant; a filler soluble in a CMP slurry; and a curative, preferably including an aromatic diamine and a triol. To produce the microcellular material, the froth can be combined with the filler, e.g., PVP, followed by curing the resulting mixture. The microcellular material has a low rebound and can dissipate irregular energy and stabilize polishing to yield improved uniformity and less dishing. CMP pads using the microcellular material have pores created by inert gas frothing throughout the pad polymer body and additional surface pores created by dissolution of fillers during polishing, providing flexibility in surface softness and pad stiffness. | 2012-01-19 |
20120015520 | Methods of Modifying Oxide Spacers - Methods for reducing line roughness of spacers and other features utilizing a non-plasma and non-wet etch fluoride processing technology are provided. Embodiments of the methods can be used for spacer or line reduction and/or smoothing the surfaces along the edges of such features through the reaction and subsequent removal of material. | 2012-01-19 |
20120015521 | AMORPHOUS CARBON DEPOSITION METHOD FOR IMPROVED STACK DEFECTIVITY - Embodiments described herein relate to materials and processes for patterning and etching features in a semiconductor substrate. In one embodiment, a method of forming a composite amorphous carbon layer for improved stack defectivity on a substrate is provided. The method comprises positioning a substrate in a process chamber, introducing a hydrocarbon source gas into the process chamber, introducing a diluent source gas into the process chamber, introducing a plasma-initiating gas into the process chamber, generating a plasma in the process chamber, forming an amorphous carbon initiation layer on the substrate, wherein the hydrocarbon source gas has a volumetric flow rate to diluent source gas flow rate ratio of 1:12 or less; and forming a bulk amorphous carbon layer on the amorphous carbon initiation layer, wherein a hydrocarbon source gas used to form the bulk amorphous carbon layer has a volumetric flow rate to a diluent source gas flow rate of 1:6 or greater to form the composite amorphous carbon layer. | 2012-01-19 |
20120015522 | SUBSTRATE PROCESSING METHOD, SEMICONDUCTOR CHIP MANUFACTURING METHOD, AND RESIN-ADHESIVE-LAYER-BACKED SEMICONDUCTOR CHIP MANUFACTURING METHOD - To provide a substrate processing method and a semiconductor chip manufacturing method that enable low-cost formation of a mask for etching using plasma etching. During formation of a mask used in plasma dicing for separating a semiconductor wafer | 2012-01-19 |
20120015523 | SYSTEMS AND METHODS FOR ETCHING SILICON NITRIDE - To remove a silicon nitride layer on a silicon wafer, phosphoric acid is applied onto the wafer in a sealed chamber. The phosphoric acid may be atomized and sprayed onto the wafer as a mist or aerosol. The wafer is heated to a processing temperature and then maintained at or near the processing temperature with a coating of phosphoric acid on the wafer. The heating and applying phosphoric acid are then stopped, the wafer is cooled, and then removed from the process chamber. An infrared radiating assembly above the processing chamber may project infrared radiation into the chamber to heat the wafer. The wafer may be cooled by optionally spraying de-ionized water and/or nitrogen gas onto the workpiece. A cooling assembly may be used to cool an infrared radiating assembly. Silicon nitride is rapidly removed using very small amounts of phosphoric acid, and without the risks and disadvantages of conventional hot phosphoric bath techniques. | 2012-01-19 |
20120015524 | Process for Enhancing Solubility and Reaction Rates In Supercritical Fluids - Processes for enhancing solubility and the reaction rates in supercritical fluids are provided. In preferred embodiments, such processes provide for the uniform and precise deposition of metal-containing films on semiconductor substrates as well as the uniform and precise removal of materials from such substrates. In one embodiment, the process includes, providing a supercritical fluid containing at least one reactant, the supercritical fluid being maintained at above its critical point, exposing at least a portion of the surface of the semiconductor substrate to the supercritical fluid, applying acoustic energy, and reacting the at least one reactant to cause a change in at least a portion of the surface of the semiconductor substrate. | 2012-01-19 |
20120015525 | METHOD OF CLEANING A THIN FILM FORMING APPARATUS, THIN FILM FORMING METHOD, AND THIN FILM FORMING APPARATUS - A method of cleaning a thin film forming apparatus, for removing deposits adhering to an inside thereof after supplying a film-forming gas into a reaction chamber to form a amorphous carbon film on a workpiece, includes a heating operation of heating at least one of an inside of the reaction chamber and an inside of an exhaust pipe connected to the reaction chamber to a predetermined temperature; and a removing operation of supplying a cleaning gas containing oxygen gas and hydrogen gas into at least one of the inside of the reaction chamber and the inside of the exhaust pipe heated in the heating operation, heating the cleaning gas to the predetermined temperature to activate the oxygen gas and the hydrogen gas contained in the cleaning gas, and thereafter removing the deposits adhering to the inside of the thin film forming apparatus by the oxygen gas and the hydrogen gas activated. | 2012-01-19 |
20120015526 | Silicon Dioxide Deposition Methods Using at Least Ozone and TEOS as Deposition Precursors - Embodiments disclosed herein pertain to silicon dioxide deposition methods using at least ozone and tetraethylorthosilicate (TEOS) as deposition precursors. In one embodiment, a silicon dioxide deposition method using at least ozone and TEOS as deposition precursors includes flowing precursors comprising ozone and TEOS to a substrate under subatmospheric pressure conditions effective to deposit silicon dioxide-comprising material having an outer surface onto the substrate. The outer surface is treated effective to one of add hydroxyl to or remove hydroxyl from the outer surface in comparison to any hydroxyl presence on the outer surface prior to said treating. After the treating, precursors comprising ozone and TEOS are flowed to the substrate under subatmospheric pressure conditions effective to deposit silicon dioxide-comprising material onto the treated outer surface of the substrate. Other embodiments are contemplated. | 2012-01-19 |
20120015527 | Method of Fine Patterning Semiconductor Device - For patterning during integrated circuit fabrication, an image layer is activated for forming a respective first type polymer block at each of two nearest activated areas. A layer of block copolymer is formed on the image layer, and a plurality of the first type polymer blocks and a plurality of second and third types of polymer blocks are formed on an area of the image layer between outer edges of the two nearest activated areas, from the block copolymer. At least one of the first, second, and third types of polymer blocks are removed to form a variety of mask structures. | 2012-01-19 |
20120015528 | CONNECTOR ASSEMBLY - An apparatus includes a connector port. The connector port includes an upright portion configured to connect to a connection of a motherboard and two connection portions extending from the upright portion. An angle between the two connection portions is greater than 0 degrees and less than 180 degrees. Each of the two connection portions are configured to connect with a connector. | 2012-01-19 |
20120015529 | CONTACTING PLUG AS WELL AS CONTACTING CONNECTION - A contacting plug for contacting a contact carrier, in particular a circuit board, having two clamping claws able to be pivoted relative to each other, transversely to a plug-in direction, at least one of which is implemented as contact holder carrying at least one flexible contact element, which contact holder is implemented with a contact force for resting on the contact carrier, and a spring arrangement for generating a clamping force that is independent of the contact force. According to the invention, the spring arrangement is designed for bracing exclusively on the contacting plug for generating the clamping force. | 2012-01-19 |
20120015530 | Electronic apparatus - The embodiments relate to an electronic apparatus having a connector. The electronic apparatus includes a main circuit board configured to have a first face on which a through hole penetrating through the main circuit board is formed and a second face on which the through hole is formed; the connector mounted on the first face; and a supporter including a supporting portion for supporting the connector on the first face of the main circuit board, and a fixing portion having a screw hole overlapping the through hole on a side of the second face, wherein the supporter is fixed to the main circuit board by a screw inserted from a side of the first face into the screw hole while the connector is supported by the supporter. | 2012-01-19 |
20120015531 | PRESS-CONTACTING CONNECTION STRUCTURE OF ELECTRIC WIRE - A press-contacting connection structure of electric wires includes a first cover of a holder, and a second cover of the holder attached to the first holder, and a holder mounting part provided on an electric wire connection target member and configured to be attached to the second cover. The electric wires arranged in parallel with each other are held between the first cover and the second cover so that one side portions of the electric wires extend from one side of the holder and the other side portions of the electric wires extend from the other side of the holder. Ends of the one side portions of the electric wires are folded toward the other side of the holder over the first cover, and are bound by a binding band with the other side portions of the electric wires. A press-contact terminal is inserted into the holder through an opening formed in the second cover when the second cover is attached with the holder mounting part, so that the press-contact terminal is press-contacted to the electric wire accommodated in the holder. | 2012-01-19 |
20120015532 | HIGH DENSITY DECAL AND METHOD FOR ATTACHING SAME - A flexible, high density decal and the use thereof methods of forming detachable electrical interconnections between a flexible chip carrier and a printed wiring board. The flexible decal has fine-pitch pads on a first surface and pads of a pitch wider than the fine pitch on a second surface, the fine-pitch pads on the first surface designed to electrically connect to a semiconductor device, and the wider-pitch pads on the second surface designed to electrically connect to a printed wiring board or the like. The pads on the first surface are conductively wired to the pads on the second surface through one or more insulating levels in the flexible decal. | 2012-01-19 |
20120015533 | TRANSCEIVER ASSEMBLY - A receptacle connector includes a housing having a mating interface for mating with a mating connector. Ground contacts are held by the housing. The ground contacts include ground mating segments arranged along the mating interface of the housing for mating with ground terminals of the mating connector. The ground mating segments of the ground contacts include ground mating surfaces configured to engage the ground terminals. The ground mating surfaces of the ground mating segments extending within at least one ground plane. Signal contacts are held by the housing. The signal contacts include signal mating segments arranged along the mating interface of the housing for mating with signal terminals of the mating connector. The signal mating segments of the signal contacts include signal mating surfaces configured to engage the signal terminals. The signal mating surfaces of the signal contacts extend within at least one signal plane that extends parallel to and is spaced apart from the at least one ground plane. | 2012-01-19 |