03rd week of 2022 patent applcation highlights part 54 |
Patent application number | Title | Published |
20220020591 | METHOD AND DEVICE FOR PLATING A RECESS IN A SUBSTRATE - The teaching relates to a method for plating a recess in a substrate, a device for plating a recess in a substrate and a system for plating a recess in a substrate comprising the device. The method for plating a recess in a substrate includes the following: | 2022-01-20 |
20220020592 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes an n-type semiconductor layer; a first metal layer provided on the n-type semiconductor layer, the first metal layer including first atoms capable of being n-type impurities in the n-type semiconductor layer; a second metal layer provided on the first metal layer, the second metal layer including titanium atoms; a third metal layer provided on the second metal layer; and a second atom capable of being a p-type impurity in the n-type semiconductor layer. The second atom and a part of the titanium atoms are included in a vicinity of an interface between the first metal layer and the second metal layer. | 2022-01-20 |
20220020593 | METHODS FOR FORMING SEMICONDUCTOR DEVICE HAVING UNIFORM FIN PITCH - Disclosed are approaches for forming a semiconductor device. In some embodiments, a method may include providing a patterned hardmask over a substrate, and providing, from an ion source, a plasma treatment to a first section of the patterned hardmask, wherein a second section of the patterned hardmask does not receive the plasma treatment. The method may further include etching the substrate to form a plurality of fins in the substrate, wherein the first section of the patterned hardmask is etched faster than the second section of the patterned hardmask. | 2022-01-20 |
20220020594 | FLOWABLE FILM FORMATION AND TREATMENTS - Exemplary processing methods may include forming a plasma of a silicon-containing precursor. The methods may include depositing a flowable film on a semiconductor substrate with plasma effluents of the silicon-containing precursor. The semiconductor substrate may define a feature within the semiconductor substrate. The methods may include forming a plasma of a hydrogen-containing precursor within the processing region of the semiconductor processing chamber. A bias power may be applied to the substrate support from a bias power source. The methods may include etching the flowable film from a sidewall of the feature within the semiconductor substrate with plasma effluents of the hydrogen-containing precursor. The methods may include densifying remaining flowable film within the feature defined within the semiconductor substrate with plasma effluents of the hydrogen-containing precursor. | 2022-01-20 |
20220020595 | TECHNIQUE FOR SEMICONDUCTOR MANUFACTURING - A technique for semiconductor manufacturing is provided. The technique includes the operations as follows. A semiconductor structure having a first material and a second material is revived. The first material has a first incubation time to a first etching chemistry. The second material has a second incubation time to the first etching chemistry. The first incubation time is shorter than the second incubation time. A first main etch to the semiconductor structure for a first duration by the first etching chemistry is performed. The first duration is greater than the first incubation time and shorter than the second incubation time. | 2022-01-20 |
20220020596 | ETCHING PROCESSING APPARATUS, QUARTZ MEMBER AND PLASMA PROCESSING METHOD - An etching processing apparatus includes a stage configured to receive a substrate, a chamber configured to contain the stage, and a plasma generator configured to generate plasma in the chamber. An annular quartz member is disposed in a space in which the plasma is generated. The annular quartz member includes a surface facing the space. A coating film covers the surface of the quartz member. The coating film is made of a material other than quartz, and has a thickness of 10 nm or more and less than 800 nm. | 2022-01-20 |
20220020597 | PLASMA ETCHING APPARATUS, PLASMA ETCHING METHOD, AND SEMICONDUCTOR DEVICE FABRICATION METHOD INCLUDING THE PLASMA ETCHING METHOD - Disclosed are plasma etching apparatuses, plasma etching methods, and semiconductor device fabrication methods. The plasma etching apparatus comprises a chamber, an electrostatic chuck in a lower portion of the chamber, a radio-frequency power supply that has a connection with the electrostatic chuck and provides the electrostatic chuck with a radio-frequency power to generate a plasma in the chamber, and a controller that has a connection with the radio-frequency power supply and controls the radio-frequency power. | 2022-01-20 |
20220020598 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING METHOD, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM - There is provided a technique that includes: etching a first film exposed on a surface of a substrate by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing: (a) forming a first modified layer in at least a portion of a surface of the first film by supplying a first gas to the substrate; and (b) etching at least a portion of the first film with an etching species, the etching species being generated by supplying a second gas having a molecular structure different from that of the first gas to the substrate to perform at least one selected from the group of causing the second gas to react with the first modified layer and activating the first modified layer with the second gas. | 2022-01-20 |
20220020599 | INTEGRATION PROCESSES UTILIZING BORON-DOPED SILICON MATERIALS - Exemplary processing methods may include depositing a boron-containing material or a silicon-and-boron-containing material on a substrate disposed within a processing region of a semiconductor processing chamber. The methods may include etching portions of the boron-containing material or the silicon-and-boron-containing material with a chlorine-containing precursor to form one or more features in the substrate. The methods may also include removing remaining portions of the boron-containing material or the silicon-and-boron-containing material from the substrate with a fluorine-containing precursor. | 2022-01-20 |
20220020600 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A method for manufacturing a semiconductor structure includes: a substrate with a groove structure formed therein is provided; a laminated structure is formed on the substrate, which includes a first conductive material layer, a second conductive material layer and an insulating material layer from bottom up, and the first conductive material layer fills the groove structure and covers the surface of the substrate; the insulating material layer, the second conductive material layer and the first conductive material layer are sequentially etched to form a bit line structure, in which a process of etching the first conductive material layer includes a first etching stage and a second etching stage, such that a bottom width of the first pattern structure located in the groove structure is not smaller than that of the first pattern structure located outside the groove structure. | 2022-01-20 |
20220020601 | ETCHING METHOD AND ETCHING APPARATUS - An etching method includes: providing, in a chamber, a substrate including a structure including a first film selected from a molybdenum film and a tungsten film; performing a first etching on the first film by supplying an oxidation gas and a first gas selected from a MoF | 2022-01-20 |
20220020602 | METHOD FOR PRODUCING PACKAGE SUBSTRATE FOR LOADING SEMICONDUCTOR DEVICE - A method for manufacturing a package substrate including an insulating layer and a wiring conductor, including: forming, on one or both sides of a core resin layer, a substrate including a peelable first metal layer that has a thickness of 1-70 μm, a first insulating resin layer, and a second metal layer; forming a non-through hole reaching a surface of the first metal layer, performing electrolytic and/or electroless copper plating on its inner wall, and connecting the second and first metal layers; arranging a second insulating resin layer and a third metal layer and heating and pressurizing the first substrate to form a substrate; forming a non-through hole reaching a surface of the second metal layer, performing electrolytic and/or electroless copper plating on its inner wall, and connecting the second and third metal layers; peeling a third substrate; and patterning the first and third metal layers to form the wiring conductor. | 2022-01-20 |
20220020603 | SHEET AND PROTECTIVE MEMBER FORMING METHOD - There is provided a sheet used at a time of formation of a protective member protecting one surface of a plate-shaped workpiece by spreading and curing a liquid resin on the one surface. The sheet includes a first layer configured to be brought into contact with a flat specular mounting surface, and a second layer configured to be brought into contact with the liquid resin. The first layer is formed of a material that is easily separated from the mounting surface after adhering to the mounting surface as compared with the second layer, and the second layer is formed of a material having high adhesiveness to the cured resin as compared with the first layer. | 2022-01-20 |
20220020604 | SEMICONDUCTOR DEVICE - A semiconductor device includes a package substrate, a semiconductor chip and a solder bump. The semiconductor chip is disposed on the package substrate. The package substrate includes a first electrode pad, and a first insulating film formed such that the first insulating film exposes a first portion of a surface of the first electrode pad. The semiconductor chip includes a second electrode pad and a second insulating film formed such that the second insulating film exposes a second portion of a surface of the second electrode pad. The second electrode pad is formed on the first electrode pad through the solder bump. L | 2022-01-20 |
20220020605 | SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package structure and a method of manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a conductive base, a first semiconductor die, a first conductive pillar, and a first encapsulant. The conductive base has a first surface. The first semiconductor die is disposed on the first surface of the conductive base. The first conductive pillar is disposed on the first semiconductor die. The first encapsulant is disposed on the first surface of the conductive base. The first encapsulant encapsulates the first semiconductor die. The first encapsulant includes an opening defined by the first conductive pillar. | 2022-01-20 |
20220020606 | TEMPORARY PROTECTIVE FILM FOR SEMICONDUCTOR ENCAPSULATION MOLDING, LEAD FRAME PROVIDED WITH TEMPORARY PROTECTIVE FILM, ENCAPSULATED MOLDED BODY PROVIDED WITH TEMPORARY PROTECTIVE FILM, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A temporary protective film for semiconductor sealing molding includes a support film and an adhesive layer provided on one surface or both surfaces of the support film and containing a resin and a silane coupling agent. The content of the silane coupling agent in the temporary protective film may be more than 5% by mass and less than or equal to 35% by mass with respect to the total mass of the resin. | 2022-01-20 |
20220020607 | PROTECTIVE COMPONENT FORMING APPARATUS - A protective component forming apparatus includes a chuck table, a resin supply unit having a pump and a pipe that supply a liquid resin from a tank to a resin sheet held by the chuck table, a pressing unit that presses a workpiece against the liquid resin supplied to the resin sheet held by the chuck table, a curing unit that irradiates the liquid resin pressed by the pressing unit with ultraviolet and cures the liquid resin, a resin inspecting part that senses the viscosity of the liquid resin, and an informing unit. | 2022-01-20 |
20220020608 | SYSTEM AND METHOD FOR SUPPLYING CHEMICAL SOLUTION - A system includes a chemical storage tank, a pipeline, a pump, a first electrostatic probe, and a control unit. The pipeline is connected to the chemical storage tank. The pump is connected to the pipeline and configured to pump a chemical solution from the chemical storage tank into the pipeline. The first electrostatic probe is coupled to the pump and configured to measure an electrostatic voltage of the pump. The control unit is coupled to the first electrostatic probe and configured to obtain a measurement of an electrostatic voltage from the first electrostatic probe. | 2022-01-20 |
20220020609 | SUBSTRATE TREATING APPARATUS - An apparatus for treating a substrate using a treating fluid in a supercritical state is provided. In a pressure increasing step of increasing a pressure in the treating space from a pressure lower than a critical pressure of the treating fluid to a treating pressure higher than the critical pressure, the apparatus controls a supply amount of the treating fluid supplied from a first supply port to control flow of the treating fluid supplied from the first supply port and then exhausted through an exhaust port. | 2022-01-20 |
20220020610 | SUBSTRATE CLEANING DEVICE AND SUBSTRATE CLEANING METHOD - A substrate cleaning device includes: a pressing member that cleans a substrate by contacting the substrate; a load measurement unit that measures a pressing load of the cleaning member; and a control unit that repeats an operation of comparing the measurement value of the load measurement unit with the setting load, changing the pressing amount of the cleaning member by a first movement amount so that a difference value decreases, when the difference value is larger than a first threshold value and equal to or smaller than a second threshold value, and changing the pressing amount of the cleaning member by a second movement amount larger than the first movement amount so that the difference value decreases, when the difference value is larger than the second threshold value, until the difference value becomes equal to or smaller than the first threshold value. | 2022-01-20 |
20220020611 | SUBSTRATE PROCESSING METHOD - A substrate processing method includes forming, by supplying a chemical liquid onto a central portion of a substrate while rotating a rotary table at a first speed, a liquid film of the chemical liquid having a first thickness; forming, by supplying the chemical liquid onto the central portion while rotating the rotary table at a second speed lower than the first speed after the forming of the liquid film having the first thickness, a liquid film of the chemical liquid having a second thickness larger than the first thickness; and heating, by heating the rotary table in a state that the rotary table is rotated at a third speed lower than the second speed or in a state that the rotating of the rotary table is stopped after the forming of the liquid film having the second thickness, the substrate and the liquid film of the chemical liquid. | 2022-01-20 |
20220020612 | SYSTEMS AND METHODS FOR FACEPLATE TEMPERATURE CONTROL - Exemplary semiconductor processing systems may include a chamber body including sidewalls and a base. The chamber body may define an interior volume. The processing systems may include a substrate support extending through the base of the chamber body. The substrate support may be configured to support a substrate within the interior volume. The processing systems may include a faceplate positioned within the interior volume of the chamber body. The faceplate may define a plurality of apertures through the faceplate. The processing systems may include a faceplate heater seated on the faceplate. The faceplate heater may include a first heater coil extending proximate a first area of the faceplate. The faceplate heater may include a second heater coil extending proximate a second area of the faceplate. | 2022-01-20 |
20220020613 | STACKED THERMAL PROCESSING CHAMBER MODULES FOR REMOTE RADIATIVE HEATING IN SEMICONDUCTOR DEVICE MANUFACTURE - Stacked thermal process chamber module for remote radiative heating of semiconductor device workpieces. A stacked thermal process module may include a stack of thermal process chambers and one or more generators of electromagnetic radiation. The electromagnetic radiation may be transported from a generator remote from the process chambers through one or more waveguides, thereby minimizing the volume and/or cleanroom footprint of the stacked thermal process chamber module. A waveguide may terminate in a process chamber so that electromagnetic radiation delivered during a thermal process may be coupled into one or more materials of the workpiece. The radiative heating process may overcome many of the limitations of thermal process chambers that instead employ a local heat source located within a process chamber. | 2022-01-20 |
20220020614 | PROCESSING APPARATUS - A processing apparatus includes a wafer conveying-out mechanism; a wafer table; a frame conveying-out mechanism; a frame table; a tape attaching mechanism that attaches a tape to a frame; a tape-attached frame conveying mechanism that conveys the tape-attached frame; a tape pressure bonding mechanism that pressure bonds the tape of the tape-attached frame to a back surface of a wafer; a frame unit conveying-out mechanism that conveys out a frame unit in which the tape of the tape-attached frame and the back surface of the wafer are pressure bonded; a reinforcement section removing mechanism that cuts and removes a ring-shaped reinforcement section from the wafer; a ringless unit conveying-out mechanism that conveys out a ringless unit from which the reinforcement section has been removed; and a frame cassette table on which a frame cassette accommodating the ringless unit is to be placed. | 2022-01-20 |
20220020615 | MULTIPLE PROCESS SEMICONDUCTOR PROCESSING SYSTEM - Exemplary substrate processing systems may include a plurality of processing regions. The systems may include a transfer region housing defining a transfer region fluidly coupled with the plurality of processing regions. The systems may include a plurality of substrate supports. Each substrate support of the plurality of substrate supports may be vertically translatable between the transfer region and an associated processing region of the plurality of processing regions. The systems may include a transfer apparatus including a rotatable shaft extending through the transfer region housing. The transfer apparatus may also include an end effector coupled with the rotatable shaft. The systems may include an exhaust foreline including a plurality of foreline tails. Each foreline tail of the plurality of foreline tails may be fluidly coupled with a separate processing region of the plurality of processing regions. The systems may include a plurality of throttle valves. | 2022-01-20 |
20220020616 | SUBSTRATE PROCESSING DEVICE - A substrate processing device is a device continuously performing wet processing and dry processing. The substrate processing device includes a plurality of processing modules. Each of the plurality of processing modules includes a single wet processing unit performing wet processing on a substrate; a single dry processing unit performing dry processing on a substrate; and a single transfer unit located between the wet processing unit and the dry processing unit to transfer a substrate between the wet processing unit and the dry processing unit. | 2022-01-20 |
20220020617 | LOW OPEN AREA AND COUPON ENDPOINT DETECTION - The disclosure describes apparatus and method for detecting an endpoint in plasma-assisted wafer processing in a chamber. A fiber array comprising a plurality of fibers collects optical emission light from the chamber during the plasma-assisted wafer processing. The fiber array is split into two or more groups of fibers, each group carrying a portion of the light to a segment of a photodetector. Each segment of photodetector has a corresponding narrowband optical filter designed for a specific range of wavelengths. A computer processor analyzes detected signals from the plurality of segments of the photodetector, and determines, based on the analysis of the detected signals, an endpoint of the plasma-assisted wafer processing as indicated by the presence or the absence of the one or more chemical species in the chamber. The photodetector can be based on photomultiplier tube (PMT) array or based on photodiodes (e.g., avalanche photodiodes (APDs)). | 2022-01-20 |
20220020618 | CONTROL DEVICE, SYSTEM AND CONTROL METHOD - A control device includes a reception unit configured to receive a film characteristic at a plurality of positions of a film formed on a substrate by a film forming processing based on a processing recipe, an optimization processing unit configured to execute an optimization calculation of the processing recipe based on the film characteristic, a diagnosis unit configured to diagnose a validity of an in-plane shape of the film characteristic based on the film characteristic, and a determination unit configured to determine whether or not to notify a user of an encouraging action based on a diagnosis result by the diagnosis unit. | 2022-01-20 |
20220020619 | CHIP-TRANSFERRING SYSTEM AND CHIP-TRANSFERRING METHOD - A chip-transferring system and a chip-transferring method are provided. The chip-transferring system includes a substrate-carrying module for carrying a chip-carrying structure, a chip-transferring module, and a system control module. The chip-carrying structure includes a circuit substrate for carrying a plurality of conductive materials, a plurality of micro heaters, and a micro heater control chip. The chip-transferring module is configured for transferring a chip onto two corresponding ones of the conductive materials, and the chip-transferring module includes a motion sensing chip. When chip movement information of the chip that is provided by the motion sensing chip is transmitted to the system control module, the micro heater control chip is configured to control a corresponding one of the micro heaters to start or stop heating the two corresponding conductive materials by control of the system control module according to the chip movement information of the chip. | 2022-01-20 |
20220020620 | LOAD PORT DEVICE, GAS GATE AND GAS-PROVIDING METHOD - The present disclosure provides a load port device, a gas gate and a gas-providing method. The load port device includes a gas-providing nozzle and the gas gate. The gas-providing nozzle is used for providing gas to a wafer container. The gas gate includes a plurality of gas inlet ports, a gas-providing port and a controller. Each gas inlet port connects to a gas source. The gas-providing port connects to the gas-providing nozzle. The controller is configured to: select one of the plurality of gas inlet ports; and connect the selected gas inlet port to the gas-providing port. | 2022-01-20 |
20220020621 | CEILING CONVEYANCE VEHICLE AND CEILING CONVEYANCE VEHICLE SYSTEM - A ceiling conveyance vehicle includes a traveling wheel to roll on a track including a first track and a second track and a main body below the track and coupled to the traveling wheel. The ceiling conveyance vehicle includes a direction changer to change between a first state in which the traveling wheel rolls on the first track and a second state in which the traveling wheel rolls on the second track, with an orientation of the main body with respect to the track maintained, an article holder capable of holding an article, a hoisting-and-lowering driver to hoist and lower the article holder, a lateral slider to slidingly move the hoisting-and-lowering driver in a horizontal, linear direction, and a first rotational driver to rotationally drive the lateral slider around a first perpendicular axis with respect to the main body. | 2022-01-20 |
20220020622 | SUBSTRATE TRANSPORT SYSTEM AND SUBSTRATE TRANSPORT METHOD - A substrate transport system for transporting a substrate in a vacuum atmosphere includes a vacuum chamber, inside of which is configured to be capable of being set to a vacuum atmosphere, a transport arm provided inside the vacuum chamber and configured to hold and transport the substrate, a horizontal movement mechanism configured to move the transport arm in a horizontal direction inside the vacuum chamber, a horizontal duct arm mechanism including therein an accommodation portion having a normal pressure atmosphere, the horizontal duct arm mechanism being configured to be extendable/contractible as the transport arm moves horizontally, a vertical movement mechanism configured to move the transport arm in a vertical direction inside the vacuum chamber, and a vertical duct arm mechanism including therein an accommodation portion having a normal pressure atmosphere, the vertical duct arm mechanism being configured to be extendable/contractible as the transport arm moves vertically. | 2022-01-20 |
20220020623 | SUBSTRATE TRANSFERRING DEVICE AND METHOD OF OPERATING THE SAME - A substrate transferring device is configured to transfer a substrate while holding it. The substrate transferring device includes a hand configured to hold the substrate, a manipulator to which the hand is attached, and a substrate detector provided to the hand and configured to detect a distance to a principal surface of the substrate. Preferably, the substrate detector is provided to a tip-end part of the hand. Preferably, the substrate detector is a capacitive sensor. | 2022-01-20 |
20220020624 | WAFER TO WAFER BONDING APPARATUS AND WAFER TO WAFER BONDING METHOD - A wafer bonding apparatus including a first stage having a first surface and being configured to hold a first wafer on the first surface; a second stage having a second surface and being configured to hold a second wafer on the second surface facing the first surface; a first target image sensor on an outer portion of the first stage; a second target image sensor on an outer portion of the second stage; and a target portion on the first or second stage, the target portion having a target plate fixedly installed and spaced apart from the first or second target image sensor by a predetermined distance, wherein, in an alignment measurement of the first and second stages, the first and second stages are movable so that the first and second target image sensors face each other and the target plate is between the first and second target image sensors. | 2022-01-20 |
20220020625 | DEVICE-LIKE OVERLAY METROLOGY TARGETS DISPLAYING MOIRE EFFECTS - A metrology system and metrology methods are disclosed. The metrology system comprises a set of device features on a first layer of a sample, a first set of target features on a second layer of the sample and overlapping the set of device features, and a second set of target features on the second layer of the sample and overlapping the set of device features. Relative positions of a first set of Moiré fringes and a second set of Moiré fringes indicate overlay error between the first layer of the sample and the second layer of the sample. | 2022-01-20 |
20220020626 | SEMICONDUCTIVE CERAMIC MEMBER - A semiconductive ceramic member according to the present disclosure contains a plurality of aluminum oxide crystal grains, and a plurality of titanium oxide crystal grains. The total content of aluminum oxide and titanium oxide is 99% by mass or more per 100% by mass of all constituents. The content of the aluminum oxide is 86% by mass or more and 96% by mass or less and the content of the titanium oxide is 4% by mass or more and 14% by mass or less per 100% by mass of the aluminum oxide and the titanium oxide in total. A peak of TiO | 2022-01-20 |
20220020627 | PROCESSING TAPE AND METHOD OF FABRICATING A SEMICONDUCTOR DEVICE USING THE SAME - A processing tape may include a base layer, an adhesive layer disposed on the base layer, a protection release film on the adhesive layer, and a first release layer interposed between the adhesive layer and the protection release film. The first release layer may include a silicone-based material and may be non-photo-curable. | 2022-01-20 |
20220020628 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device, including preparing a semiconductor wafer having a first main surface and a second main surface opposite to each other, forming a first electrode on the first main surface of the semiconductor wafer, applying a first tape to the second main surface of the semiconductor wafer, so as to cover the second main surface of the semiconductor wafer with the first tape, applying a second tape to an outer peripheral portion of the semiconductor wafer, to thereby cover an end of the semiconductor wafer with the second tape, heating the semiconductor wafer having the first tape and the second tape applied thereto, by a heat treatment at a temperature of at least 40 degrees C., and forming a plating layer on a surface of the first electrode after heating the semiconductor wafer. | 2022-01-20 |
20220020629 | PIN LIFTING DEVICE HAVING A TEMPERATURE SENSOR - Disclosed is a pin lifting device is designed for moving and positioning a substrate to be processed in a vacuum process chamber. The pin lifting device includes a coupling part having a coupling adapted to receive a support pin designed to contact and support the substrate, and further comprises a drive part having a drive unit adapted to cooperate with the coupling such that the coupling is linearly adjustable along an adjustment axis from a lowered normal position to an extended support position and back The pin lifting device has at least one temperature sensor, where the temperature sensor is designed and arranged such that a measurement signal representing thermal information with respect to at least part of the pin lifting device can be generated by means of the temperature sensor. | 2022-01-20 |
20220020630 | MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE - A manufacturing method of a semiconductor structure includes the following steps. A substrate is provided. A barrier layer is formed on the substrate. A sacrificial layer is formed on the barrier layer. An opening pattern is formed over the sacrificial layer by utilizing a photolithography process. The sacrificial layer is etched according to the opening pattern to form first trenches by using the barrier layer as an etch stop layer. A medium layer material is filled in the first trenches. The sacrificial layer is etched to form second trenches by using the barrier layer as the etch stop layer. A hard mask layer material is filled in the second trenches. The medium layer material is etched to form a hard mask layer by using the barrier layer as the etch stop layer. | 2022-01-20 |
20220020631 | INTEGRATED CIRCUIT STRUCTURE AND METHOD FOR PREPARING THE SAME - The present disclosure provides an integrated circuit structure with dielectric isolation structure for reducing capacitive coupling and crosstalk between conductive features and a method for preparing the same. The method includes: forming a first conductive structure over a substrate; forming a first dielectric structure over the first conductive structure; transforming a sidewall portion of the first conductive structure into a first dielectric portion; removing the first dielectric portion such that a width of the first dielectric structure is greater than a width of a remaining portion of the first conductive structure; forming an inter-layer dielectric (ILD) layer covering a sidewall of the first dielectric structure; forming a reinforcement pillar of energy removable material in the ILD layer; forming a capping dielectric layer over the reinforcement pillar; and performing a thermal process to transform the reinforcement pillar into a dielectric isolation structure including a liner layer enclosing an air gap. | 2022-01-20 |
20220020632 | FORMATION METHOD FOR AIR SPACER LAYER AND SEMICONDUCTOR STRUCTURE - The present application relates to a formation method for an air spacer layer and a semiconductor structure. The formation method for an air spacer layer includes: forming a first structure on a substrate and forming a second structure on the substrate, the second structure being located on a side surface of the first structure, a first trench being formed between the second structure and the first structure, and the second structure being exposed in the first trench; and growing, by an epitaxial growth process, an epitaxial layer on the second structure exposed in the first trench, the epitaxial layer not filling up the first trench, and an unfilled portion of the first trench forming the air spacer layer. | 2022-01-20 |
20220020633 | Body-Source-Tied Semiconductor-On-Insulator (SOI) Transistor - A semiconductor-on-insulator (SOI) transistor includes a semiconductor layer situated over a buried oxide layer, the buried oxide layer being situated over a substrate. The SOI transistor is situated in the semiconductor layer and includes a transistor body, gate fingers, source regions, and drain regions. The transistor body has a first conductivity type. The source regions and the drain regions have a second conductivity type opposite to the first conductivity type. A heavily-doped body-implant region has the first conductivity type and overlaps at least one source region. A common silicided region electrically ties the heavily-doped body-implant region to the at least one source region. The common silicided region can include a source silicided region, and a body tie silicided region situated over the heavily-doped body-implant region. The source silicided region can be separated from a drain silicided region by the gate fingers. | 2022-01-20 |
20220020634 | Partial Wrap Around Top Contact - Contact designs for semiconductor FET devices are provided. In one aspect, a contact structure includes: a metal line(s); a first ILD surrounding the metal line(s), wherein a top surface of the first ILD is recessed below a top surface of the metal line(s); a liner disposed on the first ILD and on portions of the metal line(s); a top contact(s) disposed over, and in direct contact with, the metal line(s), wherein an upper portion of the top contact(s) has a width W | 2022-01-20 |
20220020635 | NANOSCALE RESOLUTION, SPATIALLY-CONTROLLED CONDUCTIVITY MODULATION OF DIELECTRIC MATERIALS USING A FOCUSED ION BEAM - Methods for creating a conductive feature in a dielectric material are provided. In an embodiment, such a method comprises irradiating a region of a dielectric material having a resistivity of at least 10 | 2022-01-20 |
20220020636 | SEMICONDUCTOR DEVICE WITH MULTI-LAYER CONNECTING STRUCTURE AND METHOD FOR FABRICATING THE SAME - The present application discloses a semiconductor device with the multi-layered connecting structure and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a single-layered connecting structure positioned above the substrate, and a multi-layered connecting structure positioned above the substrate and including a plurality of first conductive layers and a plurality of second conductive layers alternatively stacked. A top surface of the multi-layered connecting structure is substantially coplanar with a top surface of the single-layered connecting structure and a width of the multi-layered connecting structure is less than a width of the single-layered connecting structure. | 2022-01-20 |
20220020637 | METHOD FOR PREPARING SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE - A method for preparing a semiconductor structure and the semiconductor structure are provided. The method for preparing the semiconductor structure comprises: providing a semiconductor substrate and forming a conductive layer on the semiconductor substrate; forming a first protective layer on a surface of the conductive layer; performing a passivation treatment on the first protective layer to enable the first protective layer to form a passivation layer, wherein the passivation layer comprises a multilayer thin film structure and ion concentrations of the multilayer thin film structure are not the same; forming an insulation layer on the passivation layer; and sequentially forming a barrier layer and a second protective layer on the insulation layer. | 2022-01-20 |
20220020638 | Interconnect Structures with Selective Barrier for BEOL Applications - Interconnect structures with selective barrier for back-end-of-line (BEOL) applications are provided. In one aspect, an interconnect structure includes: a dielectric disposed over at least one metal line; at least one feature present in the dielectric over the at least one metal line; a barrier layer lining only surfaces of the dielectric within the at least one feature; at least one interconnect present in the at least one feature over the barrier layer, wherein the at least one interconnect is in direct contact with the at least one feature. A method of forming an interconnect structure is also provided. | 2022-01-20 |
20220020639 | Contact plug structure and manufacturing method thereof - The invention provides a contact plug structure. The contact plug structure comprises a substrate and a dielectric layer, and a first contact hole located in the dielectric layer and penetrating into the substrate, the first contact hole has a first through hole portion located in the dielectric layer and a first groove located in the substrate, and the first through hole portion is communicated with the first groove, the maximum width of the first groove is larger than that of the first through hole portion in the direction parallel to the substrate surface. A barrier layer at least partially covering the sidewall of the first groove. A conductive pad layer is located on the bottom surface of the first groove. The conductive core layer is arranged on the conductive pad layer, and the barrier layer wraps the conductive pad layer and the conductive core layer. | 2022-01-20 |
20220020640 | INTERCONNECTION ELEMENT AND METHOD OF MANUFACTURING THE SAME - An interconnection element of an interconnection structure of an integrated circuit is manufactures by a method where a cavity is etched in an insulating layer. A silicon nitride layer is then deposited on walls and a bottom of the cavity. The nitrogen atom concentration in the silicon nitride layer increasing as a distance from an exposed surface of the silicon nitride layer increases. A copper layer is deposited on the silicon nitride layer. The cavity is further filled with copper. A heating process is performed after the deposition of the copper layer, to convert the copper layer and the silicon nitride layer to form a copper silicide layer which has a nitrogen atom concentration gradient corresponding to the gradient of the silicon nitride layer. | 2022-01-20 |
20220020641 | VOID FREE LOW STRESS FILL - Provided herein are methods of depositing low stress and void free metal films in deep features and related apparatus. Embodiments of the methods include treating the sidewalls of the holes to inhibit metal deposition while leaving the feature bottom untreated. In subsequent deposition operations, metal precursor molecules diffuse to the feature bottom for deposition. The process is repeated with subsequent inhibition operations treating the remaining exposed sidewalls. By repeating inhibition and deposition operations, high quality void free fill can be achieved. This allows high temperature, low stress deposition to be performed. | 2022-01-20 |
20220020642 | ALD (ATOMIC LAYER DEPOSITION) LINER FOR VIA PROFILE CONTROL AND RELATED APPLICATIONS - Methods are disclosed that provide improved via profile control by forming atomic layer deposition (ALD) liners to protect side walls of vias during subsequent etch processes. ALD liners can be used for BEOL etch processes as well as for full self-aligned via (FSAV) processes and/or other processes. For one embodiment, ALD liners are used as protection or sacrificial layers for vias to reduce damage during multilayer via or trench etch processes. The ALD liners can also be deposited at different points within process flows, for example, before or after removal of organic planarization layers. The use of ALD liners facilitates shrinking of via critical dimensions (CDs) while still controlling via profiles for various process applications including dual Damascene processes and FSAV processes. In addition, the use of ALD liners improves overall CD control for via or hole formation as well as device yield and reliability. | 2022-01-20 |
20220020643 | PROTECTIVE FILM FORMING AGENT FOR PLASMA DICING AND METHOD FOR MANUFACTURING SEMICONDUCTOR CHIP - A protective film forming agent for plasma dicing which can favorably form an opening (processed groove) of a desired shape by irradiation of a laser beam, at a desired position of the protective film, upon producing semiconductor chips by cutting a semiconductor substrate by plasma dicing, and a method for producing a semiconductor chip using this protective film forming agent. The protective film forming agent comprises a water-soluble resin, a light absorber, and a solvent, and a weight loss rate when the temperature is raised to 500° C. in thermogravimetry of the water-soluble resin is at least 80 weight %. | 2022-01-20 |
20220020644 | SPACER STRUCTURE FOR SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a first channel layer and a sacrificial layer. The method can further include forming a first recess structure in a first portion of the fin structure, forming a second recess structure in the sacrificial layer of a second portion of the fin structure, forming a dielectric layer in the first and second recess structures, and performing an oxygen-free cyclic etching process to etch the dielectric layer to expose the channel layer of the second portion of the fin structure. The process of performing the oxygen-free cyclic etching process can include performing a first etching process to selectively etch the dielectric layer over the channel layer of the second portion of the fin structure with a first etching selectivity, and performing a second etching process to selectively etch the dielectric layer over the channel layer of the second portion of fin structure with a second etching selectivity greater than the first etching selectivity | 2022-01-20 |
20220020645 | STRUCTURES AND METHODS OF FABRICATING ELECTRONIC DEVICES USING SEPARATION AND CHARGE DEPLETION TECHNIQUES - A method of fabricating an electronic device can include forming a plurality of vertical channels having sidewalls over a substrate, and forming gate dielectric regions over portions of the vertical channels and planar regions adjoining the vertical channels. Gate electrode regions are then formed over portions of the gate dielectric regions. The gate electrode material and the vertical channel region are doped and sized to enable full depletion of charges during operation. Source and body tie regions are formed on the vertical sidewalls by doping with a p-type or n-type dopant. Dielectric regions over the gate electrode regions are formed to electrically isolate the gate electrode regions from the source regions. A metallic layer is formed over the first side of the substrate having the vertical channels. Stress is then induced within the substrate by annealing and/or cooling to separate a semiconductor region of the substrate and the metallic layer from the remaining portion of the substrate. Drain electrode contacts are formed over the semiconductor region while gate electrode and source electrode contacts are formed by etching portions of a metallic layer formed over the first side of the substrate. | 2022-01-20 |
20220020646 | EPITAXIAL GROWTH OF SOURCE AND DRAIN MATERIALS IN A COMPLEMENTARY FIELD EFFECT TRANSISTOR (CFET) - A method of performing epitaxial growth of a source and drain on levels of a complementary field effect transistor (CFET) is provided. The method includes depositing a first blocking material in a vertical channel of an unfinished CFET structure, oxidizing silicon at a surface of an upper level of the CFET to provide one or more SiO | 2022-01-20 |
20220020647 | SELF-LIMITING MANUFACTURING TECHNIQUES TO PREVENT ELECTRICAL SHORTS IN A COMPLEMENTARY FIELD EFFECT TRANSISTOR (CFET) - A method of forming a complementary field effect transistor (CFET) is provided. The method includes adding a blocking material to a vertical channel of the CFET having an epitaxial growth, the blocking material being located below and in contact with a lower portion of the growth, adding an insulating material to an open area within the vertical channel to surround a portion of the epitaxial growth, performing an etch to (i) remove a portion of the insulating material, (ii) expose a contact surface of the epitaxial growth and (iii) provide a vertical opening within the vertical channel, the etch leaving a portion of the blocking material, and filling in the vertical opening with a conductive material, the conductive material reaching the exposed contact surface of the epitaxial growth, the blocking material remaining below the conductive material to prevent contact between the conductive material and a silicon substrate below the growth. | 2022-01-20 |
20220020648 | DEVICE AND METHOD USED FOR MEASURING WAFERS - The present disclosure relates to a device and method for measuring wafers. The device comprises: a moving platform, which is used to adjust the location of wafers; a first pre-alignment module and a first image recognition module, which are used to align a first wafer at a first location on the moving platform before measuring the first wafer; a second pre-alignment module and a second image recognition module, which are used to align a second wafer at a second location on the moving platform before measuring the second wafer; and a measurement module, which is used to measure the first wafer and the second wafer at a third location on the moving platform, wherein the first location, second location and third location are different from each other. The embodiments of the present disclosure may improve the measurement efficiency of the device. | 2022-01-20 |
20220020649 | Wavelet System and Method for Ameliorating Misregistration and Asymmetry of Semiconductor Devices - A wavelet-analysis system and method for use in fabricating semiconductor device wafers, the system including a misregistration metrology tool operative to measure at least one measurement site on a wafer, thereby generating an output signal, and a wavelet-based analysis engine operative to generate at least one wavelet-transformed signal by applying at least one wavelet transformation to the output signal and generate a quality metric by analyzing the wavelet-transformed signal. | 2022-01-20 |
20220020650 | DEFECTIVE CHIP PROCESSING METHOD - When a chip, or manufactured integrate circuit, is found to have a portion that is defective, “floorsweeping” may be used to salvage the working portion of the chip. Floorsweeping involves downgrading, or turning off, the portion of the chip with the defect and then operating the remaining portion of the chip as a lower quality chip than the larger chip that was originally intended. In use, applications will then only use the active portion of the chip. However, the resulting lower quality chip will still have the same static leakage of the larger, non-defective chip. This leakage results from a voltage still being applied to the entire area of the larger chip, even though a portion of that area has been downgraded. The present disclosure provides a method for processing defective chips to form a smaller chip that avoids the excess static leakage associated with floorsweeping by physically removing the defective portion of the chip. | 2022-01-20 |
20220020651 | POWER SEMICONDUCTOR MODULE AND MANUFACTURING METHOD FOR POWER SEMICONDUCTOR MODULE - A frame is made of a first material. An external terminal electrode is attached to the frame. A heat sink plate supports the frame and includes a mounting region in the frame. The heat sink plate is made of a non-composite material containing copper with purity of 95.0 weight percentage or more. A first adhesive layer bonds the frame and the heat sink plate to each other. The first adhesive layer is made of a second material different from the first material, and has a first composition. A power semiconductor element is mounted on the mounting region of the heat sink plate. A cover is attached to the frame to constitute a sealing space sealing the power semiconductor element without gross leak. A second adhesive layer bonds the frame and the cover to each other, and has a second composition different from the first composition of the first adhesive layer. | 2022-01-20 |
20220020652 | ELECTRONIC CHIP PACKAGE HAVING A SUPPORT AND A CONDUCTIVE LAYER ON THE SUPPORT - The invention concerns a device comprising a support, an electrically-conductive layer covering the support, a semiconductor substrate on the conductive layer, and an insulating casing. | 2022-01-20 |
20220020653 | SEMICONDUCTOR PACKAGE - A semiconductor package including a package substrate, a semiconductor chip on a top surface of the package substrate, a connection terminal between the package substrate and the semiconductor chip, the connection terminal connecting the package substrate to the semiconductor chip, a non-conductive film (NCF) between the package substrate and semiconductor chip, the NCF surrounding the connection terminal and bonding the semiconductor chip to the package substrate, and a side encapsulation material covering a side surface of the semiconductor chip, contacting the package substrate, and including a first portion between a bottom surface of the semiconductor chip and the top surface of the package substrate may be provided. At least a portion of the NCF includes a second portion that horizontally protrudes from the semiconductor chip when viewed, and a portion of the side encapsulation material is in contact with the bottom surface of the semiconductor chip. | 2022-01-20 |
20220020654 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes a first substrate, a second substrate, and a barrier structure. The first substrate has a first surface and a second surface opposite to the first surface. The second substrate has a first surface facing the second surface of the first substrate. The first substrate electrically bonds to the second substrate through a conductive terminal disposed between the second surface of the first substrate and the first surface of the second substrate. The barrier structure is disposed adjacent to the first surface of the first substrate. | 2022-01-20 |
20220020655 | SEMICONDUCTOR PACKAGES AND METHODS OF FORMING THE SAME - A semiconductor package includes a circuit board structure, a first redistribution layer structure and first bonding elements. The circuit board structure includes outermost first conductive patterns and a first mask layer adjacent to the outermost first conductive patterns. The first redistribution layer structure is disposed over the circuit board structure. The first bonding elements are disposed between and electrically connected to the first redistribution layer structure and the outermost first conductive patterns of the circuit board structure. In some embodiments, at least one of the first bonding elements covers a top and a sidewall of the corresponding outermost first conductive pattern. | 2022-01-20 |
20220020656 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - Disclosed is a semiconductor package comprising a lower substrate including a conductive line; a first semiconductor chip on the lower substrate; an under-fill layer between the first semiconductor chip and the lower substrate, the under-fill layer including a central part below the first semiconductor chip and an edge part isolated from direct contact with the central part in a first direction parallel to a top surface of the lower substrate, and a recess region between the central part and the edge part. The recess region may be defined by a sidewall of the central part, a sidewall of the edge part, and a top surface of the conductive line in the lower substrate. | 2022-01-20 |
20220020657 | SEMICONDUCTOR DEVICE - A semiconductor device is provided, including multiple memory chips and a temperature detection module. The temperature detection circuit includes: multiple temperature sensitive units, arranged on the memory chips to detect temperatures of the memory chips; and a processing unit. The multiple temperature sensitive units share the processing unit with each other. The processing unit is configured to process a signal of at least one of the temperature sensitive units. The processing unit includes a calibration value memory cell and a calibration unit. The calibration value memory cell is configured to store a calibration value corresponding to the temperature sensitive unit. The calibration unit is configured to calibrate the temperature sensitive unit according to the calibration value. | 2022-01-20 |
20220020658 | POWER AMPLIFICATION DEVICE - A power amplification device includes: a first semiconductor chip including a first main surface and a second main surface; a first field-effect transistor, a first drain finger part, a plurality of first gate finger parts, and a source finger part; a sub-mount substrate including a third main surface and a fourth main surface; and a first filled via provided penetrating from the third main surface to the fourth main surface. In plan view, the first filled via has a rectangular shape. A long side direction of the first filled via is parallel to a long side direction of the plurality of first gate finger parts. In plan view, the first filled via is positioned to overlap part of one first gate finger part included in the plurality of first gate finger parts. | 2022-01-20 |
20220020659 | PACKAGED CHIP AND METHOD FOR MANUFACTURING PACKAGED CHIP - Embodiments of this application disclose a packaged chip and a method for manufacturing a packaged chip. The packaged chip includes a substrate, a chip, and a heat sink. The heat sink includes a first bracket, a second bracket, and a cover. The first bracket and the second bracket are disposed on the substrate. The cover is supported on the substrate by the first bracket and the second bracket. The first bracket is a sealed annular bracket. The first bracket and the cover encircle a first space. The chip is accommodated in the first space. A thermal interface material is disposed between the chip and the cover. A hole connected to the first space is provided on the cover. The hole and the first space are filled with a filling material. The second bracket is located outside the first space. | 2022-01-20 |
20220020660 | HEATER ELEMENTS FOR PROCESSOR DEVICES - Examples include a computing system including a heater element for heating a processor device installed in the computing system. The computing system includes a chassis, a circuit board assembly housed in the chassis and a heat sink assembly disposed on the chassis to form a cover of the chassis. The circuit board assembly includes a processor package including a substrate having a first portion and a second portion. The processor package includes the processor device disposed on the first portion of the substrate. The heater element disposed on the second portion of the substrate. In the computing system, the heat sink assembly is disposed on the chassis such that a gap separates the heat sink assembly and the heater element. | 2022-01-20 |
20220020661 | POWER CONVERSION DEVICE - A power conversion device includes: a power semiconductor module; a capacitor; a heatsink; cooling fins; a first partition; a cooling flow path through which a coolant flows between the heatsink and the first partition; a second partition extending from the first partition; an inflow path extending from a coolant inlet along another surface of the first partition and a surface of the second partition on a first side surface side, and connected to a first side surface side of the cooling flow path; and an outflow path extending from a coolant outlet along the other surface of the first partition and a surface of the second partition on a second side surface side, and connected to a second side surface side of the cooling flow path, wherein a length of the first side surface of the power semiconductor module is greater than a length of the third side surface thereof. | 2022-01-20 |
20220020662 | MEMORY DEVICE WITH LOW DENSITY THERMAL BARRIER - Methods, systems, and devices related to a memory device with a thermal barrier are described. The thermal barrier (e.g., a low density thermal barrier) may be positioned between an access line (e.g., a digit line or a word line) and a cell component. The thermal barrier may be formed on the surface of a barrier material by applying a plasma treatment to the barrier material. The thermal barrier may have a lower density than the barrier material and may be configured to thermally insulate the cell component from thermal energy generated in the memory device, among other benefits. | 2022-01-20 |
20220020663 | THERMALLY CONDUCTIVE MOLDING, PRODUCTION METHOD FOR THE SAME, STRUCTURE, AND MULTILAYER FILM - The production method for a thermally conductive molding includes: preparing a first film that is disposed on a mold having a three-dimensional shape so as to conform to the three-dimensional shape, and that has a first layer and a second layer that is releasably adhered to the first layer on a surface opposite to the mold of the first layer; disposing a curable composition including a thermally conductive material and a (meth)acrylic monomer on the first film; disposing a second film on the curable composition and sandwiching the curable composition between the first film and the second film; radically polymerizing the (meth)acrylic monomer in the curable composition to form a cured product of the curable composition between the first film and the second film; and releasing the first layer from the second layer to obtain a thermally conductive molding including the second layer, the cured product, and the second film. | 2022-01-20 |
20220020664 | THERMAL INTERFACE MATERIAL PASTE AND SEMICONDUCTOR PACKAGE - A semiconductor package includes at least one semiconductor device mounted on a first substrate, a thermosetting resin layer on the at least one semiconductor device, the thermosetting resin layer including an irreversible thermochromic pigment, a metal plate on the thermosetting resin layer, and a molding member surrounding the at least one semiconductor device at least in a lateral direction and being in contact with the thermosetting resin layer. | 2022-01-20 |
20220020665 | DOUBLE-SIDE BACK-END-OF-LINE METALLIZATION FOR PSEUDO THROUGH-SILICON VIA INTEGRATION - Methods, systems, and devices for double side back-end-of-line (BEOL) metallization for pseudo through-silicon via (pTSV) integration are described. An integrated circuit (IC) may include multiple metallic layers integrated within multiple layers of a multi-dimensional integrated stack (e.g., a three dimensional (3D) integrated stack). By performing a BEOL metallization process, the integrated circuit may implement techniques for 3D vertical chip integration. For example, a first set of layers may be formed during a first portion of a BEOL process and a second portion of the BEOL process may integrate a second set of metallic layers as well as a buried power delivery network (PDN). The metallic layers may form a number of pTSVs and may promote a PDN to experience a reduced PDN IR drop. The PDN may be integrated and the pTSVs may be formed by integrating the metallic layers within a number of dielectric layers. | 2022-01-20 |
20220020666 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device includes a substrate, a semiconductor fin, a source/drain structure, a first buried power line, a contact, a first through substrate via (TSV), and a second TSV. The substrate has a well region extending a frontside surface of the substrate into the substrate. The semiconductor fin is on the well region. The source/drain structure is on the semiconductor fin. The first buried power line is electrically coupled to the source/drain structure on the first semiconductor fin. The first buried power line has a length extending along a lengthwise direction of the first semiconductor fin and a height extending within the well region. The first TSV extends from a backside surface of the substrate through the substrate to the first buried power line. The second TSV extends from the backside surface of the substrate to the well region. | 2022-01-20 |
20220020667 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor includes a substrate having a first surface and a second surface opposite to each other, the substrate having a via hole extending in a thickness direction from the first surface, a circuit pattern in the first surface of the substrate, a through electrode structure in the via hole, a device isolation structure in a first trench extending in one direction in the first surface of the substrate, the device isolation structure between the via hole and the circuit pattern, the device isolation structure including a first oxide layer pattern and a first nitride layer pattern sequentially stacked on an inner surface of the first trench, the first nitride layer pattern filling the first trench, and an insulation interlayer on the first surface of the substrate and covering the circuit pattern. | 2022-01-20 |
20220020668 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate, a buried insulating film, a first conductive film, an insulating layer, a first contact and a second contact. The semiconductor substrate includes a first semiconductor region having a first conductive type and a second semiconductor region having a second conductive type. The buried insulating film surrounds the second semiconductor region in plan view. The first conductive film directly contacts with the first and second semiconductor regions. The first and second contacts overlap with the second semiconductor region in plan view and reach the first conductive film. The first contact is adjacent to the second contact along a first side of the second semiconductor region in plan view. In a direction along the first side, a first distance between the second semiconductor region and the buried insulating film is greater than a second distance between the first contact and the second contact. | 2022-01-20 |
20220020669 | EMBEDDED DIE PACKAGING FOR POWER SEMICONDUCTOR DEVICES - Embedded die packaging for high voltage, high temperature operation of power semiconductor devices is disclosed, wherein a power semiconductor die is embedded in laminated body comprising a layer stack of a plurality of dielectric layers and electrically conductive layers. For example, the dielectric layers comprise dielectric build-up layers of filled or fiber reinforced dielectric and conductive interconnect comprises copper layers and copper filled vias. Where a solder resist coating is provided, a dielectric build-up layer, e.g. filled or glass fiber reinforced epoxy, is provided between the solder resist coating and underlying copper interconnect, particularly in regions which experience high electric field during operation, such as between closely spaced source and drain interconnect metal. For example, the power semiconductor device comprises a GaN HEMT rated for operation at ≥100V wherein the package body has a laminated structure configured for high voltage, high temperature operation with improved reliability. | 2022-01-20 |
20220020670 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURE - A semiconductor device is provided that includes a frontside and a backside, four sidewalls, a first solder/glue connection on the frontside and a second solder/glue connection on the backside. The semiconductor device is either connected as a chip scale package to a printed circuit board or inside a semiconductor package via one of the four sidewalls, so that the first solder/glue connection and the second solder/glue connection are visible for a visual solder/glue inspection. | 2022-01-20 |
20220020671 | FLIP-STACK TYPE SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - The present invention minimizes parasitic inductance at the time of packaging a semiconductor that requires high efficiency and high-speed switching driving. In implementing a semiconductor package composed of one or more switching devices and one or more diode devices, the present invention provides a flip-stack structure in which a switching device is mounted on an insulating substrate or a metal frame, a flat metal is bonded onto the switching device, and a diode device is flipped and stacked on the flat metal, and accordingly, the flat metal with a large area is used for connection between the devices and between the devices and the insulating substrate, thereby minimizing parasitic inductance generated at a time of semiconductor packaging and automating the entire process of the semiconductor packaging. | 2022-01-20 |
20220020672 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME, AND POWER CONVERSION DEVICE - A semiconductor device includes a heat sink, an insulating layer, a lead frame, a power semiconductor element, a sealing resin, and fins. The heat sink has a first main surface and a second main surface opposed to each other. A lead frame including a lead terminal is disposed on the first main surface of the heat sink with the insulating layer interposed. The power semiconductor element is mounted on the lead frame. The sealing resin is formed to cover an inside region located inside of an outer peripheral region located around the entire periphery along the outer periphery of the first main surface of the heat sink. A first depression is formed along the sealing resin in the outer peripheral region of the first main surface. | 2022-01-20 |
20220020673 | QUAD FLAT NO-LEAD PACKAGE STRUCTURE - A quad flat no-lead (QFN) package structure including a lead frame, a semiconductor die, and an encapsulating material. The lead frame includes a die pad and a plurality of contacts surrounding the die pad. The semiconductor die is disposed on the die pad and electrically connected to the plurality of contacts, wherein a shortest distance between the semiconductor die and a first side of the die pad is shorter than a shortest distance between the semiconductor die to a second side of the die pad, and the first side is opposite to the second side. The encapsulating material encapsulates the lead frame and the semiconductor die and partially exposing the plurality of contacts, wherein an aspect ratio of the QFN package is substantially equal to or greater than 3. | 2022-01-20 |
20220020674 | WIRING STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A wiring structure and a method for manufacturing the same are provided. The wiring structure includes a conductive structure and at least one conductive through via. The conductive structure includes a plurality of dielectric layers and a plurality of circuit layers in contact with the dielectric layers. The conductive through via extends through the conductive structure. The conductive through via is a monolithic structure, and includes a main portion and an extending portion protruding from the main portion. | 2022-01-20 |
20220020675 | Multi-Liner TSV Structure and Method Forming Same - A method includes etching a substrate to form an opening, depositing a first dielectric liner extending into the opening, and depositing a second dielectric liner over the first dielectric liner. The second dielectric liner extends into the opening. A conductive material is filled into the opening. The method further includes performing a first planarization process to planarize the conductive material so that a portion of the conductive material in the opening forms a through-via, performing a backside grinding process on the substrate until the through-via is revealed from a backside of the substrate, and forming a conductive feature on the backside of the substrate. The conductive feature is electrically connected to the through-via. | 2022-01-20 |
20220020676 | SEMICONDUCTOR PACKAGE AND PACKAGE-ON-PACKAGE INCLUDING THE SAME - A semiconductor package that includes a support wiring structure. A semiconductor chip is on the support wiring structure. A cover wiring structure is on the semiconductor chip. A plurality of connection structures penetrates a filling member and electrically connects the support wiring structure to the cover wiring structure. The filling member fills a space between the support wiring structure and the cover wiring structure. The filling member surrounds the plurality of connection structures and the semiconductor chip and includes a plurality of fillers. A partial portion of the plurality of fillers includes cutting fillers having a flat surface that extends along a vertical level that is a reference level. | 2022-01-20 |
20220020677 | PACKAGE STRUCTURE OF COMMON-SOURCE COMMON-GATE GALLIUM NITRIDE FIELD-EFFECT TRANSISTOR - A package structure of a common-source common-gate gallium nitride field-effect transistor is disclosed, including a lead frame. A gallium nitride field-effect transistor and a metal oxide semiconductor are directly disposed on the lead frame. The gallium nitride field-effect transistor includes a first matrix directly disposed on the lead frame. A first drain, a first gate, and a first source are disposed on a surface side of the first matrix, and the first drain and the first gate are separately electrically connected to the lead frame. The metal oxide semiconductor includes a second matrix directly disposed on the lead frame. A second drain, a second gate, and a second source are disposed on a surface side of the second matrix, the second drain is directly electrically connected to the first source, and the second gate and the second source are separately electrically connected to the lead frame. | 2022-01-20 |
20220020678 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a chip; a circuit element formed in the chip; an insulating layer formed over the chip so as to cover the circuit element; a multilayer wiring region formed in the insulating layer and including a plurality of wirings laminated and arranged in a thickness direction of the insulating layer so as to be electrically connected to the circuit element; at least one insulating region which does not include the wirings in an entire region in the thickness direction of the insulating layer and is formed in a region outside the multilayer wiring region in the insulating layer; and at least one terminal electrode disposed over the insulating layer so as to face the chip with the at least one insulating region interposed between the at least one terminal electrode and the chip. | 2022-01-20 |
20220020679 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURE - A semiconductor device is provided that includes a substrate, a pocket within the substrate, a solderable/glueable re-distribution layer arranged in the pocket and a die. The die is arranged downwards, so that a base contact and an emitter contact of the die face the bottom of the device, and a collector contact of the die faces the top of the device. The solderable/glueable re-distribution layer includes a first and second re-distribution layer part and the first re-distribution layer part and the second re-distribution layer part are isolated from each other by an isolating material. The emitter contact is connected to the first re-distribution layer part and the base contact is connected to the second re-distribution layer part. The emitter contacts via the first re-distribution layer part, the base contacts via the second re-distribution layer part, and the collector contact are fan out to the top surface of the semiconductor device. | 2022-01-20 |
20220020680 | LEAD FRAME, PACKAGE STRUCTURE COMPRISING THE SAME AND METHOD FOR MANUFACTURING THE PACKAGE STRUCTURE - A lead frame includes a die paddle and a plurality of leads. The leads surround the die paddle. Each of the leads includes an inner lead portion and an outer lead portion connecting to the inner lead portion. The inner lead portion is adjacent to and spaced apart from the die paddle. A bottom surface of the inner lead portion is higher than a bottom surface of the outer lead portion. The bottom surface of the inner lead portion includes one or more supporting members disposed thereon. The one or more supporting members have a convex surface facing away from the inner lead portion. | 2022-01-20 |
20220020681 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device according to an embodiment includes a substrate. The substrate includes first and second areas, and block areas. The second area includes subareas. Each of the subareas includes a contact area and an insulating area arranged in the first direction. The contact area includes terraced portions and first contacts corresponding to two block areas. The insulating area includes second contacts corresponding to the two block areas. Contact areas of odd-numbered subareas and insulating areas of even-numbered subareas are disposed in an alternating manner in the second direction. Insulating areas of the odd-numbered subareas and contact areas of the even-numbered subareas are disposed in an alternating manner in the second direction. | 2022-01-20 |
20220020682 | SEMICONDUCTOR DEVICE - A semiconductor device includes bumps and a plurality of input/output areas on a substrate. Each of the input/output areas include semiconductor elements on the substrate, lower wiring patterns connected to the semiconductor elements, and input/output pins above and connected to the lower wiring patterns. The semiconductor elements provide a logic circuit and a protection circuit. The bumps are above the lower wiring patterns and connected to the input/output pins by upper wiring patterns. The input/output areas include a first input/output area and a second input/output area. The input/output areas includes a first circuit area including the electrostatic discharge protection circuit and a second circuit area including the logic circuit. In the first input/output area, the input/output pin is in the first circuit area. In the second input/output area, the input/output pin is in the second circuit area. | 2022-01-20 |
20220020683 | SEMICONDUCTOR DEVICE - A semiconductor device having a novel structure is provided. The semiconductor device includes a silicon substrate and a device provided above the silicon substrate. The device includes a transistor and a conductor. The transistor includes a metal oxide in a channel formation region. Conductivity is imparted to the silicon substrate. The conductor is electrically connected to each of a drain of the transistor and the silicon substrate through an opening provided in the device. Heat of the drain of the transistor can be efficiently released through the silicon substrate. | 2022-01-20 |
20220020684 | SEMICONDUCTOR DEVICE AND METAL-OXIDE-SEMICONDUCTOR CAPACITOR STRUCTURE - A semiconductor device is disposed below an inductor. The semiconductor device includes a metal-oxide-semiconductor capacitor structure and a patterned shielding structure. The metal-oxide-semiconductor capacitor structure includes a polysilicon layer, an oxide definition layer, and a first metal layer. The first metal layer is connected to the polysilicon layer and the oxide definition layer. The patterned shielding structure is disposed over the metal-oxide-semiconductor capacitor structure and includes a second metal layer. | 2022-01-20 |
20220020685 | SLIT OXIDE AND VIA FORMATION TECHNIQUES - Methods and apparatuses for slit oxide and via formation techniques are described, for example, for fabricating three dimensional memory devices that may include multiple decks of memory cells that each include memory cell stacks and associated access lines. The techniques may create an interconnect region without removing a portion of the memory cell stacks. The interconnect region may include one or more conductive vias extending through the decks of memory cells to couple the access lines with logic circuitry that may be located underneath the decks of memory cells. Further, the techniques may divide an array of memory cells into multiple subarrays of memory cells by forming trenches, which may sever the access lines. In some cases, each subarray of memory cells may be electrically isolated from other subarrays of memory cells. The techniques may reduce a total number of fabrication process steps. | 2022-01-20 |
20220020686 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present technology relates to a semiconductor device and a method of manufacturing the same. The semiconductor device includes a first stack including first interlayer insulating layers and first conductive patterns which are alternately stacked with one another, a second stack including second interlayer insulating layers and second conductive patterns which are alternately stacked with one another on the first stack, a plurality of channel plugs vertically formed through the first stack and the second stack, and at least one dummy plug vertically formed through the second without passing through the first stack. | 2022-01-20 |
20220020687 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH PROGRAMMABLE ANTI-FUSE FEATURE - The present application discloses a method for fabricating a semiconductor device. The method includes providing a substrate, forming a peak portion on the substrate, forming a gate insulating layer on the substrate and the peak portion, forming a gate bottom conductive layer on the gate insulating layer, and forming a first doped region in the substrate and adjacent to one end of the gate insulating layer. | 2022-01-20 |
20220020688 | Fully Aligned Via for Interconnect - A fully aligned via interconnect structure and techniques for formation thereof using subtractive metal patterning are provided. In one aspect, an interconnect structure includes: metal lines Mx−1; metal lines Mx disposed over the metal lines Mx−1; and at least one via Vx−1 fully aligned between the metal lines Mx−1 and the metal lines Mx, wherein a top surface of at least one of the metal lines Mx−1 has a stepped profile. In another aspect, another interconnect structure includes: metal lines Mx−1; metal lines Mx disposed over the metal lines Mx−1; at least one via Vx−1 fully aligned between the metal lines Mx−1 and the metal lines Mx; and sidewall spacers alongside the metal lines Mx. A method of forming an interconnect structure is also provided. | 2022-01-20 |
20220020689 | INDUCTOR DEVICE WIRING ARCHITECTURE, INTEGRATED CIRCUIT, AND COMMUNICATIONS DEVICE - Embodiments of this application disclose an inductor device wiring architecture, including an inductor device and a plurality of dummy metals located under the inductor device. The plurality of dummy metals are arranged in a plurality of metal layers. Each of the plurality of metal layers corresponds to some of the plurality of dummy metals. Arrangement areas of dummy metals corresponding to at least two of the plurality of metal layers progressively increase in a direction away from the inductor device. In the inductor device wiring architecture, adverse effects on performance of the inductor device can be reduced, and a product yield can be increased. The embodiments of this application further disclose an integrated circuit and a communications device. | 2022-01-20 |
20220020690 | SEMICONDUCTOR CHIP INCLUDING PENETRATING ELECTRODES, AND SEMICONDUCTOR PACKAGE INCLUDING THE SEMICONDUCTOR CHIP - A semiconductor chip may include: a body portion including a front surface and a back surface; penetrating electrodes penetrating the body portion; and back connection electrodes disposed over the back surface of the body portion and connected to the penetrating electrodes, wherein the penetrating electrodes include a power penetrating electrode for transmitting a power voltage and a ground penetrating electrode for transmitting a ground voltage, the back connection electrodes include a power back connection electrode connected to the power penetrating electrode and a ground back connection electrode connected to the ground penetrating electrode, and one power back connection electrode is connected with two or more power penetrating electrodes, and one ground back connection electrode is connected with two or more ground penetrating electrodes. | 2022-01-20 |