13th week of 2012 patent applcation highlights part 62 |
Patent application number | Title | Published |
20120079134 | PROVIDING VIRTUAL NETWORKS USING MULTI-TENANT RELAYS - Embodiments are directed to providing a multi-tenant relay service that securely relays data between computer systems. A computer system receives a portion of data that is to be passed from a first computer system belonging to a first tenant to a second, different computer system. The instantiated multi-tenant relay service is configured to securely relay data for multiple different tenants. The computer system creates a secure routing channel for routing the data of the first tenant between the first computer system and the second computer system. The secure routing channel applies a unique identifier to each portion of data received from the first tenant. The computer system also routes the received data from the first computer system to the second computer system through the secure routing channel using the applied unique identifier. | 2012-03-29 |
20120079135 | Insertion of User Information into Headers to Enable Targeted Responses - An intermediary device configured to insert at least one of user interest categories or a client device location in the header portion of a message received from a client device is described herein. The insertion enables a server receiving the message from the intermediary device to target content to the client device based on the at least one of the user interest categories or the client device location. | 2012-03-29 |
20120079136 | System and Method for Dynamically Configuring a Target Device - In accordance with the present disclosure, a method for dynamically configuring a target device comprises receiving by one or more ports of a target device one or more initiator identifiers from one or more initiators. The method further comprises determining whether a plurality of ports received initiator identifiers from a common initiator. The method further comprises configuring the plurality of the ports to operate as a single, logical port if the plurality of ports received initiator identifiers from a common initiator. | 2012-03-29 |
20120079137 | SYSTEMS CONFIGURED TO IDENTIFY AN OPERATING MODE - Systems having a host computer system, a memory device coupled to the host computer system, and identification circuitry. The identification circuitry is configured to identify an operating mode of the host computer system from comparing applied signals to sensed signals. | 2012-03-29 |
20120079138 | DYNAMICALLY CONFIGURABLE SERIAL DATA COMMUNICATION INTERFACE - A serial peripheral interface (SPI) controller can be configured in response to data received via the interface. The SPI controller can perform read and write operations upon registers of a register bank in response to signals received via one or more of a data signal line, a clock signal line, and a select signal line. By detecting combinations of signals on one or more of the data signal line, clock signal line and select signal line, the SPI controller can detect the initiation of data read and write operations that may be in accordance with any of several different SPI protocols. | 2012-03-29 |
20120079139 | COMPUTER SYSTEM, APPARATUS, AND METHOD FOR CHECKING FOR CABLE MISCONNECTIONS - When checking whether or not the connection-destination port of a cable that is connected between apparatuses is correct, notification is made to a user by a control apparatus. The control apparatus identifies a second port that is the correct connection destination of a target first port, which is a check-target first port of multiple first ports, identifies a second port, which is connected via a cable to the target first port, and determines whether or not these second ports are the same. In a case where the result of this determination is negative, the control apparatus causes the second display apparatus to execute a display with respect to the second port that is the correct connection destination of the target first port. | 2012-03-29 |
20120079140 | Techniques for Achieving Complete Interoperability Between Different Types of Data and Multimedia Interfaces in Handheld Devices - A triple-mode connectivity apparatus for enabling interoperability between a multimedia display interface and a data interface. The apparatus comprises a universal connector installed in a first device and structured to enable connectivity between the multimedia display interface and the data interface of a second device, the first device is connected to the second device using a cable having a first connector compliant with the universal connector and a second connecter compliant with the data interface of the second device; a physical layer interface for processing signals compliant with the multimedia display interface and the data interface; and a detector for detecting an interface type of the second device and setting the apparatus to process signals according to the determined interface type. | 2012-03-29 |
20120079141 | INFORMATION PROCESSING APPARATUS AND INTER-PROCESSOR COMMUNICATION CONTROL METHOD - An information processing apparatus includes a plurality of processors configured to form a pipeline, a plurality of communication units configured to transfer communication data between a processor in an upstream stage of the pipeline and another processor in a downstream stage and to temporarily store the communication data output from the processor in the upstream stage to the processor in the downstream stage into an internal FIFO buffer, and a memory configured to be accessible from each of the processors and each of the communication units. | 2012-03-29 |
20120079142 | MULTIPLE IMAGE BUFFER SIMULATION - Various embodiments related to a host computing device for rendering and sending image data to a peripheral device for display at the peripheral device. For example, one embodiment comprises a host computing device, the host computing device comprising a data storage subsystem and a logic subsystem. The host computing device further comprises instructions stored in the data storage subsystem and executable by the logic subsystem to output to the peripheral device a frame of image data representing a difference between a currently rendered image and an (N−1)-th previously rendered image, N being an integer and having a value of 3 or more. | 2012-03-29 |
20120079143 | WIRELESS HOST I/O USING VIRTUALIZED I/O CONTROLLERS - Mechanisms provide hosts such as servers and mobile devices with access to virtualized I/O resources including virtual Host Bus Adapters (vHBAs) and virtual Network Interface Cards (vNICs) over a wireless I/O interconnect. Host applications access virtualized I/O resources using virtual device drivers that communicate with virtualized I/O resources on an I/O director using a reliable communication protocol running over a wireless network. I/O data is throttled if necessary based on wireless network considerations. | 2012-03-29 |
20120079144 | Low Latency First-In-First-Out (FIFO) Buffer - Systems and methods are provided for a first-in-first-out buffer. A buffer includes a first sub-buffer configured to store data received from a buffer input, and a second sub-buffer. The second sub-buffer is configured to store data received from either the buffer input or the first sub-buffer and to output data to a buffer output in a same order as that data is received at the buffer input. Buffer control logic is configured to selectively route data from the buffer input or the first sub-buffer to the second sub-buffer so that data received at the buffer input is available to be output from the second sub-buffer in a first-in-first-out manner. | 2012-03-29 |
20120079145 | ROOT HUB VIRTUAL TRANSACTION TRANSLATOR - Systems and methods of operating root hub host controllers provide for determining, at a protocol engine having a dedicated port, a speed of a device in response to a coupling of the device to the dedicated port. Data transfer can occur at a second speed between software interface logic of the host controller and the protocol engine, and at the first speed between the protocol engine and the device via the dedicated port, wherein the second speed is greater than the first speed. In addition, data may be transferred in unicast transactions in which no split tokens are exchanged. | 2012-03-29 |
20120079146 | METHOD AND ARRANGEMENT FOR STREAMING DATA PROFILING - A circuit arrangement includes a plurality of functional units each of which comprises a plurality of data processing modules and a local controller. The plurality of data processing modules run a common system clock and are connected by a streaming data bus running a handshake-type streaming data transfer protocol. A profiling module of the circuit arrangement assesses control signals tapped at predefined interfaces of the streaming data bus during real time operation, for determining link performance and communication patterns for profiling and debugging purposes, and hence constitutes a simple and low cost approach for assessing intra-component and inter-component link performance and communication patterns on large SoCs. A method for profiling data flow for use in such a circuit arrangement is also provided. | 2012-03-29 |
20120079147 | BUS CONTROL DEVICE - A bus controller includes: a data receiving section for receiving output status information from other bus controllers on transmission routes available; a route load detecting section for calculating uniformity of distribution index indicating the degree of non-uniformity in transmission flow rate between the routes based on the output status information; a routing section for determining transmission routes, of which the transmission flow rates have been adjusted by reference to the index; a packet assembling section for generating a packet; a data output section for outputting the packet through one of output ports; a header analyzing section for determining which output port is connected to a transmission route chosen by reference to information about the packet receiving end; and a data output section for outputting the packet through the output port. | 2012-03-29 |
20120079148 | REORDERING ARRANGEMENT - An embodiment of a network-on-chip is provided. The network-on-chip includes a plurality of sources of requests and a plurality of destinations for requests. The plurality of destinations are configured to provide respective responses to respective requests. The network-on-chip further includes an interconnect for routing said requests and respective responses to said requests to and from the plurality of sources and at least one transaction reordering arrangement. The transaction reordering arrangement is configured to reorder said responses such that said responses are provided to a respective source in an order which corresponds to an order in which the requests are issued by said respective source. A respective transaction reordering arrangement is associated with a respective source. | 2012-03-29 |
20120079149 | METHOD FOR VEHICLE INTERNETWORKS - Vehicle internetworks provide for communications among diverse electronic devices within a vehicle, and for communications among these devices and networks external to the vehicle. The vehicle internetwork comprises specific devices, software, and protocols, and provides for security for essential vehicle functions and data communications, ease of integration of new devices and services to the vehicle internetwork, and ease of addition of services linking the vehicle to external networks such as the Internet. | 2012-03-29 |
20120079150 | Bus system and deadlock avoidance circuit thereof - Disclosed herein is a deadlock avoidance circuit including: a previous-transaction-information management section; a transaction-issuance-termination determination section; and a response-outputting control section. | 2012-03-29 |
20120079151 | IDENTIFICATION, BY A MASTER CIRCUIT, OF TWO SLAVE CIRCUITS CONNECTED TO A SAME BUS - A method of communication between a master circuit and two slave circuits over a serial bus wherein: the two slave circuits simultaneously transmit their associated identifiers; the two slave circuits simultaneously transmit the inverse of these identifiers; and each slave circuit exploits the combinations present on the bus to determine an order of communication between the two circuits. | 2012-03-29 |
20120079152 | METHOD FOR CONNECTING SLAVE CARDS TO A BUS SYSTEM - A method for connecting slave cards to a first bus system and a system for implementing the method are described. In the method, signals are transferred from the slave cards to a CPU via the first bus system, a master being assigned to each slave card, and the signals being transferred from each slave card via the assigned master. | 2012-03-29 |
20120079153 | COMMUNICATION METHOD AND DEVICE FOR A MOTOR VEHICLE - A communication method is implemented in an on-board network between a master station (M) and a plurality of slave stations (S1, S2, S3, S4), of the type of those compatible with the standard Local Interconnect Network (LIN) protocol in which data frames are sent by the slave stations on a serial bus in response to the sending by the master station of identifiers representative of the required content of the frames. All or part of each of the specific data frames attached to the same predetermined identifier is formed sequentially by each of the slave stations. This enables an optimisation of the load on a LIN network, thus enabling use of this economical standard for all “passenger compartment functions”, and in particular for the management of AFS type advanced lighting systems. | 2012-03-29 |
20120079154 | TRANSACTION REORDERING ARRANGEMENT - An embodiment of a transaction reordering arrangement is provided. The transaction reordering arrangement includes a queue into which respective responses to requests are writable and a controller configured to control a position in said queue to which said respective responses to said requests are written. The position is controlled such that the responses are read out of said queue in an order which corresponds to an order in which the requests are issued. | 2012-03-29 |
20120079155 | Interleaved Memory Access from Multiple Requesters - A shared memory system having multiple banks is coupled to a set of requesters. Separate arbitration and control logic is provided for each bank, such that each bank can be accessed individually. The separate arbitration logics individually arbitrate transaction requests targeted to each bank of the memory. Access is granted to each bank on each access cycle to a highest priority request for each bank, such that more than one transaction request may be granted access to the memory on a same access cycle. A wide transaction request that has a transaction width that is wider than a width of one bank is divided into a plurality of divided requests. | 2012-03-29 |
20120079156 | IMPLEMENTING QUICKPATH INTERCONNECT PROTOCOL OVER A PCIe INTERFACE - Methods and apparatus for implementing the Intel QuickPath Interconnect® (QPI) protocol over a PCIe interface. The upper layers of the QPI protocol are implemented over a physical layer of the PCIe interface via use of QPI data bit mappings onto corresponding PCIe x16, x8, and x4 lane configurations. A QPI link layer to PCIe physical layer interface is employed to abstract the QPI link, routing, and protocol layers from the underlying PCIe physical layer (and corresponding PCIe interface circuitry), enabling QPI protocol messages to be employed over PCIe hardware. Thus, QPI functionality, such as support for coherent memory transactions, may be implemented over PCIe interface circuitry. | 2012-03-29 |
20120079157 | DEVELOPMENT OF FUNCTIONAL MODULES USING A MODULE BUS - Systems and methods are provided that facilitate development of a module for use in a control application by assembling one or more predefined aspects onto a module bus. The module bus acts as a virtual backplane that allows module functionality in the form of predefined bus-compliant aspects to be selected and added to the bus, thereby yielding a module having a desired set of functions. When an aspect is added to the module bus, the bus integrates the aspects into the module automatically without the need to modify the module's core code to interface the aspects with the module. The module bus also establishes the necessary interdependencies between aspects representing cross-cutting concerns without requiring new code to be writing to link the aspects. | 2012-03-29 |
20120079158 | SIGNAL SWITCH CONNECTOR SET APPLIED TO MOTHERBOARD OF COMPUTER SYSTEM - A signal switch connector set is disposed on a motherboard of a computer system. The signal switch connector set is capable of selectively connecting a USB 3.0 signal terminal of a south bridge chip to a USB 3.0 port located at the rear panel of a casing or connecting the USB 3.0 terminal of the south bridge chip to the USB 3.0 port located at the front panel of the casing. | 2012-03-29 |
20120079159 | Throttling Integrated Link - Methods and apparatus for throttling an interface that is integrated on the same die as a processor are described. In one embodiment, a signal from an Integrated Input/Output hub (e.g., integrated on the same die as a processor) causes throttling of a link coupled between the IIO and an Input/Output (IO) device. Other embodiments are also disclosed. | 2012-03-29 |
20120079160 | METHOD AND SYSTEM OF ADAPTING COMMUNICATION LINKS TO LINK CONDITIONS ON A PLATFORM - A method and system to adapt communication links statically and/or dynamically to their individual link conditions on a platform. The communicatively coupled devices have logic to adapt one or more settings of a respective one or more communication links with another device based at least in part on a respective metric of received data patterns from the respective one or more communication links. The communicatively coupled devices in the platform have a back channel to allow feedback or information to be sent from one receiving device to a transmitting device in one embodiment of the invention. | 2012-03-29 |
20120079161 | CIRCUIT FOR SIMULTANEOUSLY ANALYZING PERFORMANCE AND BUGS AND METHOD THEREOF - A circuit for simultaneously analyzing performance and bugs includes a mapping unit and a USB 3.0 data flow analyzer. The mapping unit is used for mapping commands transmitted to a USB 3.0 host through a peripheral component interconnect express and internal events of the USB 3.0 host to a packet of a USB 3.0 bus. The USB 3.0 data flow analyzer is used for analyzing performance and bugs of the USB 3.0 host through the packet of the USB 3.0 bus. | 2012-03-29 |
20120079162 | TRANSPARENT REPEATER DEVICE FOR HANDLING DISPLAYPORT CONFIGURATION DATA (DPCD) - Consistent with an example embodiment a repeater device is provided for handling signal transmissions, in particular in a DisplayPort environment. The repeater is to be coupled with an upstream device and a downstream device, the repeater being adapted for transmitting signals received from the upstream device to the downstream device and for conditioning the signals before transmission. The repeater is configured to provide a transparent communication path between the upstream device and the downstream device for DPCD access transactions belonging to a second group of DPCD access transactions. For DPCD access transactions belonging to a first group of DPCD access transaction, the repeater is configured to process the DPCD access transactions by accessing one or more DPCD registers included in the repeater. | 2012-03-29 |
20120079163 | SKEW MANAGEMENT IN AN INTERCONNECTION SYSTEM - An interconnection system is described where data lanes may be exchanged between lines at intervals along a transmission path so that the differential time delay between bits on a plurality of the lines is reduced when determined at a receiving location. The data lanes may be bound to the lines through the operation of a configurable switch, or by a configurable switch in conjunction with predetermined manufactured connections, or a combination of the techniques. The wiring of a connectorized node module, which may include a memory device, may be configured so that the differential time delay between pairs of input lines of a node, as measured at the output of a node, is reduced. | 2012-03-29 |
20120079164 | MICROPROCESSOR WITH DUAL-LEVEL ADDRESS TRANSLATION - A processor includes a first translation look-aside buffer to support a guest operating mode. A second translation look-aside buffer supports a root operating mode. Hardware resources support the guest operating mode as controlled by guest mode control registers defining guest context. The guest context is used by the hardware resources to access the first translation look-aside buffer to translate a guest virtual address to a guest physical address. The hardware resources access the second translation look-aside buffer to translate the guest physical address to a physical address. | 2012-03-29 |
20120079165 | Paging Memory From Random Access Memory To Backing Storage In A Parallel Computer - Paging memory from random access memory (‘RAM’) to backing storage in a parallel computer that includes a plurality of compute nodes, including: executing a data processing application on a virtual machine operating system in a virtual machine on a first compute node; providing, by a second compute node, backing storage for the contents of RAM on the first compute node; and swapping, by the virtual machine operating system in the virtual machine on the first compute node, a page of memory from RAM on the first compute node to the backing storage on the second compute node. | 2012-03-29 |
20120079166 | ELECTRONIC DEVICE AND METHOD FOR INITIALIZING DATA STORAGE - An electronic device for initializing a data storage is provided. The data storage has been accessed. The data storage includes a plurality blocks, which comprise some bad blocks. Each block comprising a block marking area for writing a block identifier. The block identifier is for marking whether the block is a bad block or a good block. After the data storage is accessed, a bad-block table for recording the block identifier of each block is stored at a predetermined location of the data storage. When initializing the data storage, the electronic device accesses the bad-block table from the predetermined location of the data storage, erases data stored on the data storage, obtains the block identifier of each block from the bad-block table; and writes the block identifier to the block marking area of each block. | 2012-03-29 |
20120079167 | MEMORY SYSTEM - According to one embodiment, a memory system includes a non-volatile semiconductor memory, a block management unit, and a transcription unit. The semiconductor memory includes a plurality of blocks to which data can be written in both the first mode and the second mode. The block management unit manages a block that stores therein no valid data as a free block. When the number of free blocks managed by the block management unit is smaller than or equal to a predetermined threshold value, the transcription unit selects one or more used blocks that stores therein valid data as transcription source blocks and transcribes valid data stored in the transcription source blocks to free blocks in the second mode. | 2012-03-29 |
20120079168 | METHOD FOR PERFORMING BLOCK MANAGEMENT, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for performing block management is provided. The method is applied to a controller of a Flash memory having multiple channels. The Flash memory includes a plurality of blocks respectively corresponding to the channels. The method includes: temporarily storing at least one index of at least one good block that is not grouped into any meta block into a spare good block table, where the good block is a block that is not determined as a bad block within the plurality of blocks; and when it is detected that a specific block corresponding to a specific channel within blocks currently grouped into meta blocks is a bad block, dynamically updating the spare good block table for use of block management. In particular, when needed, the good block is utilized for replacing a block grouped into a meta block. An associated memory device and a controller thereof are also provided. | 2012-03-29 |
20120079169 | METHOD FOR PERFORMING META BLOCK MANAGEMENT, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for performing meta block management is provided. The method is applied to a controller of a Flash memory having multiple channels, where the Flash memory includes a plurality of blocks respectively corresponding to the channels. The method includes: utilizing a meta block mapping table to store block grouping relationships respectively corresponding to a plurality of meta blocks, where blocks in each meta block respectively correspond to the channels; and when it is detected that a specific block corresponding to a specific channel within a meta block does not have remaining space for programming, according to the meta block mapping table, utilizing at least one blank block corresponding to the specific channel within at least one other meta block as extension of the specific block, for use of further programming. An associated memory device and a controller thereof are also provided. | 2012-03-29 |
20120079170 | METHOD FOR PERFORMING BLOCK MANAGEMENT, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for performing block management is provided. The method is applied to a controller of a Flash memory having multiple channels, where the Flash memory includes a plurality of blocks respectively corresponding to the channels. The method includes: obtaining at least one portion of a plurality of address-to-channel mapping relationships, for use of writing/programming operations; and according to at least one address-to-channel mapping relationship of the plurality of address-to-channel mapping relationships, programming at least one page of data into the Flash memory through at least one channel in a page mode. An associated memory device and a controller thereof are also provided. | 2012-03-29 |
20120079171 | Non-volatile memory systems and methods of managing power of the same - A non-volatile memory system and a method of managing the power of the same are provided. The non-volatile memory system includes a non-volatile memory configured to store a first mapping table comprising a list of a logical address and a physical address corresponding to the logical address with respect to a code region and a list of a logical address and a physical address corresponding to the logical address with respect to a general purpose (GP) region, and a controller configured to load the first mapping table from the non-volatile memory to a first memory and load the second mapping table from the non-volatile memory to a second memory. Power-up of the second memory is delayed with respect to power-up of the non-volatile memory system and the first or second memory is powered down if a condition is satisfied, so that power consumption of the non-volatile memory system is reduced. | 2012-03-29 |
20120079172 | MEMORY SYSTEM - Created is transfer order information indicating an order of transfer from multiple memory areas in accordance with an order of logical addresses and memory locations which are specified by read commands. Readout from the multiple memory areas in accordance with the transfer order information is performed by controlling memory controllers in accordance with the created transfer order information. | 2012-03-29 |
20120079173 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WITH ADVANCED MULTI-PAGE PROGRAM OPERATION - A nonvolatile semiconductor memory device includes a memory cell array having a plurality of banks and a cache block corresponding to each of the plurality of banks. The cache block has a predetermined data storage capacity. A page buffer is included which corresponds to each of the plurality of banks. A programming circuit programs all of the plurality of banks except a last of said banks with page data. The page data is loaded through each page buffer and programmed into each cache block such that when page data for the last bank is loaded into the page buffer, the loaded page data and the page data programmed into the respective cache blocks are programmed into respective corresponding banks. | 2012-03-29 |
20120079174 | APPARATUS, SYSTEM, AND METHOD FOR A DIRECT INTERFACE BETWEEN A MEMORY CONTROLLER AND NON-VOLATILE MEMORY USING A COMMAND PROTOCOL - A method for a direct interface between a memory controller and a non-volatile memory controller using a command protocol includes receiving a command from a memory controller to a non-volatile memory controller over a wire interface by way of a command protocol. The memory controller is coupled to one or more processors and the non-volatile memory controller, in one embodiment, is coupled to non-volatile memory media. The command protocol includes a control path that enables the memory controller to distinguish among different memory modules. The non-volatile memory controller stores data sequentially on the non-volatile memory media to preserve an ordered sequence of memory operations performed on the non-volatile memory media. The method includes executing the command within the non-volatile memory controller in response to determining that the non-volatile memory controller is capable of satisfying the command. | 2012-03-29 |
20120079175 | APPARATUS, SYSTEM, AND METHOD FOR DATA TRANSFORMATIONS WITHIN A DATA STORAGE DEVICE - An apparatus, system, and method are disclosed for executing data transformations for a data storage device. A storage controller module executes a storage operation for a set of data within a data storage device. A transformation module determines to apply a data transformation to the set of data in response to a transformation indicator. A processing module applies the data transformation to the set of data internally on the data storage device prior to completing the storage operation. | 2012-03-29 |
20120079176 | MEMORY DEVICE - A multi-channel flash memory device comprising die-stacked flash memory dies. The flash memory device is compact due to the stacked dies arrangement while providing high speed performance due to its multiple data channel arrangement. A specific example is a flash memory comprising 4 stacked flash memory dies with 4 parallel data channels. This invention alleviates the bottle neck problems of know die-stacked flash memory devices. | 2012-03-29 |
20120079177 | MEMORY INTERLEAVE FOR HETEROGENEOUS COMPUTING - A memory interleave system for providing memory interleave for a heterogeneous computing system is provided. The memory interleave system effectively interleaves memory that is accessed by heterogeneous compute elements in different ways, such as via cache-block accesses by certain compute elements and via non-cache-block accesses by certain other compute elements. The heterogeneous computing system may comprise one or more cache-block oriented compute elements and one or more non-cache-block oriented compute elements that share access to a common main memory. The cache-block oriented compute elements access the memory via cache-block accesses (e.g., 64 bytes, per access), while the non-cache-block oriented compute elements access memory via sub-cache-block accesses (e.g., 8 bytes, per access). A memory interleave system is provided to optimize the interleaving across the system's memory banks to minimize hot spots resulting from the cache-block oriented and non-cache-block oriented accesses of the heterogeneous computing system. | 2012-03-29 |
20120079178 | METHOD AND SYSTEM FOR ADAPTIVE CODING IN FLASH MEMORIES - To store bits in one or more cells, an adaptive mapping of bits to ranges of a physical parameter of the cell(s) is provided, in accordance with respective initial values of the physical parameter, by steps including encoding the bits as a codeword by partitioning the bits into subsets and finding a factor bit string such that the codeword is a concatenation of the factor bit string and separate Galois field products of all the subsets with the factor bit string. The initial values of the physical parameter are adjusted accordingly as needed. | 2012-03-29 |
20120079179 | Processor and method thereof - A processor and an operating method are described. By diversifying an L1 memory being accessed, based on an execution mode of the processor, an operating performance of the processor may be enhanced. By disposing a local/stack section in a system dynamic random access memory (DRAM) located external to the processor, a size of a scratch pad memory may be reduced without deteriorating a performance. While a core of the processor is performing in a very long instruction word (VLIW) mode, the core may data-access a cache memory and thus, a bottleneck may not occur with respect to the scratch pad memory even though a memory access occurs with respect to the scratch pad memory by an external component. | 2012-03-29 |
20120079180 | DRAM Controller and a method for command controlling - A memory controller and a command control method are disclosed. When there is a need to access an unactivated bank in an external DRAM, an ACT command and an access command of a low rate are generated in parallel for the bank, and the parallel ACT and access commands of the low rate are sequentially output to a bus of the external DRAM in serial at a high rate. | 2012-03-29 |
20120079181 | TRANSLATING MEMORY MODULES FOR MAIN MEMORY - A translating memory module is disclosed including a printed circuit board, at least one memory integrated circuit coupled to the printed board, and at least one support chip coupled to the printed circuit board and coupled between the edge connector and the at least one memory integrated circuit. The at least one support chip includes a bi-directional translator to translate between a first memory communication protocol for the at least one memory integrated circuit and a second memory communication protocol for a memory channel differing from the first memory communication protocol. The second memory communication protocol to communicate data, address, and control signals over the memory channel bus to read and write data into the memory of the translating memory module. | 2012-03-29 |
20120079182 | FAST EXIT FROM DRAM SELF-REFRESH - Embodiments of the invention describe a dynamic random access memory (DRAM) device that may abort a self-refresh mode to improve the exit time from a DRAM low power state of self-refresh. During execution of a self-refresh mode, the DRAM device may receive a signal (e.g., a device enable signal) from a memory controller operatively coupled to the DRAM device. The DRAM device may abort the self-refresh mode in response to receiving the signal from the memory controller. | 2012-03-29 |
20120079183 | REDUCED CURRENT REQUIREMENTS FOR DRAM SELF-REFRESH MODES - Embodiments of the invention describe systems, methods, and apparatuses to reduce the instantaneous power necessary to execute a DRAM device initiated self-refresh. Embodiments of the invention describe a DRAM device enabled to stagger self-refreshes between a plurality of banks. Staggering self-refreshes between banks reduces the current required for a DRAM self-refresh, thus reducing the amount of current required by the DRAM device. | 2012-03-29 |
20120079184 | METHODS FOR MANAGING OWNERSHIP OF REDUNDANT DATA AND SYSTEMS THEREOF - A storage system according to one embodiment includes a first storage tier; a second storage tier; logic for storing instances of a file in the first storage tier and the second storage tier; logic for receiving a request to access the file or instance thereof from a user in a group of users; logic for providing the user requesting access to the file with remote access to an instance of the file on the first storage tier that is not being used by any other user in the group of users; logic for setting an ownership status of the instance of the file on the first storage tier to owned by the user requesting access to the file; and logic for setting an ownership status of an unused instance of the file on the second storage tier from owned by the user requesting access to the file to unowned or owned by a second user which previously owned the instance of the file on the first storage tier. Additional systems, methods, and computer program products are also presented. | 2012-03-29 |
20120079185 | TAPE STORAGE SYSTEM INCLUDING MULTIPLE TAPE STORAGE APPARATUSES - A tape storage system according to one embodiment includes two or more tape storage apparatuses each having a buffer divided in fixed-length segments, and being connectable to a host, where a first of the tape storage apparatuses is configured to receive multiple data clusters and a synchronization request from a host, and, when one of the segments of the buffer is accumulated and filled with the data, to write the accumulated data onto a tape. A second of the tape storage apparatuses is connected to the first tape storage apparatus, the second tape storage apparatus being configured to receive the multiple data clusters sent from the host via the first tape storage apparatus, and being configured to write a predetermined number of data clusters accumulated in the segments thereof onto a second tape at a timing corresponding to the synchronization request. | 2012-03-29 |
20120079186 | MULTI-PROCESSOR COMPUTING SYSTEM HAVING FAST PROCESSOR RESPONSE TO CACHE AGENT REQUEST CAPACITY LIMIT WARNING - An apparatus is described that includes a plurality of processors, a plurality of cache slices and respective cache agents. Each of the cache agents have a buffer to store requests from the processors. The apparatus also includes a network between the processors and the cache slices to carry traffic of transactions that invoke the processors and/or said cache agents. The apparatus also includes communication resources between the processors and the cache agents reserved to transport one or more warnings from one or more of the cache agents to the processors that the one or more cache agents' respective buffers have reached a storage capacity threshold. | 2012-03-29 |
20120079187 | MANAGEMENT OF WRITE CACHE USING STRIDE OBJECTS - Method, system, and computer program product embodiments for, in a computing storage environment for destaging data from nonvolatile storage (NVS) to a storage unit, identifying working data on a stride basis by a processor device are provided. A multi-update bit is established for each stride in a modified cache. The multi-update bit is adapted to indicate at least one track in a working set. A schedule of destage scans is configured based on a plurality of levels of urgency. A destage operation is performed based on at least one of a number of strides examined by the destage scans, whether the multi-update bit is set, and whether an emergency level of the plurality of levels of urgency is active. | 2012-03-29 |
20120079188 | METHOD AND APPARATUS TO ALLOCATE AREA TO VIRTUAL VOLUME BASED ON OBJECT ACCESS TYPE - In accordance with an aspect of the invention, a storage system comprises a processor; a memory; a disk control module configured to receive a write command for writing to an unallocated area and to identify an object of the write command to be written as a written object; and an object allocation acquisition module configured to obtain object allocation information specifying one or more virtual volume locations for storing the written object. The disk control module allocates, to each of the one or more virtual volume locations, an area selected from a plurality of logical volumes if the written object is predefined as a randomly accessed object. The disk control module allocates to the one or more virtual volume locations a consecutive area of one logical volume if the written object is predefined as a sequentially accessed object. | 2012-03-29 |
20120079189 | INTRA-DEVICE DATA PROTECTION IN A RAID ARRAY - A system and method for intra-device data protection in a RAID array. A computer system comprises client computers and data storage arrays coupled to one another via a network. A data storage array utilizes solid-state drives and Flash memory cells for data storage. A storage controller within a data storage array is configured to identify a unit of data stored in the data storage subsystem, wherein said unit of data is stored across at least a first storage device and a second storage device of the plurality of storage devices, each of the first storage device and the second storage device storing intra-device redundancy data corresponding to the unit of data; and change an amount of intra-device redundancy data corresponding to the unit of data on only the first storage device. | 2012-03-29 |
20120079190 | OFFSET PROTECTION DATA IN A RAID ARRAY - A system and method for offset protection data in a RAID array. A computer system comprises client computers and data storage arrays coupled to one another via a network. A data storage array utilizes solid-state drives and Flash memory cells for data storage. A storage controller within a data storage array is configured to store user data in a first page of a first storage device of the plurality of storage devices; generate intra-device protection data corresponding to the user data, and store the intra-device protection data at a first offset within the first page. The controller is further configured to generate inter-device protection data corresponding to the first page, and store the inter-device protection data at a second offset within a second page in a second storage device of the plurality of storage devices, wherein the first offset is different from the second offset. | 2012-03-29 |
20120079191 | METHODS FOR MANAGING OWNERSHIP OF REDUNDANT DATA AND SYSTEMS THEREOF - A storage system according to one embodiment includes a first storage tier; a second storage tier; logic for storing instances of a file in the first storage tier and the second storage tier; logic for determining when to migrate an instance of the file associated with a first user and stored on the first storage tier to the second storage tier; logic for searching for an instance of the file or portion thereof on the second storage tier that is not associated with any user; logic for associating the instance of the file or portion thereof on the second storage tier with the first user; and logic for disassociating the instance of the file on the first storage tier from the first user. Additional systems, methods, and computer program products are also presented. | 2012-03-29 |
20120079192 | METHODS FOR MANAGING OWNERSHIP OF REDUNDANT DATA AND SYSTEMS THEREOF - A storage system according to one embodiment includes a first storage tier; a second storage tier; logic for storing instances of a file in the first storage tier and the second storage tier; logic for determining an ownership status for each instance of the file in the storage system, wherein the ownership status includes owned and unowned; logic for determining a location of each instance of the file in the storage system; logic for determining whether each instance of the file in the first storage tier is being accessed or not being accessed; logic for assigning each instance of the file to one of a plurality of indices using the determined ownership status, location, and whether the instance is being accessed; logic for receiving a request to access the file or instance thereof from a user; logic for selecting an instance of the file based on an assignment of the instance of the file to one of the indices; and logic for providing the user with access to the selected instance of the file or copy thereof. Additional systems, methods, and computer program products are also presented. | 2012-03-29 |
20120079193 | METHOD AND SYSTEM FOR DISTRIBUTING MULTIPLE STORAGE DEVICES TO MULTIPLE TIERS IN A STORAGE APPARATUS - A management system of a storage apparatus, which exercises control so as to arrange data in a storage device of a certain tier of multiple tiers, carries out a first tier definition process (a process for distributing multiple storage devices to multiple tiers based on respective storage device types of the multiple storage devices and type/tier information that denotes the corresponding relationship between multiple storage device types and multiple tiers). Subsequent to the first tier definition process, the management system acquires performance information denoting the performance of a storage device for each of the multiple storage devices. The management system carries out a second tier definition process (a process for distributing the multiple storage devices to the multiple tiers based on the performance information of multiple storage devices such that two or more storage devices of similar performance are distributed to the same tier). | 2012-03-29 |
20120079194 | METHOD OF TESTING DATA STORAGE DEVICES AND A GENDER THEREFOR - A method of testing data storage devices, the method including virtualizing data storage spaces of N data storage devices to a single virtual storage space, wherein N is a natural number equal to or greater than two, and testing the N data storage devices by performing a testing sequence on the virtual storage space. | 2012-03-29 |
20120079195 | SINGLE NODENAME CLUSTER SYSTEM FOR FIBRE CHANNEL - A system and method provides a single system image for a clustered storage network including techniques for processing data access commands between storage appliances over the cluster interconnect. The system is configured such that the cluster is assigned a single world wide nodename. Requests coming to the cluster from client initiators are directed to one or the storage appliances in the cluster, i.e. the “receiving” storage appliance. Commands received by the receiving storage appliance are examined to determine LUN value(s) in the request. If the LUN value is associated with a local storage device, the request is processed by the receiving storage appliance. If the LUN value is not associated with the receiving storage appliance, the request is conveyed over the cluster interconnect to the partner storage appliance to be processed and the appropriate data written or retrieved. | 2012-03-29 |
20120079196 | File server, file management system and file relocation method - In a file server for suppressing power consumption of a storage apparatus, when a file sharing program receives a file access from a client, the program references a mapping table. The program addresses the access to the target file in the volume of a RAID group where the target file is stored. A coupling-request reception program memorizes a coupling time for each user into a coupling history table. A grouping program applies a grouping to users whose coupling time-zones are similar. A data transfer program transfers, into the same RAID group, data of the files associated with the grouped users, thereby collecting the data into the same RAID group. Thus, the time-zone when no access is made to the RAID group (i.e., non-coupling time-zone) can be made longer. Accordingly, a spin-up/down request program makes a spin-down request to the RAID group in the non-coupling time-zone. | 2012-03-29 |
20120079197 | CARD-READING DEVICE AND METHOD FOR USING THE CARD-READING DEVICE TO ACCESS MEMORY CARD - The present invention relates to a card-reading device and a method for using the card-reading device to access a memory card, the card-reading device comprises: a central processing unit; at least one connecting unit; at least two interface unit, comprising a first interface unit connecting to the central unit and the connecting unit, and a second interface unit connecting to the central processing unit; and at least one accommodating unit, adapted for accommodating an external memory card. Moreover, through the method, a first electronic device or a second electronic device is able to access the memory card accommodated by the card-reading device. | 2012-03-29 |
20120079198 | HARDWARE ACCELERATION OF COMMONALITY FACTORING ON REMOVABLE MEDIA - Systems and methods for commonality factoring for storing data on removable storage media that may allow for highly compressed data to be stored efficiently on portable memory devices. The methods include breaking data into unique chunks and calculating identifiers, e.g., hash identifiers, based on the unique chunks. Redundant chunks can be identified by comparing identifiers of other chunks to the identifiers of unique chunks. When a redundant chunk is identified, a reference to the existing unique chunk is generated such that the chunk can be reconstituted in relation to other chunks in order to recreate the original data. One or more of the unique chunks, the identifiers, and/or the references may be stored on the portable memory device. Hardware and/or software for the chunking and/or hashing functions can reside in a host computer, a removable storage device or cartridge, and/or a removable cartridge holder. | 2012-03-29 |
20120079199 | INTELLIGENT WRITE CACHING FOR SEQUENTIAL TRACKS - Method, system, and computer program product embodiments for, in a computing storage environment for destaging data from nonvolatile storage (NVS) to a storage unit, write caching for sequential tracks by a processor device are provided. If a first track is determined to be sequential, and an earlier track is also determined to be sequential, a temporal bit associated with the earlier track is cleared to allow for destage of data of the earlier track. If a temporal bit for one of a plurality of additional tracks in one of a plurality of strides in a modified cache is determined to be not set, a stride associated with the one of the plurality of additional tracks is selected for a destage operation. If the NVS exceeds a predetermined storage threshold, a predetermined one of the plurality of strides is selected for the destage operation. | 2012-03-29 |
20120079200 | UNIFIED STREAMING MULTIPROCESSOR MEMORY - One embodiment of the present invention sets forth a technique for providing a unified memory for access by execution threads in a processing system. Several logically separate memories are combined into a single unified memory that includes a single set of shared memory banks, an allocation of space in each bank across the logical memories, a mapping rule that maps the address space of each logical memory to its partition of the shared physical memory, a circuitry including switches and multiplexers that supports the mapping, and an arbitration scheme that allocates access to the banks. | 2012-03-29 |
20120079201 | SYSTEM AND METHOD FOR EXPLICITLY MANAGING CACHE COHERENCE - One embodiment of the present invention sets forth am extension to a cache coherence protocol with two explicit control states, P (private), and R (read-only), that provide explicit program control of cache lines for which the program logic can guarantee correct behavior. In the private state, only the owner of a cache line can access the cache line for read or write operations. In the read-only state, only read operations can be performed on the cache line, thereby disallowing write operations to be performed. | 2012-03-29 |
20120079202 | MULTISTREAM PREFETCH BUFFER - A prefetching system receives a memory read request having an associated address. In response to a determination that a most significant portion of the associated address is not present within slots of an array for storing the most significant portion of predicted addresses, a prefetch FIFO (First In-First Out) counter is modified to point to a next slot of the array and a new predicted address is generated in response to the received most significant portion of the associated address and is placed in the next slot of the array. The prefetch FIFO counter cycles through the slots of the array before wrapping around to a first slot of the array for storing the most significant portion of predicted addresses. | 2012-03-29 |
20120079203 | Transaction Info Bypass for Nodes Coupled to an Interconnect Fabric - A shared resource within a module may be accessed by a request from an external requester. An external transaction request may be received from an external requester outside the module for access to the shared resource that includes control information, not all of which is needed to access the shared resource. The external transaction request may be modified to form a modified request by removing a portion of the locally unneeded control information and storing the unneeded portion of control information as an entry in a bypass buffer. A reply received from the shared resource may be modified by appending the stored portion of control information from the entry in the bypass buffer before sending the modified reply to the external requester. | 2012-03-29 |
20120079204 | Cache with Multiple Access Pipelines - Parallel pipelines are used to access a shared memory. The shared memory is accessed via a first pipeline by a processor to access cached data from the shared memory. The shared memory is accessed via a second pipeline by a memory access unit to access the shared memory. A first set of tags is maintained for use by the first pipeline to control access to the cache memory, while a second set of tags is maintained for use by the second pipeline to access the shared memory. Arbitrating for access to the cache memory for a transaction request in the first pipeline and for a transaction request in the second pipeline is performed after each pipeline has checked its respective set of tags. | 2012-03-29 |
20120079205 | METHOD AND APPARATUS FOR REDUCING PROCESSOR CACHE POLLUTION CAUSED BY AGGRESSIVE PREFETCHING - A method and apparatus for controlling a first and second cache is provided. A cache entry is received in the first cache, and the entry is identified as having an untouched status. Thereafter, the status of the cache entry is updated to accessed in response to receiving a request for at least a portion of the cache entry, and the cache entry is subsequently cast out according to a preselected cache line replacement algorithm. The cast out cache entry is stored in the second cache according to the status of the cast out cache entry. | 2012-03-29 |
20120079206 | METHOD, APPARATUS, PROXY SERVER, AND SYSTEM FOR SELECTING CACHE REPLACEMENT POLICIES - Embodiments of the present invention provide a method, an apparatus, and a proxy server for selecting cache replacement policies to reduce manual participation and switch cache replacement policies automatically. The method includes: obtaining statistical data of multiple cache replacement policies that are running simultaneously; and switching, according to an event of policy decision for cache replacement policies and the statistical data, an active cache replacement policy to a cache replacement policy that complies with a policy decision requirement. The automatic switching of cache replacement policies lowers the technical requirements on administrators. In addition, in the operation process of a proxy cache, a cache replacement policy that is applicable to a current scenario and meets a performance expectation of a user can be selected automatically, so as to make the technical solution feature good adaptability. Compared with the existing solution in which only a cache replacement policy is used throughout, the technical solution of the present invention can improve the performance of the proxy cache. | 2012-03-29 |
20120079207 | MASS STORAGE SYSTEM AND METHOD OF OPERATING THEREOF - There is provided a mass storage system and a method of operating thereof. The method comprises: a) generating one or more consistency checkpoints; b) associating each generated consistency checkpoint with a global number of snapshots generated in the storage system corresponding to time of generation of respective checkpoint; c) upon generating, placing each consistency checkpoint at the beginning of a sequence of dirty data portions which are handled in a cache memory with the help of a replacement technique with an access-based promotion; d) enabling within the sequence of dirty data portions an invariable order of consistency checkpoints and dirty data portions corresponding to volumes with generated snapshots; and e) responsive to destaging a certain consistency checkpoint, recording associated with the certain checkpoint global number of generated snapshots to a predefined storage location configured to be read during a recovery of the storage system. The invariable order can be provided by ceasing access-related promotion of all dirty data portions corresponding to all volumes with generated snapshots. | 2012-03-29 |
20120079208 | PROBE SPECULATIVE ADDRESS FILE - An apparatus to resolve cache coherency is presented. In one embodiment, the apparatus includes a microprocessor comprising one or more processing cores. The apparatus also includes a probe speculative address file unit, coupled to a cache memory, comprising a plurality of entries. Each entry includes a timer and a tag associated with a memory line. The apparatus further includes control logic to determine whether to service an incoming probe based at least in part on a timer value. | 2012-03-29 |
20120079209 | METHOD AND APPARATUS FOR IMPLEMENTING MULTI-PROCESSOR MEMORY COHERENCY - A method and an apparatus for implementing multi-processor memory coherency are disclosed. The method includes: a Level-2 (L2) cache of a first cluster receives a control signal of the first cluster for reading first data; the L2 cache of the first cluster reads the first data in a Level-1 (L1) cache of a second cluster through an Accelerator Coherency Port (ACP) of the L1 cache of the second cluster if the first data is currently maintained by the second cluster, where the L2 cache of the first cluster is connected to the ACP of the L1 cache of the second cluster; and the L2 cache of the first cluster provides the first data read to the first cluster for processing. The technical solution under the present invention implements memory coherency between clusters in the ARM Cortex-A9 architecture. | 2012-03-29 |
20120079210 | OPTIMIZED RING PROTOCOLS AND TECHNIQUES - Methods and apparatus relating to optimized ring protocols and techniques are described. In one embodiment, a first agent generates a request to write to a cache line of a cache over a first ring of a computing platform. A second agent that receives the write request forwards it to a third agent over the first ring of the computing platform. In turn, a third agent (e.g., a home agent) receives data corresponding to the write request over a second, different ring of the computing platform and writes the data to the cache. Other embodiments are also disclosed. | 2012-03-29 |
20120079211 | Coherency control with writeback ordering - Interconnect circuitry configured to provide routes for interconnecting several initiator devices and at least one recipient device including a memory. At least one of the initiator devices has a cache for storing a local copy of a subset of data items stored in the memory. The interconnect circuitry includes: a plurality of input ports and at least one output port; a plurality of paths for transmitting the transaction requests between the inputs and the at least one output; coherency control circuitry for maintaining an order in which at least some of the transaction requests to a same data storage location proceed through the interconnect circuitry. The interconnect circuitry is configured not to control the writeback transaction requests with the coherency control circuitry, such that the writeback transaction requests proceed independently of transaction requests routed through the coherency control circuitry. | 2012-03-29 |
20120079212 | ARCHITECTURE FOR SHARING CACHES AMONG MULTIPLE PROCESSES - Various embodiments of the present invention provide a system for caching information in a multi-process environment. The system includes a processor. A shared memory is communicatively coupled to the processor. The shared memory includes a set of data. A writer process is communicatively coupled to the shared memory. The write process reads and updates the set of data. A plurality of reader processes is communicatively coupled to the shared memory. Each reader process reads at least part of the set of data directly from the shared memory and sends a set of update information to the writer process. The writer process then updates the set of data stored in the shared memory based on the set of update information. | 2012-03-29 |
20120079213 | MANAGING CONCURRENT ACCESSES TO A CACHE - Various embodiments of the present invention manage concurrent accesses to a resource in a parallel computing environment. A plurality of locks is assigned to manage concurrent access to a plurality of parts of a resource. A usage of at least one of the plurality of parts of the resource is monitored. The assignment of the plurality of locks to the plurality of parts of the resource is modified based on the usage that has been monitored. | 2012-03-29 |
20120079214 | ALLOCATION AND WRITE POLICY FOR A GLUELESS AREA-EFFICIENT DIRECTORY CACHE FOR HOTLY CONTESTED CACHE LINES - Methods and apparatus relating to allocation and/or write policy for a glueless area-efficient directory cache for hotly contested cache lines are described. In one embodiment, a directory cache stores data corresponding to a caching status of a cache line. The caching status of the cache line is stored for each of a plurality of caching agents in the system. An write-on-allocate policy is used for the directory cache by using a special state (e.g., snoop-all state) that indicates one or more snoops are to be broadcasted to all agents in the system. Other embodiments are also disclosed. | 2012-03-29 |
20120079215 | Performing Mode Switching In An Unbounded Transactional Memory (UTM) System - In one embodiment, the present invention includes a method for selecting a first transaction execution mode to begin a first transaction in a unbounded transactional memory (UTM) system having a plurality of transaction execution modes. These transaction execution modes include hardware modes to execute within a cache memory of a processor, a hardware assisted mode to execute using transactional hardware of the processor and a software buffer, and a software transactional memory (STM) mode to execute without the transactional hardware. The first transaction execution mode can be selected to be a highest performant of the hardware modes if no pending transaction is executing in the STM mode, otherwise a lower performant mode can be selected. Other embodiments are described and claimed. | 2012-03-29 |
20120079216 | MEMORY CONTROL DEVICE AND METHOD - A priority control register | 2012-03-29 |
20120079217 | SOURCE SIDE WEAK EVENT IMPLEMENTATION - Systems and methods are presented to facilitate implementation of controlling memory management, e.g., garbage collection, of computer objects based upon determination of a source side weak event and associated components. A first class determines the existence of a listener and a second class, based upon an indication from the first class, determines whether the second class should “re-register for finalization” during execution of a finalizing operation. Where existence of the second class is maintained, existence of associated components such as the first class, a delegate, a listener, and the like, is continued and data, etc., continues to be published from the weak event to the listener. Where existence of the second class is no longer maintained (e.g., the second class does not re-register for finalization), the various components, e.g., the first class, the second class, a delegate, a listener, and any other objects are available for garbage collection. | 2012-03-29 |
20120079218 | CONFIGURABLE STATUS PROCESSING UNIT FOR SENSOR-ACTUATOR SYSTEMS - An electronic communication unit which is in the form of a sensor and/or actuator unit, including at least a first status information processing module having a status memory unit which stores status information for the communication unit in the form of a status data item (stat), wherein the first status information processing module further includes a masking memory unit connected to the status memory unit and also a status processing element connected to the masking memory unit, wherein the first status information processing module is designed such that at least one status information item from the status data item (stat) is selected by the masking memory unit and the resultant selective status data item (sel-stat) is processed by the status processing element such that the output of the latter provides a short status data item (k-stat) which has a shorter data word length than the selective status data item (sel-stat). | 2012-03-29 |
20120079219 | METHODS, SYSTEMS, AND DEVICES FOR MANAGEMENT OF A MEMORY SYSTEM - Methods, devices, and systems for a memory management system within an electronic device are disclosed, such as those wherein the memory management system is external to and compatible with the architecture of currently existing operating systems. One such memory management system may include a power savings manager configured to be invoked by a memory allocation manager. The power savings manager may also be configured to determine whether physical memory blocks should be active or inactive. Furthermore, the memory management system may include a driver configured to activate or deactivate a memory block in response to a system call from the power savings manager. | 2012-03-29 |
20120079220 | System and Method for Optimized Data Backup - A spilt backup agent model where a component on a host and a component on the block storage device function together logically to provide a backup agent. In certain embodiments, the mechanism provides a split backup agent model using a NDMP protocol. The NDMP protocol is an industry standard protocol that allows for backup of hosts with a single backup agent that is compatible with multiple independent software vendor (ISV) backup software. Thus with the present invention, proprietary backup software dependent host agents are not required. The NDMP protocol provides for separation of control and data connections where the control path runs between the data server on the host that needs to be backed up and backup software (e.g., a Data Management Application (DMA)) and between the backup device and the backup software. The data path runs between the host and the backup device. | 2012-03-29 |
20120079221 | System And Method For Providing Flexible Storage And Retrieval Of Snapshot Archives - A group of computers is configured to implement a block storage service. The block storage service includes a block-level storage for storing data from a set of distinct computing instances for a set of distinct users. An interface is configured to allow the set of distinct users to specify respective destinations for storing backup copies of respective data stored in the block-level storage for the distinct users. At least some of the respective destinations are for different storage systems remote from one another. A backup copy function is provided for creating backup copies of data stored in the block-level storage by the set of distinct computing instances for the set of distinct users. The backup copies are stored in different destination locations specified by respective ones of the plurality of distinct users via the interface. | 2012-03-29 |
20120079222 | Host Based Write Ordering for Asynchronous Replication - A host write based write ordering mechanism is used so the write ordering on the secondary system is derived from the write ordering applied by the host to the primary system. In this scheme any set of writes that was issued in parallel on the primary system may also be issued in parallel on the secondary system. The parallel writes provide better performance compared to absolute or strict write ordering allowing only one outstanding write per volume group. | 2012-03-29 |
20120079223 | METHODS FOR MANAGING OWNERSHIP OF REDUNDANT DATA AND SYSTEMS THEREOF - A storage system according to one embodiment includes a first storage tier; an intermediate storage tier; a second storage tier; logic for storing instances of a file in the first storage tier, the intermediate storage tier, and the second storage tier; logic for determining which of a plurality of instances of the file in the first storage tier are to be migrated to the second storage tier; logic for copying one instance of the file from the first storage tier to the intermediate storage tier; and logic for copying the instance of the file from the intermediate storage tier to the second storage tier for creating an instance of the file on the second storage tier for each instance of the file on the first storage tier that is to be migrated to the second storage tier. Additional systems, methods, and computer program products are also presented. | 2012-03-29 |
20120079224 | MAINTAINING MIRROR AND STORAGE SYSTEM COPIES OF VOLUMES AT MULTIPLE REMOTE SITES - Provided are a computer program product, system, and method for maintaining mirror and storage system copies of volumes at multiple remote sites. A first server maintains a mirror copy relationship in a computer readable storage medium between a first storage system at a first site and a second storage system at a second site to mirror data at the first storage system to the second storage system, wherein the first and second sites connect over a network. The first server performs a first point-in-time copy operation from the first storage system to a first storage system copy, wherein the data for the first storage system copy is consistent as of the determined point-in-time, wherein the point-in-time copy operation is completed upon creating a data structure indicating data for the first storage system copy as located at the first storage or the first storage system copy. The first server transmits a command to a second server to create a point-in-time copy of the second storage system. The second server processes mirror data transferred from the first server as part of the mirror copy relationship to determine when to create a second point-in-time copy from the second storage system to a second storage system copy in response to the command. The second server performs the second point-in-time copy operation, in response to determining from the mirror data to create the second point-in-time copy. | 2012-03-29 |
20120079225 | DATA PROCESSING SYSTEM - A data processing system includes a first storage system that is connected to a host device and sends and receives data to and from the host device; a second storage system that is connected to the first storage system and receives data from the first storage system; and a third storage system that is connected to the first storage system and receives data from the first storage system. The first storage system, the second storage system and the third storage system are arranged to be changeable between a first status including first and second copy pairs and a second status including a third copy pair in response to a predetermined condition at the first storage system. | 2012-03-29 |
20120079226 | COMPUTER SYSTEM AND COMPUTER SYSTEM MANAGEMENT METHOD - A computer system of the present invention selects and executes an appropriate action in a case where capacity of a pool that provides a real storage area to a virtual logical volume is insufficient. A management computer determines, based on a utilization status of each pool, whether or not there exists a prescribed pool that requires pool size expansion. The management computer, in a case where the prescribed pool is detected, selects at least any one of a volume addition method for adding an unused real volume to the prescribed pool and a data migration method for migrating data of the virtual logical volume to another pool other than the prescribed pool, and expands a pool size of the prescribed pool in accordance with the selected method. | 2012-03-29 |
20120079227 | APPLICATION MIGRATION AND POWER CONSUMPTION OPTIMIZATION IN PARTITIONED COMPUTER SYSTEM - A storage device including a migration source logical volume of an application copies data stored in the logical volume into a migration destination logical volume of the application. After the copy process is started, the storage device stores data written into the migration source logical volume as differential data without storing the data into the migration source logical volume. When the copy process is completed for the data stored in the migration source logical volume, a management computer starts copying of the differential data, and in a time interval after the copying of the data stored in the migration source logical volume is completed but before the copying of the differential data is completed, a computer being a migration destination of the application is turned ON, thereby reducing power consumption at the time of application migration. | 2012-03-29 |
20120079228 | DIGITAL COUNTER SEGMENTED INTO SHORT AND LONG ACCESS TIME MEMORY - A method performed in a memory controller for maintaining segmented counters split into primary and secondary memories, the primary memory faster. Events occur that require incrementing one of the segmented counters and the memory controller responds by incrementing a corresponding primary part in the primary memory. Each time a primary part is rolling over the memory controller determines that a secondary part should be updated. Also, the memory controller periodically determines that the secondary part of a segmented counter should be opportunistically updated. The opportunistic update is based on a probability function and a random number. The secondary part includes at least all of bits of the segmented counter not in the primary part and is stored in the secondary memory. Each time an update to the secondary part occurs, both the secondary part and primary part of the segmented counter must be updated. | 2012-03-29 |
20120079229 | DATA STORAGE OPTIMIZATION FOR A VIRTUAL PLATFORM - A method for storing data in virtual system is described. The method includes selecting virtual blocks in the virtual disk for storage of data based on contiguous logical blocks, in a disk file residing on physical storage media, that are mapped to the virtual blocks. | 2012-03-29 |
20120079230 | Selecting a Target Number of Pages for Allocation to a Partition - In an embodiment, a target number of discretionary pages is calculated for a first partition. If the target number of discretionary pages for the first partition is less than a number of the discretionary pages that are allocated to the first partition, a result page is found that is allocated to the first partition and the result page is deallocated from the first partition. If the target number of discretionary pages for the first partition is greater than the number of the discretionary pages that are allocated to the first partition, a free page is allocated to the first partition. | 2012-03-29 |
20120079231 | DATA WRITING METHOD, MEMORY CONTROLLER, AND MEMORY STORAGE APPARATUS - A data writing method and a memory controller and a memory storage apparatus using the same are provided. The data writing method includes grouping a plurality of physical blocks into a plurality of physical units, grouping the physical units into at least a data area and a free area, and configuring a plurality of logical units for mapping to the physical units of the data area. The data writing method also includes getting a physical unit from the free area, writing data in at least one of the logical units into the gotten physical unit, and writing an end mark into the gotten physical unit, and in the gotten physical unit, the end mark follows the data belonging to the at least one logical unit. Thereby, the storage space of each physical unit can be effectively used, and the lifespan of the memory storage apparatus can be prolonged. | 2012-03-29 |
20120079232 | APPARATUS, METHOD, AND SYSTEM FOR IMPLEMENTING MICRO PAGE TABLES - An apparatus, method, machine-readable medium, and system are disclosed. In one embodiment the apparatus is a micro-page table engine that includes logic that is capable of receiving a memory page request for a page in global memory address space. The apparatus also includes a translation lookaside buffer (TLB) that is capable of storing one or more memory page address translations. Additionally, the apparatus also has a page miss handler capable of performing a micro physical address lookup in a page miss handler tag table in response to the TLB not storing the memory page address translation for the page of memory referenced by the memory page request. The apparatus also includes memory management logic that is capable of managing the page miss handler tag table entries. The micro-page table engine allows the TLB to be an agent that determines whether data in a two-level memory hierarchy is in a hot region of memory or in a cold region of memory. When data is in the cold region of memory, the micro-page table engine fetches the data to the hot memory and a hot memory block is then pushed out to the cold memory area. | 2012-03-29 |
20120079233 | VECTOR LOGICAL REDUCTION OPERATION IMPLEMENTED ON A SEMICONDUCTOR CHIP - A semiconductor processor is described. The semiconductor processor includes logic circuitry to perform a logical reduction instruction. The logic circuitry has swizzle circuitry to swizzle a vector's elements so as to form a swizzle vector. The logic circuitry also has vector logic circuitry to perform a vector logic operation on said vector and said swizzle vector. | 2012-03-29 |