20th week of 2012 patent applcation highlights part 17 |
Patent application number | Title | Published |
20120119303 | Oxygen-Rich Layers Underlying BPSG - An integrated circuit structure and a method of forming the same are provided. The method includes providing a surface; performing an ionized oxygen treatment to the surface; forming an initial layer comprising silicon oxide using first process gases comprising a first oxygen-containing gas and tetraethoxysilane (TEOS); and forming a silicate glass over the initial layer. The method may further include forming a buffer layer using second process gases comprising a second oxygen-containing gas and TEOS, wherein the first and the second process gases have different oxygen-to-TEOS ratio. | 2012-05-17 |
20120119304 | SEMICONDUCTOR MEMORY - A semiconductor memory includes: a plurality of active regions AA | 2012-05-17 |
20120119305 | LAYOUT OF POWER MOSFET - A layout of a power MOSFET includes a first zigzag gate structure located on a substrate of the power MOSFET and having a first side and a second side, a first contact located on the substrate and at the first side of the first zigzag gate structure, and a second contact structure located on the substrate and at the second side of the first zigzag gate structure. | 2012-05-17 |
20120119306 | METAL GATE TRANSISTOR, INTEGRATED CIRCUITS, SYSTEMS, AND FABRICATION METHODS THEREOF - A method of forming an integrated circuit structure includes providing a gate strip in an inter-layer dielectric (ILD) layer. The gate strip comprises a metal gate electrode over a high-k gate dielectric. An electrical transmission structure is formed over the gate strip and a conductive strip is formed over the electrical transmission structure. The conductive strip has a width greater than a width of the gate strip. A contact plug is formed above the conductive strip and surrounded by an additional ILD layer. | 2012-05-17 |
20120119307 | SELF-ALIGNED CONTACT EMPLOYING A DIELECTRIC METAL OXIDE SPACER - A dielectric liner is formed on sidewalls of a gate stack and a lower contact-level dielectric material layer is deposited on the dielectric liner and planarized. The dielectric liner is recessed relative to the top surface of the lower contact-level dielectric material layer and the top surface of the gate stack. A dielectric metal oxide layer is deposited and planarized to form a dielectric metal oxide spacer that surrounds an upper portion of the gate stack. The dielectric metal oxide layer has a top surface that is coplanar with a top surface of the planarized lower contact-level dielectric material layer. Optionally, the conductive material in the gate stack may be replaced. After deposition of at least one upper contact-level dielectric material layer, at least one via hole extending to a semiconductor substrate is formed employing the dielectric metal oxide spacer as a self-aligning structure. | 2012-05-17 |
20120119308 | GATE ETCH OPTIMIZATION THROUGH SILICON DOPANT PROFILE CHANGE - Improved semiconductor devices including metal gate electrodes are formed with reduced performance variability by reducing the initial high dopant concentration at the top portion of the silicon layer overlying the metal layer. Embodiments include reducing the dopant concentration in the upper portion of the silicon layer, by implanting a counter-dopant into the upper portion of the silicon layer, removing the high dopant concentration portion and replacing it with undoped or lightly doped silicon, and applying a gettering agent to the upper surface of the silicon layer to form a thin layer with the gettered dopant, which layer can be removed or retained. | 2012-05-17 |
20120119309 | SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF - There is provided a technology capable of providing desirable operation characteristics in a field effect transistor formed in an active region surrounded by a trench type element isolation part. An element isolation part includes trench type element isolation films, diffusion preventive films each including a silicon film or a silicon oxide film, and having a thickness of 10 to 20 nm formed over the top surfaces of the trench type element isolation films, and silicon oxide films each with a thickness of 0.5 to 2 nm formed over the top surfaces of the diffusion preventive films. The composition of the diffusion preventive film is SiO | 2012-05-17 |
20120119310 | STRUCTURE AND METHOD TO FABRICATE A BODY CONTACT - A structure and method to fabricate a body contact on a transistor is disclosed. The method comprises forming a semiconductor structure with a transistor on a handle wafer. The structure is then inverted, and the handle wafer is removed. A silicided body contact is then formed on the transistor in the inverted position. The body contact may be connected to neighboring vias to connect the body contact to other structures or levels to form an integrated circuit. | 2012-05-17 |
20120119311 | SEMI-CONDUCTOR SENSOR FABRICATION - Methods of fabricating semiconductor sensor devices include steps of fabricating a hermetically sealed MEMS cavity enclosing a MEMS sensor, while forming conductive vias through the device. The devices include a first semi-conductor layer defining at least one conductive via lined with an insulator and having a lower insulating surface; a central dielectric layer above the first semiconductor layer; a second semiconductor layer in contact with the at least one conductive via, and which defines a MEMS cavity; a third semiconductor layer disposed above the second semiconductor layer, and which includes a sensor element aligned with the MEMS cavity; a cap bonded to the third semiconductor to enclose and hermetically seal the MEMS cavity; wherein the third semiconductor layer separates the cap and the second semiconductor layer. | 2012-05-17 |
20120119312 | METHOD FOR MANUFACTURING A MICROELECTROMECHANICAL COMPONENT; AND A MICROELECTROMECHANICAL COMPONENT - The invention relates to microelectromechanical components, like microelectromechanical gauges used in measuring e.g. acceleration, angular acceleration, angular velocity, or other physical quantities. The microelectromechanical component, according to the invention, comprises a microelectromechanical chip part, sealed by means of a cover part, and an electronic circuit part, suitably bonded to each other. The aim of the invention is to provide an improved method of manufacturing a microelectromechanical component, and to provide a microelectromechanical component, which is applicable for use particularly in small microelectromechanical sensor solutions. | 2012-05-17 |
20120119313 | Memory Cell With Phonon-Blocking Insulating Layer - An apparatus and associated method for a non-volatile memory cell with a phonon-blocking insulating layer. In accordance with various embodiments, a magnetic stack has a tunnel junction, ferromagnetic free layer, pinned layer, and an insulating layer that is constructed of an electrically and thermally insulative material that blocks phonons while allowing electrical transmission through at least one conductive feature. | 2012-05-17 |
20120119314 | PHOTOELECTRIC CONVERSION ELEMENT, METHOD FOR MANUFACTURING PHOTOELECTRIC CONVERSION ELEMENT, AND ELECTRONIC APPARATUS - A photoelectric conversion element includes a first electrode, a second electrode, and a photoelectric conversion element provided between the first electrode and the second electrode. The photoelectric conversion element includes a polymer. The polymer includes at least one light absorber which absorbs light and generates at least one kind of carrier. An end part of the polymer combines with a surface, which faces the second electrode, of the first electrode. | 2012-05-17 |
20120119315 | SENSING DEVICES - A sensing device ( | 2012-05-17 |
20120119316 | SOLID-STATE IMAGING DEVICE AND METHOD FOR MAKING THE SAME, AND MANUFACTURING SUBSTRATE FOR SOLID-STATE IMAGING DEVICE - A method for making a solid-state imaging device includes forming a pinning layer, which is a P-type semiconductor layer or an N-type semiconductor layer, on a first substrate by deposition; forming a semiconductor layer on the pinning layer; forming a photoelectric conversion unit in the semiconductor layer, the photoelectric conversion unit being configured to convert incident light into an electrical signal; forming, on the semiconductor layer, a transistor of a pixel unit and a transistor of a peripheral circuit unit disposed in the periphery of the pixel unit, and then forming a wiring section on the semiconductor layer; bonding a second substrate on the wiring section; and removing the first substrate after the second substrate is bonded. | 2012-05-17 |
20120119317 | ANTIBLOOMING IMAGING APPARATUS, SYSTEMS, AND METHODS - Apparatus, systems, and methods are described to assist in reducing dark current in an active pixel sensor. In various embodiments, a potential barrier arrangement is configured to block the flow of charge carriers generated outside a photosensitive region. In various embodiments, a potential well-potential barrier arrangement is formed to direct charge carriers away from the photosensitive region during an integration time. | 2012-05-17 |
20120119318 | SEMICONDUCTOR DEVICE WITH LATERAL ELEMENT - In a semiconductor device in which a first electrode and a second electrode are disposed on a surface of a first conductivity-type semiconductor layer of a semiconductor substrate and a lateral element is formed to cause an electric current between the first electrode and the second electrode, a scroll-shaped resistive field plate is disposed on the semiconductor layer across an insulation film. The resistive field plate extends toward the second electrode while surrounding a periphery of the first electrode in a scroll shape. A resistance value of a total resistance of the resistive field plate is in a range between 90 kΩ and 90 MΩ. | 2012-05-17 |
20120119319 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first semiconductor region and a second semiconductor region provided on a main surface of a substrate, being apart from each other and having first conductivity; a third semiconductor region provided between the first semiconductor region and the second semiconductor region and having second conductivity opposite to the first conductivity; a fourth semiconductor region provided on a main surface of the substrate, connected to the third semiconductor region, manufactured together with the third semiconductor region in the same manufacturing process, and having the conductivity same as that of the third semiconductor region; and trenches made on the main surface of the fourth semiconductor region and having a depth smaller than a junction depth of the fourth semiconductor region. | 2012-05-17 |
20120119320 | DIODE FOR ADJUSTING PIN RESISTANCE OF A SEMICONDUCTOR DEVICE - A diode comprises a P-type well formed in a semiconductor substrate, at least one N-type impurity doping area formed in the P-type well, an isolation area formed to surround the N-type impurity doping area, a P-type impurity doping area formed to surround the isolation area, first contacts formed in the N-type impurity doping area in a single row or a plurality of rows, and second contacts formed in the P-type impurity doping area in a single row or a plurality of rows, wherein pin resistance can be adjusted through changing any one of a distance between the N-type impurity doping area and the P-type impurity doping area, a contact pitch between the first contacts, and a contact pitch between the second contacts. | 2012-05-17 |
20120119321 | TOPOGRAPHY BASED PATTERNING - A mask having features formed by self-organizing material, such as diblock copolymers, is formed on a partially fabricated integrated circuit. A copolymer template, or seed layer, is formed on the surface of the partially fabricated integrated circuit. To form the seed layer, diblock copolymers, composed of two immiscible blocks, are deposited in the space between copolymer alignment guides. The copolymers self-organize, with the guides guiding the self-organization and with each block aggregating with other blocks of the same type, thereby forming the seed layer. Supplemental diblock copolymers are deposited over the seed layer. The copolymers in the seed layer guide self-organization of the supplemental copolymers, thereby vertically extending the pattern formed by the copolymers in the seed layer. Block species are subsequently selectively removed to form a pattern of voids defined by the remaining block species, which form a mask that can be used to pattern an underlying substrate. | 2012-05-17 |
20120119322 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A plurality of light-shielding films etc. are formed on a surface of a first insulating film. Then, a dummy pattern is formed on a surface of a second insulating film between adjoining ones of the light-shielding films etc., so that a height of the dummy pattern is equal to that of the second insulating film on the light-shielding films etc., as measured from the surface of the first insulating film. Thereafter, a third insulating film covering the dummy pattern and having a flat surface is formed over the surface of the second insulating film. Subsequently, a base layer is bonded to a support substrate so that the flat surface of the third insulating film faces the support substrate. A semiconductor device is manufactured in this manner. | 2012-05-17 |
20120119323 | SOS SUBSTRATE HAVING LOW SURFACE DEFECT DENSITY - A method of making bonded SOS substrate with a semiconductor film on or above a sapphire substrate by implanting ions from a surface of the semiconductor substrate to form an ion-implanted layer; activating at least a surface of one of the sapphire substrate and the semiconductor substrate from which the ions have been implanted; bonding the surface of the semiconductor substrate and the surface of the sapphire substrate at a temperature of from 50° C. to 350° C.; heating the bonded substrates at a maximum temperature of from 200° C. to 350° C.; and irradiating visible light from a sapphire substrate side or a semiconductor substrate side to the ion-implanted layer of the semiconductor substrate to make the interface of the ion-implanted layer brittle at a temperature of the bonded body higher than the temperature at which the surfaces were bonded, to transfer the semiconductor film to the sapphire substrate. | 2012-05-17 |
20120119324 | MEMS ISOLATION STRUCTURES - A device may comprise a substrate formed of a first semiconductor material and a trench formed in the substrate. A second semiconductor material may be formed in the trench. The second semiconductor material may have first and second portions that are isolated with respect to one another and that are isolated with respect to the first semiconductor material. | 2012-05-17 |
20120119325 | GUARD TRENCH - A device may comprise a substrate formed of a first semiconductor material, a first trench formed in the substrate, a second trench formed in the substrate proximate the first trench, an oxide layer formed in the first trench and the second trench, and a second semiconductor material formed upon the oxide layer. The oxide layer in the second trench may be adapted to mitigate undercut of the oxide layer in the first trench during an etching process. | 2012-05-17 |
20120119326 | CAPACITOR AND SEMICONDUCTOR DEVICE - A capacitor includes first electrode patterns and second electrode patterns disposed alternately on a plane, each of the first electrode patterns having a linear shape and extending in a first direction from a first end to a third end with a first length, each of the second electrodes having a linear shape and extending in said first direction from a second end to a fourth end with a second length shorter than the first length, a first wiring pattern supplying a first voltage to the first electrode patterns by first via-plugs, and a second wiring pattern supplying a second voltage to the second electrode patterns by second via-plugs, wherein the first end of the first electrode pattern extends beyond the second end of the second electrode pattern and the third end of the first electrode pattern extends beyond the fourth end of said the electrode. | 2012-05-17 |
20120119327 | CAPACITOR AND SEMICONDUCTOR DEVICE INCLUDING A CAPACITOR - A capacitor in a semiconductor memory device comprises a lower electrode on a substrate that is formed of a conductive metal oxide having a rutile crystalline structure, a titanium oxide dielectric layer on the lower electrode that has a rutile crystalline structure and includes impurities for reducing a leakage current, and an upper electrode on the titanium oxide dielectric layer. A method of forming a capacitor in a semiconductor device comprise steps of forming a lower electrode on a substrate that includes a conductive metal oxide having a rutile crystalline structure, forming a titanium oxide dielectric layer on the lower electrode that has a rutile crystalline structure and impurities for reducing a leakage current, and forming an upper electrode on the titanium oxide dielectric layer. | 2012-05-17 |
20120119328 | Dielectric Thin Film Element and Method for Producing the Same - A dielectric thin film element that includes a substrate, a close-adhesion layer formed on one principal surface of the substrate, a capacitance section having a lower electrode layer formed on the close-adhesion layer, a dielectric layer formed on the lower electrode layer, and an upper electrode layer formed on the dielectric layer, and a protective layer formed to cover the capacitance section, wherein the end of the close-adhesion layer is exposed from the protective layer. | 2012-05-17 |
20120119329 | Method of Forming Top Electrode for Capacitor and Interconnection in Integrated Passive Device (IPD) - A method of manufacturing a semiconductor device includes providing a substrate having a first conductive layer disposed on a top surface of the substrate. A high resistivity layer is formed over the substrate and the first conductive layer. A dielectric layer is deposited over the substrate, first conductive layer and high resistivity layer. A portion of the dielectric layer, high resistivity layer, and first conductive layer forms a capacitor stack. A first passivation layer is formed over the dielectric layer. A second conductive layer is formed over the capacitor stack and a portion of the first passivation layer. A first opening is etched in the dielectric layer to expose a surface of the high resistivity layer. A third and fourth conductive layer is deposited over the first opening in the dielectric layer and a portion of the first passivation layer. | 2012-05-17 |
20120119330 | Adjustable Holding Voltage ESD Protection Device - An electrostatic discharge (ESD) protection structure comprises a bipolar PNP transistor having an emitter formed by a first high voltage P type implanted region disposed underneath a first P+ region and a collector formed by a second high voltage P type implanted region disposed underneath a second P+ region. The ESD protection structure can have an adjustable threshold voltage by controlling the distance between the first high voltage P type implanted region and the second high voltage P type implanted region. Based upon a basic ESD protection structure, the ESD protection device can provide a reliable ESD protection for semiconductor devices having different voltage ratings. | 2012-05-17 |
20120119331 | Area-Efficient High Voltage Bipolar-Based ESD Protection Targeting Narrow Design Windows - An area-efficient, high voltage, single polarity ESD protection device ( | 2012-05-17 |
20120119332 | PROCESS FOR PRODUCING A SEMICONDUCTOR-ON-SAPPHIRE ARTICLE - A process for producing a semiconductor-on-sapphire article, including: forming a barrier layer and a semiconductor layer on a sapphire substrate, the barrier layer being disposed between the sapphire substrate and the semiconductor layer to inhibit at least one of aluminium from the sapphire and extended defects arising from the sapphire-semiconductor interface from entering the semiconductor layer; wherein the semiconductor is at least one of silicon and a silicon-germanium alloy. | 2012-05-17 |
20120119333 | PRODUCT CHIPS AND DIE WITH A FEATURE PATTERN THAT CONTAINS INFORMATION RELATING TO THE PRODUCT CHIP - Product chips and die that include a pattern of features formed in a metallization level of a back-end-of-line (BEOL) wiring structure. The features in the pattern contain information relating to the die, such as a unique identifier that includes a wafer identification used to fabricate the die and a product chip location for the die on a wafer. The features may be imaged with the assistance of a beam of electromagnetic radiation that penetrates into a packaged die and is altered by the presence of the features in a way that promotes imaging. | 2012-05-17 |
20120119334 | LASER MACHINING METHOD AND CHIP - While reliably cutting an object to be processed, the strength of the resulting chips is improved. An object to be processed | 2012-05-17 |
20120119335 | Semiconductor Device With A Plurality Of Mark Through Substrate Vias - The present invention relates to a semiconductor device with a plurality of mark through substrate vias, comprising a semiconductor substrate, a plurality of original through substrate vias and a plurality of mark through substrate vias. The original through substrate vias and the mark through substrate vias are disposed in the semiconductor substrate and protrude from the backside surface of the semiconductor substrate. The mark through substrate vias are added at a specific position and/or in a specific pattern and serve as a fiducial mark, which facilitates identifying to the position and direction on the backside surface. Thus, the redistribution layer (RDL) or the special equipment for achieving the backside alignment (BSA) is not necessary. | 2012-05-17 |
20120119336 | METHOD FOR MANUFACTURING BONDED WAFER - A method for manufacturing a bonded wafer having a semiconductor film on a handle substrate involving the steps of: implanting ions into a semiconductor substrate to form an ion-implanted layer; subjecting the surface of at least one of the semiconductor substrate and the handle substrate to a surface activation treatment; bonding the surface of the semiconductor substrate to the surface of the handle substrate at a temperature from 50° C. to 350° C.; heating the bonded substrates at a maximum temperature from 200° C. to 350° C. to obtain a bonded body; and transferring a semiconductor film to the handle substrate by subjecting the bonded body to a temperature 30° C. to 100° C. higher than the bonding temperature, and irradiating the bonded body with visible light from a handle or semiconductor substrate side toward the ion-implanted layer of the semiconductor substrate to embrittle the interface of the ion-implanted layer. | 2012-05-17 |
20120119337 | SUBSTRATE PROCESSING APPARATUS, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - Provided is a substrate processing apparatus capable of suppressing accumulation of reaction products or decomposed matters on an inner wall of a nozzle and suppressing scattering of foreign substances in a process chamber. The substrate processing apparatus includes a process chamber, a heating unit, a source gas supply unit, a source gas nozzle, an exhaust unit, and a control unit configured to control at least the heating unit, the source gas supply unit and the exhaust unit. The source gas nozzle is disposed at a region in the process chamber, in which a first process gas is not decomposed even under a temperature in the process chamber higher than a pyrolysis temperature of the first process gas, and the control unit supplies the first process gas into the process chamber two or more times at different flow velocities to prevent the first process gas from being mixed. | 2012-05-17 |
20120119338 | Semiconductor Device And Method Of Manufacturing Semiconductor Device - A semiconductor chip includes a magnetic storage device and includes an electrode pad on a first face. The semiconductor chip is coated with a magnetic shield layer in a state in which at least the electrode pad is exposed. The semiconductor chip is mounted on an interconnect substrate through a bump. At least one of the semiconductor chip and the interconnect substrate includes a convex portion, and the bump is disposed over the convex portion. | 2012-05-17 |
20120119339 | Semiconductor Device and Manufacturing Method of the Same - With the use of a conductive shield formed on the top or bottom side of a semiconductor integrated circuit, an electrostatic breakdown (malfunctions of the circuit or damages of a semiconductor element) of the semiconductor integrated circuit due to electrostatic discharge is prevented, and sufficient communication capability is obtained. With the use of a pair of insulators which sandwiches the semiconductor integrated circuit, a highly reliable semiconductor device that is reduced in thickness and size and has resistance to an external stress can be provided. A semiconductor device can be manufactured with high yield while defects of shapes and characteristics due to an external stress or electrostatic discharge are prevented in the manufacturing process. | 2012-05-17 |
20120119340 | SHIELDED SEMICONDUCTOR DEVICE STRUCTURE - In one embodiment, a semiconductor device is formed to include a plurality of conductor layers that interconnect electrical signals between semiconductor elements of the semiconductor device. A metal shield layer is formed overlying a portion of the plurality of conductor layers. A signal re-distribution layer is formed overlying the metal shield layer. | 2012-05-17 |
20120119341 | Semiconductor packages with reduced solder voiding - An example semiconductor package with reduced solder voiding is described, which has a leadframe having an I/O pad and a thermal pad, a fabricated semiconductor die having a bond pad, where the fabricated semiconductor die is attached to a top surface of the thermal pad, and a wire bond connecting the bond pad to the I/O pad, where a bottom surface of the thermal pad has channels. | 2012-05-17 |
20120119342 | ADVANCED QUAD FLAT NON-LEADED PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - The advanced quad flat non-leaded package structure includes a carrier, a chip, a plurality of wires, and a molding compound. The carrier includes a die pad and a plurality of leads. The inner leads of the leads are designed to possess incurved sidewalls for enhancing the adhesion between the inner leads and the surrounding molding compound. | 2012-05-17 |
20120119343 | STACKED LEADFRAME IMPLEMENTATION FOR DC/DC CONVERTOR POWER MODULE INCORPORATING A STACKED CONTROLLER AND STACKED LEADFRAME CONSTRUCTION METHODOLOGY - Methods and systems are described for enabling the efficient fabrication of small form factor power converter packages and other devices using stacked leadframes. | 2012-05-17 |
20120119344 | MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES - Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. One such method includes forming a plurality of apertures in a substrate with the apertures arranged in an array, and, after forming the apertures, attaching the substrate to a lead frame having a plurality of pads with the apertures in the substrate aligned with corresponding pads in the lead frame. Another method includes providing a partially cured substrate, coupling the partially cured substrate to a plurality of leads, attaching a microelectronic die to the leads, and electrically connecting the microelectronic die to the leads. | 2012-05-17 |
20120119345 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DEVICE MOUNT AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base substrate having a base bottom side and a base top side; mounting an integrated circuit perpendicular to the base top side, the integrated circuit having a first conductor partially exposed at a first end facing and connected to the base top side; and forming an encapsulation over the integrated circuit. | 2012-05-17 |
20120119346 | SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME - Disclosed are a semiconductor package and a method of manufacturing the same. The semiconductor package comprises a package cap which is capable of radiating high temperatures and performs a shield function preventing transmission of electromagnetic waves into and/or out of the semiconductor package. The semiconductor package including the package cap prevents chip malfunctions and improves device reliability. The package cap is positioned to cover first and second semiconductor chips of a semiconductor package. | 2012-05-17 |
20120119347 | SEMICONDUCTOR DEVICE - A semiconductor device comprises at least a semiconductor module including a semiconductor chip, a heat sink thermally connected to the semiconductor chip and a seal member for covering and sealing the semiconductor chip and the heat sink in such a manner as to expose the heat radiation surface of the heat sink. The radiation surface is cooled by a refrigerant. An opening is formed in a part of the seal member as a refrigerant path through which the refrigerant flows. | 2012-05-17 |
20120119348 | Semiconductor Device and Method of Electrically Connecting a Shielding Layer to Ground Through a Conductive Via Disposed in Peripheral Region around Semiconductor Die - A semiconductor device is made by mounting a plurality of semiconductor die to a substrate, depositing an encapsulant over the substrate and semiconductor die, forming a shielding layer over the semiconductor die, creating a channel in a peripheral region around the semiconductor die through the shielding layer, encapsulant and substrate at least to a ground plane within the substrate, depositing a conductive material in the channel, and removing a portion of the conductive material in the channel to create conductive vias in the channel which provide electrical connection between the shielding layer and ground plane. An interconnect structure is formed on the substrate and are electrically connected to the ground plane. Solder bumps are formed on a backside of the substrate opposite the semiconductor die. The shielding layer is connected to a ground point through the conductive via, ground plane, interconnect structure, and solder bumps of the substrate. | 2012-05-17 |
20120119349 | INSULATION SHEET MADE FROM SILICON NITRIDE, AND SEMICONDUCTOR MODULE STRUCTURE USING THE SAME - An insulation sheet made from silicon nitride comprising: a sheet-shaped silicon-nitride substrate which contains β-silicon-nitride crystal grains as a main phase; and a surface layer which is formed on one face or both front and back faces of surfaces of the silicon-nitride substrate and is formed from a resin or a metal which includes at least one element selected from among In, Sn, Al, Ag, Au, Cu, Ni, Pb, Pd, Sr, Ce, Fe, Nb, Ta, V and Ti. A semiconductor module structure using the insulation sheet made from silicon nitride. | 2012-05-17 |
20120119350 | Heat Sink Module - An improved heat sink module includes a main body and at least one diode. Mounting brackets, each having a through hole, extend from the outer periphery of the arcuate main body. A plurality of engaging holes are formed on the backside of the main body and each have at least one vent slot. To increase the heat dissipation area and yield rate of the main body, a plurality of upright, alternately arranged first and second fins are provided on the front side of the main body. The first fins extend between the inner and the outer peripheries of the main body, whereas the second fins extend from the outer periphery toward the inner periphery but are spaced therefrom. Each diode is peripherally provided with engaging ribs and has a wired end. The vent slots allow the at least one diode to be inserted into the engaging holes without difficulty. | 2012-05-17 |
20120119351 | SYSTEM FOR CLAMPING HEAT SINK - A system for clamping a heat sink that prevents excessive clamping force is provided. The system may include a heat sink, a semiconductor device, a printed circuit board, and a cover. The semiconductor device may be mounted onto the circuit board and attached to the cover. The heat sink may be designed to interface with the semiconductor device to transfer heat away from the semiconductor device and dissipate the heat into the environment. Accordingly, the heat sink may be clamped into a tight mechanical connection with the semiconductor device to minimize thermal resistance between the semiconductor device and the heat sink. To prevent excessive clamping force from damaging the semiconductor device, loading columns may extend between the cover and the heat sink. | 2012-05-17 |
20120119352 | ELECTROLESS GOLD PLATING SOLUTION FOR FORMING FINE GOLD STRUCTURE, METHOD OF FORMING FINE GOLD STRUCTURE USING SAME, AND FINE GOLD STRUCTURE FORMED USING SAME - An electroless gold plating solution with which one or more openings formed in a resist overlying a substrate can be filled in a short time, the openings having a width on the order of micrometer, in particular, 100 μm or smaller, in terms of the width of the exposed substrate area, and having a height of 3 μm or larger. The electroless gold plating solution contains a deposition accelerator for deposition in fine areas, and a microfine pattern of 100 μm or finer is formed therefrom. | 2012-05-17 |
20120119353 | UNDERFILL METHOD AND CHIP PACKAGE - A method of fabricating a chip package is provided. The chip package includes a laminate, a chip and conductive elements interposed between the chip and the laminate by which signals are transmitted among the chip and the laminate. The method includes dispensing a first underfill in a space defined between opposing faces of the chip and the laminate and dispensing a second underfill at least at a portion of an edge of the chip, the second underfill including a high aspect ratio material. | 2012-05-17 |
20120119354 | Protecting Flip-Chip Package using Pre-Applied Fillet - A die has a first surface, a second surface opposite the first surface, and sidewalls includes a first portion and a second portion, wherein the first portion is closer to the first surface than the second portion. A fillet contacts the first portion of sidewalls of the die and encircles the die. A work piece is bonded to the die through solder bumps, with the second surface facing the work piece. A first underfill is filled a gap between the die and the work piece, wherein the first underfill contacts the fillet, and wherein the first underfill and the fillet are formed of different materials. | 2012-05-17 |
20120119355 | INTEGRATED CIRCUIT STRUCTURE AND METHOD OF FORMING THE SAME - A method of forming an integrated circuit structure comprises the steps of: providing a semiconductor substrate having a first side and a second side opposite the first side; forming a hole extending from the first side of the semiconductor substrate into the semiconductor substrate; filling the hole with conductive material; thinning the second side of the semiconductor substrate to a first predetermined thickness, so that the bottom of the hole does not protrude from the second side of the semiconductor substrate; and etching the second side of the semiconductor to substrate to a second predetermined thickness, thereby exposing the bottom of the hole. | 2012-05-17 |
20120119356 | SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR DEVICE - A semiconductor apparatus includes a semiconductor chip in which a plurality of electrode pads are provided on a main surface, and a plurality of bump electrodes are provided on the electrode pads of the semiconductor chip. The semiconductor apparatus also includes a wired board which is allocated in a side of the main surface of the semiconductor chip, and is positioned in a central area of the main surface of the semiconductor chip so as to be separated from an edge part of the semiconductor chip by at least 50 μm or more. The semiconductor apparatus also includes a plurality of external terminals which are provided on the wired board, and which are electrically connected to a plurality of bump electrodes through wirings of the wired board, and sealing part which is provided between the semiconductor chip and the wired board, is made of underfill material that covers a connection part between the bump electrode and the wiring. | 2012-05-17 |
20120119357 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus having stacked first and second chips includes a first through line of the first chip configured to receive a first coding signal and be electrically connected to a first through line of the second chip; a second through line of the first chip configured to receive a second coding signal; and a second through line of the second chip configured to be electrically connected to the first through line of the first chip and receive the first coding signal. | 2012-05-17 |
20120119358 | SEMICONDIUCTOR PACKAGE SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein is a semiconductor package substrate including: a substrate for package having connection pads; and a solder resist layer formed on one surface or both surfaces of the substrate for package and having openings exposing the connection pads, wherein the solder resist layer includes a roughness layer formed thereon. | 2012-05-17 |
20120119359 | BUMP STRUCTURE AND SEMICONDUCTOR PACKAGE HAVING THE BUMP STRUCTURE - Provided are a bump structure includes a first bump and a second bump, a semiconductor package including the same, and a method of manufacturing the same. The bump structure includes: first bump provided on a connection pad of a substrate, the first bump including a plurality of nano-wires extending from the connection pad and a body connecting end portions of the plurality of nano-wires; and a second bump provided on the body of the first bump. | 2012-05-17 |
20120119360 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONNECTION STRUCTURE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching a connection post to the substrate, the connection post having a post top and a post side; mounting an integrated circuit die on the substrate, the integrated circuit die having a top die surface; and forming a package body on the substrate, the connection post, and the integrated circuit die. | 2012-05-17 |
20120119361 | Semiconductor Device and Method of Forming Overlapping Semiconductor Die with Coplanar Vertical Interconnect Structure - A semiconductor device is made by forming first and interconnect structures over a first semiconductor die. A third interconnect structure is formed in proximity to the first die. A second semiconductor die is mounted over the second and third interconnect structures. An encapsulant is deposited over the first and second die and first, second, and third interconnect structures. A backside of the second die is substantially coplanar with the first interconnect structure and a backside of the first semiconductor die is substantially coplanar with the third interconnect structure. The first interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the second die. The third interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the first die. | 2012-05-17 |
20120119362 | NI PLATING OF A BLM EDGE FOR PB-FREE C4 UNDERCUT CONTROL - A structure and a method of manufacturing a Pb-free Controlled Collapse Chip Connection (C4) with a Ball Limiting Metallurgy (BLM) structure for semiconductor chip packaging that reduce chip-level cracking during the Back End of Line (BEOL) processes of chip-join cool-down. An edge of the BLM structure that is subject to tensile stress during chip-join cool down is protected from undercut of a metal seed layer, caused by wet etch of the chip to remove metal layers from the chip's surface and solder reflow, by an electroplated barrier layer, which covers a corresponding edge of the metal seed layer. | 2012-05-17 |
20120119363 | GRAIN REFINEMENT BY PRECIPITATE FORMATION IN Pb-FREE ALLOYS OF TIN - Micro-addition of a metal to a Sn-based lead-free C4 ball is employed to enhance reliability. Specifically, a metal having a low solubility in Sn is added in a small quantity corresponding to less than 1% in atomic concentration. Due to the low solubility of the added metal, fine precipitates are formed during solidification of the C4 ball, which act as nucleation sites for formation multiple grains in the solidified C4 ball. The fine precipitates also inhibit rapid grain growth by plugging grain boundaries and act as agents for pinning dislocations in the C4 ball. The grain boundaries enable grain boundary sliding for mitigation of stress during thermal cycling of the semiconductor chip and the package on the C4 ball. Further, the fine precipitates prevent electromigration along the grain boundaries due to their pinned nature. | 2012-05-17 |
20120119364 | ADDING CAP TO COPPER PASSIVATION FLOW FOR ELECTROLESS PLATING - An integrated circuit includes a metal seed layer contacting a metal element of a top interconnect layer, a plated copper pad over the seed layer, a plated metal cap layer on the top surface of the copper pad, an upper protective overcoat covering a lateral surface of the copper pad and overlapping a top surface of the cap layer with a bond pad opening exposing the cap layer, and a bond pad of electroless plated metal in the bond pad opening. | 2012-05-17 |
20120119365 | INTEGRATED CIRCUIT DEVICES HAVING CONDUCTIVE STRUCTURES WITH DIFFERENT CROSS SECTIONS - A semiconductor device includes a first conductive structure and a second conductive structure. The first conductive structure is formed in a first region of a substrate, and includes a first polysilicon layer pattern, a first conductive layer pattern having a resistance smaller than that of the first polysilicon layer pattern, and a first hard mask. The second conductive structure is formed in a second region of the substrate and has a thickness substantially the same as that of the first conductive structure. The second conductive structure includes a second polysilicon layer pattern, a second conductive layer pattern having a resistance smaller than that of the second polysilicon layer pattern and having a thickness different from that of the first conductive layer pattern, and a second hard mask. | 2012-05-17 |
20120119366 | ELECTROMIGRATION RESISTANT VIA-TO-LINE INTERCONNECT - A liner-to-liner direct contact is formed between an upper metallic liner of a conductive via and a lower metallic liner of a metal line below. The liner-to-liner contact impedes abrupt electromigration failures and enhances electromigration resistance of the metal interconnect structure. The at least one dielectric material portion may include a plurality of dielectric material portions arranged to insure direct contact of between the upper metallic liner and the lower metallic liner. Alternatively, the at least one dielectric material portion may comprise a single dielectric portion of which the area has a sufficient lateral overlap with the area of the conductive via to insure that a liner-to-liner direct contact is formed within the range of allowed lithographic overlay variations. | 2012-05-17 |
20120119367 | CONDUCTIVE PADS DEFINED BY EMBEDDED TRACES - An assembly and method of making same are provided. The assembly can include a first component including a dielectric region having an exposed surface, a conductive pad at the surface defined by a conductive element having at least a portion extending in an oscillating or spiral path along the surface, and a an electrically conductive bonding material joined to the conductive pad and bridging an exposed portion of the dielectric surface between adjacent segments. The conductive pad can permit electrical interconnection of the first component with a second component having a terminal joined to the pad through the electrically conductive bonding material. The path of the conductive element may or may not overlap or cross itself. | 2012-05-17 |
20120119368 | SEMICONDUCTOR MEMORY DEVICE - In one embodiment, a semiconductor memory device includes a substrate, and device regions formed in the substrate to extend in a first direction which is parallel to a principal plane of the substrate. The device further includes select gates disposed on the substrate to extend in a second direction which is perpendicular to the first direction, and a contact region provided between the select gates on the substrate and including contact plugs disposed on the respective device regions. Further, the contact region includes partial regions, in each of which N contact plugs are disposed on N successive device regions to be arranged on a straight line being non-parallel to the first and second directions, where N is an integer of 2 or more. Further, the contact region includes the partial regions of at least two types whose values of N are different. | 2012-05-17 |
20120119369 | SEMICONDUCTOR DEVICE - A semiconductor device includes a main current external electrode for connecting a high-voltage main current electrode of a power semiconductor element to the outside, and a resin case into which the main current external electrode is press fitted. The main current external electrode has a press-fitted fixing portion and a claw fixing portion for fixation to the resin case. The claw fixing portion includes a projection passing through a through hole defined in the resin case, and having a bendable claw portion at its tip end. | 2012-05-17 |
20120119370 | SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - Provided are a semiconductor package and a semiconductor system including the semiconductor package. The semiconductor package includes a semiconductor device and an interconnect structure electrically connected to the semiconductor device and delivering a signal from the semiconductor device, wherein the interconnect structure includes an anodized insulation region and an interconnect adjacent to and defined by the anodized insulation region. | 2012-05-17 |
20120119371 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - There is provided a method of fabricating a semiconductor device including: forming an insulating film on a semiconductor substrate; forming a pad electrode on the insulating film; forming a protective film on the pad electrode; forming, on the protective film, a resist equipped with an open portion in a first region corresponding to part of the pad electrode; by using the resist as a mask, etching the protective film and etching the first region of part of the pad electrode to a predetermined depth; etching the protective film on a second region that surrounds the first region of the pad electrode; and removing the resist. | 2012-05-17 |
20120119372 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: a substrate including an electrode pad on a surface; a semiconductor chip placed on the substrate so as to be electrically connected to the electrode pad; a first resin layer which is formed on the substrate and is also filled between the substrate and the semiconductor chip; and a second resin layer, laminated on the first resin layer, which has an elastic modulus larger than that of the first resin layer. | 2012-05-17 |
20120119373 | WAFER LEVEL SEMICONDUCTOR PACKAGE AND MANUFACTURING METHODS THEREOF - A semiconductor package includes at least one semiconductor die having an active surface, an interposer element having an upper surface and a lower surface, a package body, and a lower redistribution layer. The interposer element has at least one conductive via extending between the upper surface and the lower surface. The package body encapsulates portions of the semiconductor die and portions of the interposer element. The lower redistribution layer electrically connects the interposer element to the active surface of the semiconductor die. | 2012-05-17 |
20120119374 | THROUGH SILICON VIA WITH IMPROVED RELIABILITY - A semiconductor device includes a substrate having a top surface and a bottom surface, and a through-silicon via (TSV) extending from the top surface of the substrate to the bottom surface of the substrate, the TSV having a height and a side profile extending along a longitudinal axis, wherein the side profile has an upper segment forming a first angle relative to the longitudinal axis, and a lower segment forming a second angle relative to the longitudinal axis, the second angle being different from the first angle, and wherein the lower segment has a height that is less than 20% of the height of the TSV. | 2012-05-17 |
20120119375 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - In a manufacturing method of a semiconductor structure, a substrate having a front surface and a back surface is provided. The front surface has a device layer thereon and conductive plugs electrically connected to the device layer. A thinning process is performed on the back surface of the substrate, such that the back surface of the substrate and surfaces of the conductive plugs have a distance therebetween. Holes are formed in the substrate from the back surface to the conductive plugs, so as to form a porous film. An oxidization process is performed, such that the porous film correspondingly is reacted to form an oxide material layer. A polishing process is performed on the oxide material layer to expose the surfaces of the conductive plugs. | 2012-05-17 |
20120119376 | SEMICONDUCTOR CHIPS AND METHODS OF FORMING THE SAME - Provided are a semiconductor chip and a method of manufacturing the same. The semiconductor chip includes a substrate having a first side and a second side facing each other, and a through electrode being disposed in a hole penetrating the substrate, wherein an opening surrounded by the through electrode is disposed in the hole, wherein the opening comprises a first end adjacent to the first side of the substrate and a second end adjacent to the second side of the substrate | 2012-05-17 |
20120119377 | WIRING SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING WIRING SUBSTRATE - A wiring substrate is provided with a first wiring layer including a first land, a first insulative layer formed on the first wiring layer, a second wiring layer formed on the first insulative layer, a second insulative layer formed on the second wiring layer, and a via formed extending through the first insulative layer and the second insulative layer in a thicknesswise direction. The via includes one end, which is electrically connected to the first land of the first wiring layer, and another end, which is located opposed to the one end and serves as a pad to which a mounted electronic component is electrically connected. The second wiring layer includes a coupling portion electrically connected to the via. The coupling portion of the second wiring has a width that is smaller than a diameter of the via. | 2012-05-17 |
20120119378 | SEMICONDUCTOR PACKAGES AND METHODS OF PACKAGING SEMICONDUCTOR DEVICES - Semiconductor packages and methods of forming a semiconductor package are disclosed. The method includes providing at least one die having first and second surfaces. The second surface of the die includes a plurality of conductive pads. A support carrier is provided and the at least one die is attached to the support carrier. The first surface of the at least one die is facing the support carrier. A cap having first and second surfaces is formed to encapsulate the at least one die. The second surface of the cap is disposed at a different plane than the second surface of the die. | 2012-05-17 |
20120119379 | ELECTRIC PART PACKAGE AND MANUFACTURING METHOD THEREOF - A disclosed electric part package includes a supporting member that includes a first area in which an electric part is arranged, and a second area in which a first opening is positioned, the second area being isolated from the first area; a resin part provided on the supporting member thereby to cover the electric part arranged in the first area, the resin part including an electric terminal exposed in the first opening of the supporting member; and a wiring structure provided on the resin part, the wiring structure being electrically connected to the electric part and the electric terminal of the resin part. | 2012-05-17 |
20120119380 | MICROELECTRONIC PACKAGE WITH TERMINALS ON DIELECTRIC MASS - A package for a microelectronic element, such as a semiconductor chip, has a dielectric mass overlying the package substrate and microelectronic element and has top terminals exposed at the top surface of the dielectric mass. Traces extending along edge surfaces of the dielectric mass desirably connect the top terminals to bottom terminals on the package substrate. The dielectric mass can be formed, for example, by molding or by application of a conformal layer. | 2012-05-17 |
20120119381 | SEMICONDUCTOR DEVICE WITH VERTICAL CURRENT FLOW AND LOW SUBSTRATE RESISTANCE AND MANUFACTURING PROCESS THEREOF - A semiconductor device with vertical current flow includes a body having a substrate made of semiconductor material. At least one electrical contact on a first face of the body. A metallization structure is formed on a second face of the body, opposite to the first face. The metallization structure is provided with metal vias, which project from the second face within the substrate so as to form a high-conductivity path in parallel with portions of said substrate. | 2012-05-17 |
20120119382 | SEMICONDUCTOR DEVICE WITH VERTICAL CURRENT FLOW AND LOW SUBSTRATE RESISTANCE AND MANUFACTURING PROCESS THEREOF - A semiconductor device with vertical current flow includes a body having a substrate made of semiconductor material. At least one electrical contact on a first face of the body. A metallization structure is formed on a second face of the body, opposite to the first face. The metallization structure is provided with metal vias, which project from the second face within the substrate so as to form a high-conductivity path in parallel with portions of said substrate. | 2012-05-17 |
20120119383 | STACKED INTEGRATED CIRCUIT PACKAGE FABRICATION METHODS THAT USE VIAS FORMED AND FILLED AFTER STACKING, AND RELATED STACKED INTEGRATED CIRCUIT PACKAGE STRUCTURES - Microelectronic packages are fabricated by stacking integrated circuits upon one another. Each integrated circuit includes a semiconductor layer having microelectronic devices and a wiring layer on the semiconductor layer having wiring that selectively interconnects the microelectronic devices. After stacking, a via is formed that extends through at least two of the integrated circuits that are stacked upon one another. Then, the via is filled with conductive material that selectively electrically contacts the wiring. Related microelectronic packages are also described. | 2012-05-17 |
20120119384 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In a semiconductor device having a through-hole electrode and a manufacturing method thereof, a dummy groove hole portion for forming insulating portion insulating wirings from each other is provided, to surround a rewiring layer including a through-hole electrode on a back surface of a semiconductor substrate. This allows the wirings to be insulated from each other just by removing the metal layer existing at a bottom portion of the dummy groove hole portion. Thus, a reduction in the processing time can be realized. | 2012-05-17 |
20120119385 | Electrical Connector Between Die Pad and Z-Interconnect for Stacked Die Assemblies - Methods for forming connectors on die pads at a wafer level of processing include forming spots of a curable electrically conductive material over die pads and extending to or over the interconnect die edge; curing the conductive material; and in a wafer cutting procedure thereafter severing the spots. Also, die pad to z-interconnect connectors formed by the methods, and shaped and dimensioned accordingly. Also, stacked die assemblies and stacked die packages containing die prepared according to the methods and having die pad to z-interconnect connectors formed by the methods and shaped and dimensioned accordingly. | 2012-05-17 |
20120119386 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a semiconductor substrate which includes a first chip area and a second chip area. An insulation film is formed over the substrate. An electrical circuit is formed in the first chip area and is electrically independent from any component in another chip area. The electrical circuit includes an electrical element and an interconnect on the substrate and in the insulation film. Boundary patterns are formed in the insulation film between the first and second chip areas, are electrically independent from the electrical circuit, and have a gap therebetween. One of the boundary patterns surrounds the first chip area. | 2012-05-17 |
20120119387 | SEMICONDUCTOR PACKAGE WITH BONDING WIRES OF REDUCED LOOP INDUCTANCE - A semiconductor package includes a semiconductor device including a plurality of signal pads and a plurality of auxiliary pads which are alternatively arranged in a predetermined direction, and a package board including a plurality of signal bond fingers, a plurality of first power supply voltage bond fingers, and a plurality of second power supply voltage bond fingers. The signal pads are connected respectively to the signal bond fingers by first wires. The first power supply voltage bond fingers and the second power supply voltage bond fingers are connected respectively to the auxiliary pads by second wires. The first wires are disposed between those of the second wires which are connected to the first power supply voltage bond fingers and those of the second wires which are connected to the second power supply voltage bond fingers. | 2012-05-17 |
20120119388 | Semiconductor Device and Method of Forming Interposer Frame Electrically Connected to Embedded Semiconductor Die - A semiconductor device has an interposer frame mounted over a carrier. A semiconductor die has an active surface and bumps formed over the active surface. The semiconductor die can be mounted within a die opening of the interposer frame or over the interposer frame. Stacked semiconductor die can also be mounted within the die opening of the interposer frame or over the interposer frame. Bond wires or bumps are formed between the semiconductor die and interposer frame. An encapsulant is deposited over the interposer frame and semiconductor die. An interconnect structure is formed over the encapsulant and bumps of the first semiconductor die. An electronic component, such as a discrete passive device, semiconductor die, or stacked semiconductor die, is mounted over the semiconductor die and interposer frame. The electronic component has an I/O count less than an I/O count of the semiconductor die. | 2012-05-17 |
20120119389 | Method for Fabricating a Semiconductor Chip and Semiconductor Chip - A method includes structuring a semiconductor substrate to produce a number semiconductor chips. Each of the semiconductor chips includes a first main face and a number of side faces. An indentation is formed at a transition between the first main face and the side faces. | 2012-05-17 |
20120119390 | SEMICONDUCTOR STRUCTURE AND A METHOD OF MANUFACTURING A SEMICONDUCTOR STRUCTURE - According to one embodiment of the present invention, a semiconductor structure is provided. The semiconductor structure includes a first support structure, a plurality of chips formed on the first support structure and a reinforcing structure formed on the first support structure, the reinforcing structure including an outer surrounding element which surrounds the plurality of chips and extends from a surface of the first support structure to a height higher than each of the plurality of chips. A method of manufacturing a semiconductor structure is also provided. | 2012-05-17 |
20120119391 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package includes a support member having a concave portion formed in one surface thereof. A semiconductor chip is accommodated in the concave portion so that a circuit formation surface of the semiconductor chip is exposed on a side of the one surface of the support member. A wiring structure including a wiring layer electrically connected to the semiconductor chip is formed on the circuit formation surface of the semiconductor chip and the one surface of the support member. A portion of the support member including the one surface is made of silicon or borosilicate glass. | 2012-05-17 |
20120119392 | LEAD-FREE HIGH TEMPERATURE COMPOUND - A simple method is provided for firmly-bonded connection of an electronic component to a substrate, which dispenses with the use of lead-containing paste solders and leads to a contact layer featuring sufficiently high resistance to heat fatigue in an environment characterized by incessant periodical temperature variations, and featuring high thermal and electrical conductivity. The method for firmly-bonded connection of an electronic component to a substrate includes the steps of: (a) providing an electronic component having a first surface to be connected and a substrate having a second surface to be connected; (b) applying a paste solder to at least one of the surfaces to be connected; (c) arranging the electronic component and the substrate such that the first electronic component surface to be connected and the second substrate surface to be connected contact each other through the paste solder; and (d) soldering the arrangement from (c) in order to generate a firmly-bonded connection between the electronic component and the substrate, wherein the paste solder contains (i) 10-30% by weight copper particles, (ii) 60-80% by weight particles of at least one substance selected from the group consisting of tin and tin-copper alloys, and (iii) 3-30% by weight solder flux, wherein the mean particle diameter of the particles (i) and of the particles (ii) is no more than 15 μm, and wherein the thickness of the applied layer of paste solder is at least 20 μm. | 2012-05-17 |
20120119393 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FLEXIBLE SUBSTRATE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a package substrate having a foldable segment, a base segment, and a stack segment; connecting a base substrate connector directly on the base segment; connecting a stack substrate connector directly on the stack segment; mounting a base integrated circuit over the base segment with the base substrate connector outside a perimeter of the base integrated circuit; and folding the package substrate with the stack segment over the base segment and the stack substrate connector directly on the base substrate connector. | 2012-05-17 |
20120119394 | AUTO CHOKE APPARATUS - In an auto choke apparatus, a throttle valve and a choke valve are provided in a carburetor. A bimetal is provided near a muffler to bring the choke valve back in an opening direction after warm-up is completed. A bimetal lever has amounting hole to which one end of a choke rod is secured. A choke lever has amounting hole having a long hole shape to which the other end of the choke rod is secured. By forming the mounting hole of the choke lever in a long hole shape, the choke lever can be moved with the bimetal lever being stopped so that a throttle lever and the choke lever can be caused to work together without being restricted by the bimetal. | 2012-05-17 |
20120119395 | METHOD AND DEVICE FOR PREVENTING CORROSION ON A GAS INLET NOZZLE DURING NITRIC ACID CONDENSATION - By a method and a device for preventing corrosion on and in the region of a gas inlet nozzle during nitric acid condensation, contact of the condensing gas with the nozzle and with the surroundings of the nozzle are supposed to be minimized. This is achieved in that the gas inlet nozzle has a sleeve on the inside in the transition region to the interior of the condenser, by which sleeve a gas inlet orifice in the form of an annular gap is formed, whereby the annular space is provided with at least one feed opening for secondary air, so that an enveloping flow of secondary air is produced around the entering NO gas. | 2012-05-17 |
20120119396 | DESALINATION SYSTEM AND METHOD - A water desalination system including at least one pair of evaporators, said pair including a high pressure and a low pressure evaporator, each for evaporating saline water to produce water vapour; at least three adsorption beds in selective vapour communication with each evaporator, said adsorption beds arranged to reversibly adsorb the water vapour from the corresponding evaporator; said adsorption beds in selective vapour communication with a condenser, and in heat transfer communication with a heat source for selectively desorbing the adsorbed water vapour; said condenser arranged to condense the water vapour to desalinated water; wherein said system is arranged to sequentially connect, for a pre-determined period, each evaporator to a corresponding adsorption bed, and the heat source to the third bed. | 2012-05-17 |
20120119397 | METHOD FOR PRODUCING DISPERSION LIQUID CONTAINING PEST CONTROLLING COMPOSITION AND METHOD FOR PRODUCING MICROCAPSULE - Provided is a method for continuously producing a dispersion liquid containing a pest controlling composition. This method includes steps of: dispersing a suspension and a dispersion medium in a first dispersion tank by stirring the suspension and the dispersion medium in the first dispersion tank while continuously supplying the suspension and the dispersion medium into the first dispersion tank, the suspension being formed by suspending a solid pest controlling composition in a water-immiscible organic solvent and the dispersion medium being formed from water or a water solvent containing an alcohol; and stirring a first dispersion liquid in a second dispersion tank while continuously supplying into the second dispersion tank the first dispersion liquid discharged continuously from the first dispersion tank, wherein the stirring of the first dispersion liquid is continued until a dispersion state of the first dispersion liquid becomes stable. | 2012-05-17 |
20120119398 | MAKING CARBON ARTICLES FROM COATED PARTICLES - Methods and compositions relate to manufacturing a carbonaceous article from particles that have pitch coatings. Heating the particles that are formed into a shape of the article carbonizes the pitch coatings. The particles interconnect with one another due to being formed into the shape of the article and are fixed together where the pitch coatings along adjoined ones of the particles contact one another and are carbonized to create the article. | 2012-05-17 |
20120119399 | TRANSPORT CONTAINER - A transport container for use in a device for producing a three-dimensional object of selective solidification of a build-up material deposited in layers, in which the device has a process chamber closed during operation, where the three-dimensional object is produced in layers. The transport container has a container, in which a height-adjustable platform is arranged, on which the three-dimensional object is produced in layers. The process chamber has first and second sections in which the second section can be separated from the first section and operated in a separate state independently from the device and also can be connected to the first section to produce an operating state of the device. | 2012-05-17 |
20120119400 | VALVE GATE SYSTEM - A valve gate assembly comprises a piston that is actuable between a forward position and a rear position and has a piston stop surface and a forward pressure surface. A cylinder has a cylinder stop surface that is disposed to contact the piston stop surface when the piston is in the forward position. The cylinder stop surface is radially outward of at least a portion of the forward pressure surface and a shutoff pin is substantially aligned with the axis. | 2012-05-17 |
20120119401 | Production of carbonaceous porous bodies for use in filtration systems - A porous, carbonaceous body for use in respiratory protection is produced by making a slurry of carbonaceous powder such as carbon black, a polymeric binder such as polyvinyl alcohol and a solvent, drying and grinding the slurry to yield a ground powder, compacting the powder and heat treating the resulting green body. Alternatively, the slurry is only partially dried to produce a paste, which is compacted and then heat treated. A reactive monomer (plasticizer of cross-linking agent) can be added to the polymeric binder. | 2012-05-17 |
20120119402 | COMPOSITE COMPONENT COMPRISING A POLYMER PHASE AND A FOAMED PHASE, AND PROCESSES FOR PRODUCING THE SAME - The present invention relates to a composite component comprising an unfoamed polymer phase and a foamed phase, and to a process for producing the same. | 2012-05-17 |