22nd week of 2015 patent applcation highlights part 43 |
Patent application number | Title | Published |
20150147803 | Coatings of Semiconductor Quantum Dots for Improved Visibility of Electrodes and Pipettes - A glass pipette such as an electrode for electrophysiological recording is coated with quantum dots. This greatly aids the ability to observe the glass pipette, particular in tissue as the quantum dots provide an excellent performance under two-photon illumination used to visualize objects at depths of hundreds of microns. | 2015-05-28 |
20150147804 | BIOCHEMICAL ANALYSIS CARTRIDGE HAVING IMPROVED OPERABILITY - The present invention relates to a biochemical analysis cartridge having improved operability. More particularly, the present invention provides a biochemical analysis cartridge including an insertion-type sample cartridge and a reaction cartridge receiving the insertion-type sample cartridge, in which,as the sample cartridge is inserted into the reaction cartridge,a reaction solution chamber moves toward a broken part of a covertape so as to automatically supply the reaction solution stored in the chamber. The biochemical analysis cartridge having improved operability according to the present invention can induce the mixing between a sample and a reaction solution by simply inserting them into the reaction cartridge and a reaction thereafter, thereby minimizing the process of a measurer to intervene in the assay, and subsequently improving user convenience and operability. | 2015-05-28 |
20150147805 | Vectors, Host Cells, and Methods of Production and Uses - Antibody expression vectors and plasmids can incorporate various antibody gene portions for transcription of the antibody DNA and expression of the antibody in an appropriate host cell. The expression vectors and plasmids have restriction enzyme sites that facilitate ligation of antibody-encoding DNA into the vectors. The vectors incorporate enhancer and promoter sequences that can be varied to interact with transcription factors in the host cell and thereby control transcription of the antibody-encoding DNA. A kit can incorporate these vectors and plasmids. | 2015-05-28 |
20150147806 | METHOD FOR PREPARING TRANSFERRABLE NANOSCALE TRANSFERRABLE MEMBRANE AND USE THEREOF - Disclosed is a method for preparing a transferable membrane having a nanometer scale dimension in thickness and pore size by non-solvent vapor-induced phase separation process, comprising spin-casting a polymer solution in a closed humid chamber and controlling the relative humidity (RH) of the chamber using at least one supersaturated salts solution whereby the density of the pores are controlled. Also provided is a TNT membrane prepared by the present method and its use. The present membrane can be advantageously used as co-culture platform facilitating versatile and controllable cell co-culture assays and further allowing the quantitative analysis of paracrine communications between cells for example between cancer cells and different types of stromal cells by providing an in vivo-like environment, which can offer more in-vivo-like results to identify key signaling molecules for therapeutic targets of a disease. | 2015-05-28 |
20150147807 | HIGH-THROUGHPUT IMAGE-BASED CHEMICAL SCREENING IN ZEBRAFISH BLASTOMERE CELL CULTURE - Disclosed are methods of inducing differentiation of stem into myogenic cells without gene manipulation and for inducing proliferation of satellite cells. The cells can be used as a source of cells for transplantation in a subject in need thereof. Also disclosed is a screening assay for screening test compounds using blastomere cultures. | 2015-05-28 |
20150147808 | Use of a warmer for promoting a biological reaction - The present invention relates to the use of warmers, or autonomous heat packs, for heating and maintaining a solution on at a suitable temperature, for the period of time required to accomplish a chemical, biochemical or biological reaction, in particular in molecular biology or cell biology applications. Biology kits containing warmers are also part of this invention. | 2015-05-28 |
20150147809 | CELL SEEDING DEVICE AND METHOD - Described is a device comprising an anchor, a tray including a well adapted to receive the anchor, and a cover adapted to engage the tray and cover the well. The device may be used to form a membrane-cell matrix having a substantially uniform distribution of the cells on the membrane in at least two dimensions. | 2015-05-28 |
20150147810 | ULTRATHIN PARYLENE-C SEMIPERMEABLE MEMBRANES FOR BIOMEDICAL APPLICATIONS - Thin parylene C membranes having smooth front sides and ultrathin regions (e.g., 0.01 μm to 5 μm thick) interspersed with thicker regions are disclosed. The back sides of the membranes can be rough compared with the smooth front sides. The membranes can be used in vitro to grow monolayers of cells in a laboratory or in vivo as surgically implantable growth layers, such as to replace the Bruch's membrane in the eye. The thin regions of parylene are semipermeable to allow for proteins in serum to pass through, and the thick regions give mechanical support for handling by a surgeon. The smooth front side allows for monolayer cell growth, and the rough back side helps prevents cells from attaching there. | 2015-05-28 |
20150147811 | Filtration of Cell Culture Supernatants - The invention relates to a method for separating off a liquid supernatant from cells, comprising the steps: providing a mixture of the cells with a liquid, charging a first filter housing with the mixture, wherein in the filter housing a filter having a pore size of between 4 μm and 50 μm is provided on a flat base surface pierced in a sieve manner and the walls of the filter housing are connected so as to seal with the flat base surface that is pierced in a sieve manner, applying a differential pressure of at least 0.5 bar on the mixture, as a result of which the liquid portion of the mixture is forced through the filter and a filter cake containing cells remains in the filter housing, and removal of the filtered liquid. | 2015-05-28 |
20150147812 | CARRIER FOR GENE INTRODUCTION USE, GENE INTRODUCTION AGENT, METHODS FOR PRODUCING SAID CARRIER AND SAID GENE INTRODUCTION AGENT, AND METHOD FOR INTRODUCING GENE INTO CELL - The present invention provides; a novel gene introduction method which enables a gene to be introduced more safely and more freely, particularly a method for introducing a gene into a specified site in the brain safely and freely; a carrier for gene introduction use, which comprises a nano-particle and a substance capable of binding to a vector for gene introduction and has functional groups involved in the induction of phagocytosis by cells, wherein the substance capable of binding to a vector for gene introduction can bind to the surface of the nano-particle through some of the functional groups and another some of the functional groups remain unbound to the substance capable of binding to a vector for gene introduction; and a gene introduction agent, in which a vector for gene introduction is bound to the substance capable of binding to a vector for gene introduction in the carrier for gene introduction. | 2015-05-28 |
20150147813 | METHODS AND MATERIALS FOR INCREASING POTENCY OF CELLS - Disclosed herein are methods and materials for producing a more developmentally potent cell from a less developmentally potent cell. Specifically exemplified herein are methods that comprise introducing an expressible dedifferentiating polynucleotide sequence into a less developmentally potent cell, wherein the transfected less developmentally potent cell becomes a more developmentally potent cell capable of differentiating to a less developmentally potent cell of its lineage of origin or a different lineage. | 2015-05-28 |
20150147814 | METHOD AND SYSTEM FOR ANALYZING A LIQUID SAMPLE CONTAINING PARTICLES OF SOLID MATTER AND THE USE OF SUCH A METHOD AND SYSTEM - The invention relates to a method and system for monitoring of particles properties in a stream and the use of such method and system. In particular, the invention concerns sampling of liquids like aqueous suspensions or filtrates that contain solid matter in forest industry, oil and mining industry, as well as in and water treatment, desalination or water reuse processes, and in subsequent measurement of the samples. A sample from a stream of liquid is dyed to stain particles contained in the sample, which is conducted to a first flow chamber having means for causing said sample to be divided into particle populations according to their size or mass. A liquid flow is applied through the first flow chamber to cause at least one particle population to flow into a second flow chamber. The particle populations are measured to produce at least one measurement signal representative of the amount and/or properties of the particles, and processing extract key variables of each particle population and presenting them as an analysis of particle populations or the whole sample in terms of a count and size of particles and/or their hydrophobicity. | 2015-05-28 |
20150147815 | CELL FREE DNA DIAGNOSTIC TESTING STANDARDS - Embodiments of the invention include methods and compositions for producing proficiency testing standards for noninvasive prenatal genetic diagnostics and for the detection and monitoring of cancer. The compositions can comprise a plurality of different nucleosomal DNA fragments derived from either primary cells or cell lines. The amount of the different nucleosomal DNA fragments can be varied so as to simulate naturally occurring cell free DNA samples obtained from the blood of the pregnant woman or naturally occurring cell free DNA samples obtained from the blood of cancer patients. | 2015-05-28 |
20150147816 | METHOD OF EVALUATING RESIN - Provided is a method of evaluating a resin capable of quantitatively evaluating a deterioration degree of the resin with high accuracy and ease. The method includes evaluating the resin based on a shift of a characteristic peak representing a deterioration degree of the resin, the peak being observed in thermal analysis of the resin by a temperature increase, to lower temperatures. | 2015-05-28 |
20150147817 | PC-O 44:4 - A BIOMARKER FOR VISCERAL ADIPOSITY - The present invention generally relates to the field of biomarkers. In particular, the present invention relates to biomarkers such as PC-O 44:4 that can be used, for example for detecting and/or quantifying visceral adiposity and/or changes in visceral adiposity. This biomarker may also be used to diagnosing the effect of a change in lifestyle on visceral adiposity in a subject. | 2015-05-28 |
20150147818 | SENSOR FOR DETECTING EXPLOSIVE, AND PREPARATION METHOD THEREOF - The present invention relates to a sensor capable of detecting an aromatic nitro compound explosive, and a preparation method thereof, and more specifically, to a nanosensor system, and a detection method using the same, wherein a quantum dot-based sensor for detecting an aromatic nitro compound explosive can conveniently detect an aromatic nitro compound explosive with high sensitivity on the basis of a change in energy transfer between quantum dots. The method for detecting an explosive of the present invention makes an explosive come in contact with a quantum dot thin film to which an explosive can combine, and measures a change in fluorescence wavelength, thereby sensing an explosive. According to the present invention, the method for detecting an explosive on the basis of quantum dots uses a change in fluorescence wavelength which is unlike a known detection method using the change in quantum dot fluorescence intensity, and thus is not sensitive to a change in surroundings, can carry out rapid detection, and can detect even a low concentration of explosives with high sensitivity. Therefore, the present invention is expected to be extensively commercialized. | 2015-05-28 |
20150147819 | INTERFACING APPARATUS BETWEEN A LABORATORY AUTOMATION SYSTEM AND A PLATFORM FOR HANDLING CONSUMABLES AND LIQUIDS IN THE FIELD OF MOLECULAR BIOLOGY - Apparatus for automatically filling wells of plates with biological material from a laboratory automation system for conveying biological samples or reactants contained in test tubes, and automatically routing said plates towards processing modules of said biological material. Said apparatus contains a platform interposed between said laboratory automation system and a handling system of consumable products, which includes a horizontal crosspiece whereon a first robot and a second robot are sliding mounted, the first robot being provided with gripping means of pipettes adapted to collect and release the biological material or the reactant, and a second robot being provided with gripping means of consumable products. | 2015-05-28 |
20150147820 | SYSTEM FOR MANAGING INVENTORY OF BULK LIQUIDS - A system for managing bulk liquids for an automated clinical analyzer. The system comprises (a) at least one local reservoir for storing a bulk liquid for impending use, (b) at least one container for holding a bulk liquid before the liquid is transferred to a local reservoir, and (c) a controller for monitoring the level of a bulk liquid in a local reservoir. The local reservoir for storing a bulk liquid for impending use can be a trough. The use of troughs for storing a reagent, a diluent, or some other treating agent for impending use enables an aspirating/dispensing device having a plurality of pipettes to aspirate and dispense the reagent,diluent, or other treating agent at a high rate of throughput. The controller can monitor the level of a liquid in (a) a local reservoir for storing a bulk liquid for imminent use and the level of liquid in a (b) container for holding a bulk liquid before the liquid is transferred to a local reservoir. In the laboratory automation system described herein, the container for holding a bulk liquid before the liquid is transferred to a local reservoir can be a bottle. Other desirable features in the system include, but are not limited to, pump(s), valves, liquid level sensors. | 2015-05-28 |
20150147821 | SYSTEMS AND METHODS FOR DETECTING MOLECULAR INTERACTIONS USING MAGNETIC BEADS - Systems and methods are provided for detecting or measuring binding affinity between different compositions. The methods include contacting one or more magnetic beads having a surface including a first composition with a substrate having a surface including a second composition; applying a rotating magnetic field to the one or more magnetic beads effective to cause the one or more magnetic beads to move across the surface of the substrate; measuring the movement of the one or more magnetic beads across the substrate surface to determine a translational velocity; and determining a binding affinity between the first and second compositions from the translational velocity. | 2015-05-28 |
20150147822 | ASSAYS - The invention provides an assay for assessing the conformational stability of a membrane protein, comprising: (a) providing a sample comprising a first population and a second population of a membrane protein; wherein the membrane protein in the first population is labelled with a donor label and the membrane protein in the second population is labelled with an acceptor label, or the membrane protein in the first population is labelled with an acceptor label and the membrane protein in the second population is labelled with a donor label, (b) exposing the first and second populations of the membrane protein to a stability modulating agent and/or condition, (c) and assessing aggregation between membrane proteins of the first and second populations by activating the donor label to permit a distance-dependent interaction with the acceptor label, which interaction produces a detectable signal. | 2015-05-28 |
20150147823 | METHODS AND COMPOSITIONS FOR PERSONALIZED MEDICINE BY POINT-OF-CARE DEVICES FOR BRAIN NATRIURETIC PEPTIDE - Methods, devices, reagent, systems and kits for the detection, diagnosis of ovarian cancer as well as for the monitoring of ovarian cancer progression and for monitoring the progress of ovarian cancer treatments using BNP as a biomarker. | 2015-05-28 |
20150147824 | SILICON PRECURSORS FOR LOW TEMPERATURE ALD OF SILICON-BASED THIN-FILMS - A silicon precursor composition is described, including a silylene compound selected from among: silylene compounds of the formula: wherein each of R and R | 2015-05-28 |
20150147825 | MRAM Device and Fabrication Method Thereof - According to an embodiment, a magnetoresistive random access memory (MRAM) device comprises a bottom electrode, a stack, a dielectric material, a dielectric layer, and a conductive material. The bottom electrode is over a substrate, and the stack is over the bottom electrode. The stack comprises a magnetic tunnel junction (MTJ) and a top electrode. The dielectric material is along a sidewall of the stack, and the dielectric material has a height greater than a thickness of the MTJ and less than a stack height. The dielectric layer is over the stack and the dielectric material. The conductive material extends through the dielectric layer to the top electrode of the stack. | 2015-05-28 |
20150147826 | Integrated System, Integrated System Operation Method And Film Treatment Method - An integrated system operation method is disclosed that includes the following steps: the film of a substrate is measured by a metrology apparatus to obtain a film information. The substrate is moved from the metrology apparatus to a process apparatus adjacent to the transfer apparatus. The film information is sent to the process apparatus. A film treatment is applied to the substrate in accordance with the film information. | 2015-05-28 |
20150147827 | Substrate Tuning System and Method Using Optical Projection - Techniques herein include systems and methods that provide a spatially-controlled or pixel-based projection of light onto a substrate to tune various substrate properties. A given pixel-based image projected on to a substrate surface can be based on a substrate signature. The substrate signature can spatially represent non-uniformities across the surface of the substrate. Such non-uniformities can include energy, heat, critical dimensions, photolithographic exposure dosages, etc. Such pixel-based light projection can be used to tune various properties of substrates, including tuning of critical dimensions, heating uniformity, evaporative cooling, and generation of photo-sensitive agents. Combining such pixel-based light projection with photolithographic patterning processes and/or heating processes improves processing uniformity and decreases defectivity. Embodiments can include using a digital light processing (DLP) chip, grating light valve (GLV), or other grid-based micro projection technology. | 2015-05-28 |
20150147828 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a p-side electrode, an n-side electrode, a fluorescent material layer and a scattering layer. The semiconductor layer has a first surface and a second surface on an opposite side to the first surface and includes a light emitting layer. The p-side electrode and the n-side electrode are provided on the semiconductor layer on a side of the second surface. The fluorescent material layer is provided on a side of the first surface and includes a plurality of fluorescent materials and a first bonding material. The first bonding material integrates the fluorescent materials. The scattering layer is provided on the fluorescent material layer and includes scattering materials and a second bonding material. The scattering materials are configured to scatter radiated light of the light emitting layer. The second bonding material integrates the scattering materials. | 2015-05-28 |
20150147829 | Limiting Adjustment of Polishing Rates During Substrate Polishing - A method of controlling polishing includes polishing a region of a substrate at a first polishing rate, measuring a sequence characterizing values for the region of the substrate during polishing with an in-situ monitoring system, determining a polishing rate adjustment for each of a plurality of adjustment times prior to a polishing endpoint time, and adjusting a polishing parameter to polish the substrate at a second polishing rate. The time period is greater than a period between the adjustment times and the projected time is before the polishing endpoint time. The second polishing rate is the first polishing rate as adjusted by the polishing rate adjustment. | 2015-05-28 |
20150147830 | DETECTION OF SUBSTRATE DEFECTS BY TRACKING PROCESSING PARAMETERS - A method comprising processing a substrate exposed to a plasma in a processing chamber, obtaining a metric indicative of a parameter of the plasma during the processing of the substrate, and determining a defect in the substrate by comparing the metric to a predefined criteria. | 2015-05-28 |
20150147831 | METHOD OF MANUFACTURING ORGANIC LIGHT EMITTING DISPLAY DEVICE - Provided is a method of manufacturing an organic light emitting display device. The method includes: providing a first substrate including: a display portion, and a non-display portion, forming a thin film transistor (TFT) and an organic light emitting diode (OLED) in the display portion of the first substrate, providing a pad portion including: at least one pad contact portion at the non-display portion and electrically connected to the TFT, and a pad insulating portion between adjacent pad contact portions, providing an anti-moisture insulation layer entirely covering the first substrate, adhering an encapsulating substrate onto the anti-moisture insulation portion in correspondence with the display portion, and removing the anti-moisture insulation layer, at the pad contact portion, using a laser. | 2015-05-28 |
20150147832 | METHOD FOR PRODUCING LIGHT-EMITTING DIODE - A method for producing a light-emitting diode is provided, including the following steps. First, a carrier is provided, wherein the carrier comprises a die bonding surface. Then, a die bonding adhesive layer is formed on the die bonding surface, wherein the die bonding adhesive layer has a photoresist property. Next, at least one lighting chip is disposed on the die bonding adhesive layer, and an uncovered portion of the die bonding adhesive layer is not covered by the lighting chip. Finally, the uncovered portion of the die bonding adhesive layer is removed. | 2015-05-28 |
20150147833 | METHOD FOR MANUFACTURING ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE - A method of manufacturing an OLED device is discussed. The method can include forming a gate electrode on a substrate; forming a gate insulation film on the substrate provided with the gate electrode; forming a channel layer, a source electrode and a drain electrode on the substrate provided with the gate insulation film; forming an organic light emitting diode which includes a first electrode connected to the drain electrode, an organic emission layer formed on the first electrode, and a second electrode formed on the organic emission layer; forming a passivation layer, which has a hydrogen content below 10%, on the substrate provided with the organic light emitting diode using an organic silicon compound; and forming a sealing layer on the substrate provided with the passivation layer. | 2015-05-28 |
20150147834 | NOVEL SEMICONDUCTOR PACKAGE WITH THROUGH SILICON VIAS - The substrate with through silicon plugs (or vias) described above removes the need for conductive bumps. The process flow is very simple and cost efficient. The structures described combines the separate TSV, redistribution layer, and conductive bump structures into a single structure. By combining the separate structures, a low resistance electrical connection with high heat dissipation capability is created. In addition, the substrate with through silicon plugs (or vias, or trenches) also allows multiple chips to be packaged together. A through silicon trench can surround the one or more chips to provide protection against copper diffusing to neighboring devices during manufacturing. In addition, multiple chips with similar or different functions can be integrated on the TSV substrate. Through silicon plugs with different patterns can be used under a semiconductor chip(s) to improve heat dissipation and to resolve manufacturing concerns. | 2015-05-28 |
20150147835 | SEMICONDUCTOR LIGHT EMITTING DEVICE - There is provided a semiconductor light emitting device including a conductive substrate, a first electrode layer, an insulating layer, a second electrode layer, a second semiconductor layer, an active layer, and a first semiconductor layer that are sequentially stacked. The contact area between the first electrode layer and the first semiconductor layer is 3% to 13% of the total area of the semiconductor light emitting device, and thus high luminous efficiency is achieved. | 2015-05-28 |
20150147836 | COMPOSITION FOR CLEANING FLAT PANEL DISPLAY AND METHOD FOR MANUFACTURING DISPLAY DEVICE USING THE SAME - The disclosure provides a cleaning agent composition for a flat panel display device, including: polyaminocarboxylic acid; alkali base; a nonionic surfactant; and a fluoride component. The cleaning agent composition for the flat panel display device can effectively remove metal oxides and organic contaminants on the substrate without impairing a transparent conductive layer. | 2015-05-28 |
20150147837 | METHOD OF MANUFACTURING DISPLAY APPARATUS - A method of manufacturing a display device including providing a substrate, forming a semiconductor layer on the substrate, forming a first insulating layer on the semiconductor layer, forming a metal layer on the first insulating layer, forming a second insulating layer on the metal layer, forming an etching buffer layer on the second insulating layer, forming a photosensitive film pattern on the etching buffer layer, and etching the etching buffer layer and the first and second insulating layers to expose the semiconductor layer. | 2015-05-28 |
20150147838 | MANUFACTURING METHOD OF DISPLAY DEVICE - A manufacturing method of a display device of the invention includes a step of forming an organic layer in correspondence with respective pixels on a substrate having a display area and a non-display area, the step of forming the organic layer includes a step of depositing a material of the organic layer using a mask having a frame-like frame and a mask foil fixed to the frame, the mask foil has openings provided in an area corresponding to the display area and dummy holes provided along an outer periphery of the area corresponding to the display area in an area corresponding to the non-display area, and an area of a plan view shape of the dummy hole adjacent to a midpoint of a side of the outer periphery is larger than an area of a plan view shape of the dummy hole adjacent to a corner of the outer periphery. | 2015-05-28 |
20150147839 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device may include: forming a metal layer structure over a semiconductor workpiece; forming a first layer over the metal layer structure, the first layer including a first material; forming at least one opening in the first layer and the metal layer structure; depositing a second layer to fill the at least one opening and at least partially cover a surface of the first layer facing away from the metal layer structure, the second layer including a second material that is different from the first material; removing the second layer from at least the surface of the first layer facing away from the metal layer structure; and removing the first layer. | 2015-05-28 |
20150147840 | Synthesis Method of Organometallic Complex, Synthesis Method of Pyrazine Derivative, 5,6-Diaryl-2-Pyrazyl Triflate, Light-Emitting Element, Light-Emitting Device, Electronic Device, and Lighting Device - Provided is a 5,6-diaryl-2-pyrazyl triflate, its synthetic method, and a method for synthesizing an organometallic complex having a triarylpyrazine ligand from the 5,6-diaryl-2-pyrazyl triflate. The triflate is readily obtained from the corresponding 5,6-diarylpyrazin-2-ol, and the palladium-catalyzed coupling of the 5,6-diaryl-2-pyrazyl triflate with an arylboronic acid derivative leads to a high yield of a triarylpyrazine derivative having high purity. The use of the triarylpyrazine derivative in the reaction with a metal compound such as a metal chloride results in an ortho-metallated organometallic complex with high purity. The high purity of the organometallic complex contributes to the extremely high durability of a light-emitting element. | 2015-05-28 |
20150147841 | METHOD TO RELEASE DIAPHRAGM IN MEMS DEVICE - A method for releasing a diaphragm of a micro-electro-mechanical systems (MEMS) device at a stage of semi-finished product. The method includes pre-wetting the MEMS device in a pre-wetting solution to at least pre-wet a sidewall surface of a cavity of the MEMS device. Then, a wetting process after the step of pre-wetting the MEMS device is performed to etch a dielectric material of a dielectric layer for holding the diaphragm, wherein a sensing portion of the diaphragm is released from the dielectric layer. | 2015-05-28 |
20150147842 | ARRAYS OF FILLED NANOSTRUCTURES WITH PROTRUDING SEGMENTS AND METHODS THEREOF - A structure and method for at least one array of nanowires partially embedded in a matrix includes nanowires and one or more fill materials located between the nanowires. Each of the nanowires including a first segment associated with a first end, a second segment associated with a second end, and a third segment between the first segment and the second segment. The nanowires are substantially parallel to each other and are fixed in position relative to each other by the one or more fill materials. The third segment is substantially surrounded by the one or more fill materials. The first segment protrudes from the one or more fill materials. | 2015-05-28 |
20150147843 | METHOD OF MANUFACTURING PHOTOELECTRIC CONVERSION APPARATUS - A method of manufacturing a photoelectric conversion apparatus which includes a pixel circuit section having a well where a photoelectric conversion element and an amplification element configured to generate a signal based on an amount of charge generated in the photoelectric conversion element are arranged, and a peripheral circuit section having a MOS transistor. The method includes forming a dielectric film for covering the photoelectric conversion element, the amplification element, and a gate electrode of the MOS transistor and forming, by etching the dielectric film, a side spacer by remaining a portion of the dielectric film on a side surface of the gate electrode while protecting by a resist, wherein an opening is formed in the dielectric film of the pixel circuit section with the etching, and a contact for defining a potential of the well is formed through the opening. | 2015-05-28 |
20150147844 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes supplying a first source gas including a germanium (Ge) precursor onto a semiconductor substrate for a first time period, and periodically interrupting the supplying of the first source gas for the first time period to form Ge elements on the semiconductor substrate. | 2015-05-28 |
20150147845 | DUAL SIDED EMBEDDED DIE AND FABRICATION OF SAME BACKGROUND - Embodiments of the invention provide a method for forming a dual sided embedded die system. The method begins with starting material including a top surface and a bottom surface, a plurality of vias, a plurality of plated metal posts, die pads, and stiffeners. The surface are planarized to expose the included metal which is than selectively etching from die attach pad DAP areas to form cavities. Create a stiffener by using photo resist patterning and plating. Apply tacky tape. Attach a die. Laminate and grind. Remove tacky tape. Form redistribution layers RDLs and a solder mask. Mounting Surface Mount Devices. | 2015-05-28 |
20150147846 | NO FLOW UNDERFILL OR WAFER LEVEL UNDERFILL AND SOLDER COLUMNS - A preassembly semiconductor device comprises chip soldering structures on a semiconductor chip and substrate soldering structures on a substrate corresponding to the chip soldering structures. The substrate soldering structures extend toward the chip soldering structures for forming solder connections with the chip soldering structures. The chip and the substrate are in preassembly positions relative to one another. The height of the substrate soldering structures is greater than the height of the chip soldering structures. A pre-applied underfill is contiguous with the substrate and is sufficiently thick so as to extend substantially no further than the full height of the substrate soldering structures. In another embodiment the height of the chip soldering structures is greater than the height of the substrate soldering structures and the pre-applied underfill is contiguous with the semiconductor chip and sufficiently thick so as to extend substantially no further than the full height of the chip soldering structures. A process comprises manufacturing semiconductor assemblies from these devices by soldering the chip and the substrate to one another | 2015-05-28 |
20150147847 | Packages with Molding Material Forming Steps - A package includes a first package component having a top surface, a second package component bonded to the top surface of the first package component, and a plurality of electrical connectors at the top surface of the first package component. A molding material is over the first package component and molding the second package component therein. The molding material includes a first portion overlapping the second package component, wherein the first portion includes a first top surface, and a second portion encircling the first portion and molding bottom portions of the plurality of electrical connectors therein. The second portion has a second top surface lower than the first top surface. | 2015-05-28 |
20150147848 | RESIN-ENCAPSULATED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A resin-encapsulated semiconductor device is manufactured by mounting semiconductor elements on respective die pad portions of a frame. Electrodes on the surface of the semiconductor elements are wire bonded to lead portions of the frame. The die pad portions, semiconductor elements and lead portions are encapsulated with resin, leaving a bottom surface part of the lead portions exposed. The lead portions are partially cut by a rotary blade from an upper side of the resin to form concave parts in the lead portions, which are wet-etched to form exposed lead upper end parts. A plated layer is formed on the lead upper end parts and the lead bottom surface parts. The remaining parts of the lead portions with the plated layer are cut to separate the resin-encapsulated semiconductor device into individual pieces. | 2015-05-28 |
20150147849 | METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE - Disclosed herein is a method for manufacturing a semiconductor package. According to a preferred embodiment of the present invention, a method for manufacturing a semiconductor package includes: preparing a rectangular frame having a plurality of quadrangular holes; attaching a plurality of semiconductor chips and the frame on one surface of a tape; forming a molding part on the tape to cover the semiconductor chip and the frame; peeling the tape; forming a resin layer at a portion at which the tape is peeled; and forming a wiring on the resin layer to be connected to the semiconductor chip. | 2015-05-28 |
20150147850 | METHODS FOR PROCESSING A SEMICONDUCTOR WORKPIECE - Methods for processing a semiconductor workpiece can include providing a semiconductor workpiece that includes one or more kerf regions; forming one or more trenches in the workpiece by removing material from the one or more kerf regions from a first side of the workpiece; mounting the workpiece with the first side to a carrier; thinning the workpiece from a second side of the workpiece; and forming a metallization layer over the second side of the workpiece. | 2015-05-28 |
20150147851 | NO FLOW UNDERFILL OR WAFER LEVEL UNDERFILL AND SOLDER COLUMNS - A preassembly semiconductor device comprises chip soldering structures on a semiconductor chip and substrate soldering structures on a substrate corresponding to the chip soldering structures. The substrate soldering structures extend toward the chip soldering structures for forming solder connections with the chip soldering structures. The chip and the substrate are in preassembly positions relative to one another. The height of the substrate soldering structures is greater than the height of the chip soldering structures. A pre-applied underfill is contiguous with the substrate and is sufficiently thick so as to extend substantially no further than the full height of the substrate soldering structures. In another embodiment the height of the chip soldering structures is greater than the height of the substrate soldering structures and the pre-applied underfill is contiguous with the semiconductor chip and sufficiently thick so as to extend substantially no further than the full height of the chip soldering structures. A process comprises manufacturing semiconductor assemblies from these devices by soldering the chip and the substrate to one another | 2015-05-28 |
20150147852 | VACUUM CARRIER MODULE, METHOD OF USING AND PROCESS OF MAKING THE SAME - A vacuum carrier module includes a substrate having at least one hole and an edge region. There is at least one support on a top surface of the substrate. Further, a gel film is adhered to the edge region of the substrate. The at least one hole fluidly connects a reservoir located above the top surface of the substrate. A method of using a vacuum carrier module includes planarizing a gel film by passing an alignment material through a hole in a substrate to contact a first surface of the gel film, positioning at least one chip on a second surface of the gel film opposite the first surface. The method further includes encasing the at least one chip in a molding material and applying a vacuum to the first surface of the gel film. | 2015-05-28 |
20150147853 | CMOS WITH DUAL RAISED SOURCE AND DRAIN FOR NMOS AND PMOS - An apparatus and a method for creating a CMOS with a dual raised source and drain for NMOS and PMOS. The spacers on both stack gates are of equal thickness. In this method, a first insulating layer is formed on the surface. The first region is then masked while the other region has the first layer etched away and has an epitaxial source and drain grown on the region. A second layer is formed to all exposed surfaces. The second region is then masked while the first region is etched away. The epitaxial source and drain is formed on the first region. The second region can also be masked by adding a thin layer of undoped silicon and then oxidize it. Another way to mask the second region is to use a hard mask. Another way to form the second source and drain is to use amorphous material. | 2015-05-28 |
20150147854 | METHOD OF FABRICATING ELECTRONIC CIRCUIT - Provided is a method of fabricating an electronic circuit. The method includes preparing a substrate, forming a polymer film on the substrate, patterning the polymer film to form a polymer pattern, and forming an electronic device on the polymer pattern. | 2015-05-28 |
20150147855 | SEMICONDUCTOR DEVICE WITH HIGH BREAKDOWN VOLTAGE AND MANUFACTURE THEREOF - A semiconductor device includes: first and second n-type wells formed in p-type semiconductor substrate, the second n-type well being deeper than the first n-type well; first and second p-type backgate regions formed in the first and second n-type wells; first and second n-type source regions formed in the first and second p-type backgate regions; first and second n-type drain regions formed in the first and second n-type wells, at positions opposed to the first and second n-type source regions, sandwiching the first and the second p-type backgate regions; and field insulation films formed on the substrate, at positions between the first and second p-type backgate regions and the first and second n-type drain regions; whereby first transistor is formed in the first n-type well, and second transistor is formed in the second n-type well with a higher reverse voltage durability than the first transistor. | 2015-05-28 |
20150147856 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a trench in a semiconductor body. The method further includes doping a part of the semiconductor body via sidewalls of the trench by plasma doping. | 2015-05-28 |
20150147857 | MEMORY CELL - Memory cells are described with cross-coupled inverters including unidirectional gate conductors. Gate conductors for access transistors may also be aligned with a long axis of the inverter gate conductor. Contacts of one inverter in a cross-coupled pair may be aligned with a long axis of the other inverter's gate conductor. Separately formed rectangular active regions may be orthogonal to the gate conductors across pull up, pull down and access transistors. Separate active regions may be formed such that active regions associated with an access transistor and/or a pull up transistor are noncontiguous with, and narrower than, an active region associated with a pull down transistor of the inverter. The major components of 6T SRAM, and similar, memory cell topologies may be formed essentially from an array of rectangular lines, including unidirectional, gate conductors and contacts, and unidirectional rectangular active regions crossing gate conductors of the inverters and access transistors. | 2015-05-28 |
20150147858 | METHODS OF MANUFACTURING NON-VOLATILE MEMORY DEVICES - A non-volatile memory device includes a substrate including an active region and a field region, selection transistors and cell transistors on the active region, bit line contacts on the bridge portions, and shared bit lines electrically connected to the bit line contacts. The active region includes string portions and bridge portions. The string portions extend in a first direction and are arranged in a second direction substantially perpendicular to the first direction, and the bridge portions connect at least two adjacent string portions. Each bridge portion has a length in the first direction equal to or longer than about twice a width of each bit line contact in the first direction. | 2015-05-28 |
20150147859 | ANTIFUSE OF SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - An antifuse of a semiconductor device and a method of fabricating the same capable of causing an antifuse to stably operate by rupturing the antifuse at a specific point and stabilizing a current level when rupturing the antifuse are provided. The antifuse may include: a device isolation layer defining a first active region in a semiconductor substrate; a first and second junction regions provided in the first active region; a second active region formed over the first junction region; a gate insulating layer formed over the first active region and the second active region; and a gate electrode formed over the gate insulating layer. | 2015-05-28 |
20150147860 | METHODS OF FABRICATING SEMICONDUCTOR DEVICES - Semiconductor devices may include first and second fins that protrude from a substrate, extend in a first direction, and are separated from each other in the first direction. Semiconductor devices may also include a field insulating layer that is disposed between the first and second fins to extend in a second direction intersecting the first direction, an etch-stop layer pattern that is formed on the field insulating layer and a dummy gate structure that is formed on the etch-stop layer pattern. | 2015-05-28 |
20150147861 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING SURFACE TREATMENT AND SEMICONDUCTOR DEVICE MANUFACTURED BY THE METHOD - A method of manufacturing a semiconductor device includes forming a first plurality of recessed regions in a substrate, the substrate having a protruded active region between the first plurality of recessed regions and the protruded active region having an upper surface and a sidewall, forming a device isolation film in the first plurality of recessed regions, the device isolation film exposing the upper surface and an upper portion of the sidewall of the protruded active region, and performing a first plasma treatment on the exposed surface of the protruded active region, wherein the plasma treatment is performed using a plasma gas containing at least one of an inert gas and a hydrogen gas in a temperature of less than or equal to about 700. | 2015-05-28 |
20150147862 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate including a fin. The fin includes first and second fin portions. The first fin portion extends substantially in a horizontal direction to a surface of the semiconductor substrate. The second fin portion extends substantially in a vertical direction to the surface of the semiconductor substrate. The fin has a channel region. | 2015-05-28 |
20150147863 | SEMICONDUCTOR DEVICE HAVING A NECKED SEMICONDUCTOR BODY AND METHOD OF FORMING SEMICONDUCTOR BODIES OF VARYING WIDTH - Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body. | 2015-05-28 |
20150147864 | ONE TRANSISTOR AND ONE RESISTIVE (1T1R) RANDOM ACCESS MEMORY (RAM) STRUCTURE WITH DUAL SPACERS - The present disclosure provides methods of making resistive random access memory (RRAM) cells. The RRAM cell includes a transistor and an RRAM structure. The RRAM structure includes a bottom electrode having a via portion and a top portion, a resistive material layer on the bottom electrode having a width that is same as a width of the top portion of the bottom electrode; a capping layer over the bottom electrode, a first spacer surrounding the capping layer and a top electrode, a second spacer surround the top portion of the bottom electrode and the first spacer, and the top electrode. The RRAM cell further includes a conductive material connecting the top electrode of the RRAM structure to a metal layer. | 2015-05-28 |
20150147865 | RESISTIVE-SWITCHING MEMORY ELEMENTS HAVING IMPROVED SWITCHING CHARACTERISTICS - Resistive-switching memory elements having improved switching characteristics are described, including a memory element having a first electrode and a second electrode, a switching layer between the first electrode and the second electrode, the switching layer comprising a first metal oxide having a first bandgap greater than 4 electron volts (eV), the switching layer having a first thickness, and a coupling layer between the switching layer and the second electrode, the coupling layer comprising a second metal oxide having a second bandgap greater the first bandgap, the coupling layer having a second thickness that is less than 25 percent of the first thickness. | 2015-05-28 |
20150147866 | Resistive-Switching Memory Element - A resistive-switching memory element is described. The memory element includes a first electrode, a porous layer over the first electrode including a point defect embedded in a plurality of pores of the porous layer, and a second electrode over the porous layer, wherein the nonvolatile memory element is configured to switch between a high resistive state and a low resistive state. | 2015-05-28 |
20150147867 | Method Of Making a FinFET Device - A method of fabricating a fin-like field-effect transistor (FinFET) device is disclosed. A plurality of mandrel features are formed on a substrate. First spacers are formed along sidewalls of the mandrel feature and second spacers are along sidewalls of the first spacers. Two back-to-back adjacent second spacers separate by a gap in a first region and merge together in a second region of the substrate. A dielectric feature is formed in the gap and a dielectric mesa is formed in a third region of the substrate. A first subset of the first spacer is removed in a first cut. Fins and trenches are formed by etching the substrate using the first spacer and the dielectric feature as an etch mask. | 2015-05-28 |
20150147868 | LOCALLY ISOLATED PROTECTED BULK FINFET SEMICONDUCTOR DEVICE - A semiconductor device includes a bulk substrate having a plurality of trenches formed therein. The trenches define a plurality of semiconductor fins that are integral with the bulk semiconductor substrate. A local dielectric material is disposed in each trench and between each pair of semiconductor fins among the plurality of semiconductor fins. The semiconductor device further includes an etch resistant layer formed on the local dielectric material. | 2015-05-28 |
20150147869 | THREE-DIMENSIONAL INTEGRATED CIRCUIT DEVICE FABRICATION INCLUDING WAFER SCALE MEMBRANE - Method and Apparatus so configured for the fabrication of three-dimensional integrated devices. A crystalline substrate within an area of a donor semiconductor wafer is etched. The substrate side is located opposite a device layer and has a buried insulating layer and a substrate thickness. The etching removes at least a substantial portion of the crystalline substrate within the area such that the device layer and the buried insulating layer in the area is to conform to a pattern specific topology on an acceptor surface. The donor semiconductor wafer is supported with a supporting structure that allows the donor semiconductor wafer to flexibly conform to the pattern specific topology within at least a portion of the area after the etching to enable conformality and reliable bonding to the device surfaces of an acceptor wafer to form a three dimensional integrated device. | 2015-05-28 |
20150147870 | WAFER PROCESSING METHOD - A wafer processing method for dividing a wafer into individual devices along a plurality of crossing division lines includes preparing a frame having a plurality of crossing partitions corresponding to the division lines of the wafer, spreading a liquid resin on the front side or back side of the wafer and positioning the partitions of the frame in alignment with the division lines of the wafer, thereby covering with the liquid resin the regions on the front side or back side of the wafer other than the regions corresponding to the division lines, curing the liquid resin supplied to the front side or back side of the wafer and next removing the frame, thereby masking the regions other than the regions corresponding to the division lines, and plasma-etching the wafer processed by the masking to thereby divide the wafer into the individual devices along the division lines. | 2015-05-28 |
20150147871 | AZA-POLYSILANE PRECURSORS AND METHODS FOR DEPOSITING FILMS COMPRISING SAME - Described herein are precursors and methods for forming silicon-containing films. In one aspect, there is provided an aza-polysilane precursor comprising at least two Si—N bonds, at least one Si—Si bond, and at least two SiH | 2015-05-28 |
20150147872 | METHODS FOR FABRICATING INTEGRATED CIRCUITS USING CHEMICAL MECHANICAL POLISHING - Methods for fabricating integrated circuits are disclosed. In an exemplary embodiment, a method for fabricating an integrated circuit includes forming a silicon material layer over a semiconductor substrate. The semiconductor substrate includes a logic device region and a memory array region. The memory array region has a memory device formed on the semiconductor substrate. The method further includes forming a capping layer over the silicon material layer and over the memory device and removing the capping layer from over the memory device in the memory array region using a first chemical mechanical polishing process while leaving at least a first portion of the capping layer in place over the logic device region. Further, the method includes removing the first the silicon material layer from over the memory device in the memory array region using a second chemical mechanical polishing process. | 2015-05-28 |
20150147873 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM - Provided is a method of manufacturing a semiconductor device. The method includes: carrying a substrate, which has a Ge-containing film on at least a portion of a surface thereof, into a process chamber; heating an inside of the process chamber, into which the substrate is carried, to a first process temperature; and terminating a surface of the Ge-containing film, which is exposed at a portion of the surface of the substrate, by Si by supplying at least a Si-containing gas to the inside of the process chamber heated to the first process temperature. | 2015-05-28 |
20150147874 | METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE - The present invention provides a manufacturing method for forming a semiconductor structure, in which first, a substrate is provided, a hard mask is disposed on the substrate, the hard mask is then patterned to form a plurality of fin hard masks and a plurality of dummy fin hard masks, afterwards, a pattern transferring process is performed, to transfer the patterns of the fin hard masks and the fin hard masks into the substrate, so as to form a plurality of fin groups and a plurality of dummy fins. Each dummy fin is disposed on the end side of one fin group, and a fin cut process is performed, to remove each dummy fin. | 2015-05-28 |
20150147875 | METHODS FOR FORMING DOPED SILICON OXIDE THIN FILMS - The present disclosure relates to the deposition of dopant films, such as doped silicon oxide films, by atomic layer deposition processes. In some embodiments, a substrate in a reaction space is contacted with pulses of a silicon precursor and a dopant precursor, such that the silicon precursor and dopant precursor adsorb on the substrate surface. Oxygen plasma is used to convert the adsorbed silicon precursor and dopant precursor to doped silicon oxide. | 2015-05-28 |
20150147876 | LOW THRESHOLD VOLTAGE CMOS DEVICE - A replacement metal gate process in which a high-k dielectric is applied. The high-k dielectric may be doped with lanthanum in an NMOS region or aluminum in a PMOS region. Alternatively, after a dummy gate is removed in the NMOS and PMOS regions to leave openings in the NMOS and PMOS regions, lanthanum oxide may be deposited in the NMOS opening or aluminum oxide deposited in the PMOS opening. Thereafter, first work function metals are deposited in the NMOS opening and second work function metals are applied in the PMOS openings. A suitable gate electrode material may then fill the remainder of the NMOS and PMOS openings. | 2015-05-28 |
20150147877 | METAL OXIDE PROTECTIVE LAYER FOR A SEMICONDUCTOR DEVICE - Embodiments related to metal oxide protective layers formed on a surface of a halogen-sensitive metal-including layer present on a substrate processed in a semiconductor processing reactor are provided. In one example, a method for forming a metal oxide protective layer is provided. The example method includes forming a metal-including active species on the halogen-sensitive metal-including layer, the metal-including active species being derived from a non-halogenated metal oxide precursor. The example method also includes reacting an oxygen-containing reactant with the metal-including active species to form the metal oxide protective layer. | 2015-05-28 |
20150147878 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate having two surfaces. First side faces second side and includes recesses, and a plurality of through silicon vias (TSV), which penetrate through the semiconductor substrate, are exposed by the recesses. Even when the TSVs have different heights from each other or the degree of back-grinding is changed, due to a process parameters, yield of the semiconductor device is improved by reducing failure caused when a TSV is not exposed. | 2015-05-28 |
20150147879 | ULTRA-THIN STRUCTURE TO PROTECT COPPER AND METHOD OF PREPARATION - Methods of depositing thin, low dielectric constant layers that are effective diffusion barriers on metal interconnects of semiconductor circuits are described. A self-assembled monolayer (SAM) of molecules each having a head moiety and a tail moiety are deposited on the metal. The SAM molecules self-align, wherein the head moiety is formulated to selectively bond to the metal layer leaving the tail moiety disposed at a distal end of the molecule. A dielectric layer is subsequently deposited on the SAM, chemically bonding to the tail moiety of the SAM molecules. | 2015-05-28 |
20150147880 | CONTACT STRUCTURE AND FORMATION THEREOF - A semiconductor device and methods of formation are provided. A semiconductor device includes an annealed cobalt plug over a silicide in a first opening of the semiconductor device, wherein the annealed cobalt plug has a repaired lattice structure. The annealed cobalt plug is formed by annealing a cobalt plug at a first temperature for a first duration, while exposing the cobalt plug to a first gas. The repaired lattice structure of the annealed cobalt plug is more regular or homogenized as compared to a cobalt plug that is not so annealed, such that the annealed cobalt plug has a relatively increased conductivity or reduced resistivity. | 2015-05-28 |
20150147881 | PASSIVATION ASH/OXIDATION OF BARE COPPER - A semiconductor wafer has a clean, high quality Cu oxide formed at the surface of exposed Cu when an extended non-fabrication process time (such as shipping to an assembly/test site or prolonged storage) is expected. | 2015-05-28 |
20150147882 | Integrated Circuits with Reduced Pitch and Line Spacing and Methods of Forming the Same - A method includes performing a double patterning process to form a first mandrel, a second mandrel, and a third mandrel, with the second mandrel being between the first mandrel and the second mandrel, and etching the second mandrel to cut the second mandrel into a fourth mandrel and a fifth mandrel, with an opening separating the fourth mandrel from the fifth mandrel. A spacer layer is formed on sidewalls of the first, the mandrel, the fourth, and the fifth mandrels, wherein the opening is fully filled by the spacer layer. Horizontal portions of the spacer layer are removed, with vertical portions of the spacer layer remaining un-removed. A target layer is etched using the first, the second, the fourth, and the fifth mandrels and the vertical portions of the spacer layer as an etching mask, with trenches formed in the target layer. The trenches are filled with a filling material. | 2015-05-28 |
20150147883 | Post-CMP Cleaning and Apparatus for Performing the Same - A method of performing a post Chemical Mechanical Polish (CMP) cleaning includes picking up the wafer, spinning a cleaning solution contained in a cleaning tank, and submerging the wafer into the cleaning solution, with the cleaning solution being spun when the wafer is in the cleaning solution. After the submerging the wafer into the cleaning solution, the wafer is retrieved out of the cleaning solution. | 2015-05-28 |
20150147884 | SLURRY FOR CHEMICAL MECHANICAL POLISHING AND CHEMICAL MECHANICAL POLISHING METHOD - The present invention provides a slurry for chemical mechanical polishing, containing abrasive grain (a), compound (b) having an amino group having a pKa of more than 9, and not less than 3 hydroxyl groups, and water. | 2015-05-28 |
20150147885 | ARTICLE AND PROCESS FOR SELECTIVE ETCHING - A process for etching includes disposing an activating catalyst on a substrate; providing a vapor composition that includes an etchant oxidizer, an activatable etchant, or a combination thereof; contacting the activating catalyst with the etchant oxidizer; contacting the substrate with the activatable etchant; performing an oxidation-reduction reaction between the substrate, the activatable etchant, and the etchant oxidizer in a presence of the activating catalyst and the vapor composition; forming an etchant product that includes a plurality of atoms from the substrate; and removing the etchant product from the substrate to etch the substrate. | 2015-05-28 |
20150147886 | Method For Integrated Circuit Patterning - A method of forming a target pattern includes forming a plurality of lines over a substrate with a first mask and forming a spacer layer over the substrate, over the plurality of lines, and onto sidewalls of the plurality of lines. The method further includes removing at least a portion of the spacer layer to expose the plurality of lines and the substrate. The method further includes shrinking the spacer layer disposed onto the sidewalls of the plurality of lines and removing the plurality of lines thereby resulting in a patterned spacer layer over the substrate. | 2015-05-28 |
20150147887 | MECHANISMS FOR FORMING PATTERNS - The present disclosure provides a method for forming patterns in a semiconductor device. In accordance with some embodiments, the method includes providing a substrate and a patterning-target layer over the substrate; forming one or more mandrel patterns over the patterning-target layer; forming an opening in a resist layer by removing a first mandrel pattern and removing a portion of the resist layer that covers the first mandrel pattern; forming spacers adjacent to sidewalls of a second mandrel pattern; removing the second mandrel pattern to expose the spacers; forming a patch pattern over the spacers and aligned with the opening; etching the patterning-target layer using the patch pattern and the spacers as mask elements to form final patterns; and removing the patch pattern and the spacers to expose the final patterns. | 2015-05-28 |
20150147888 | LIQUID PROCESSING APPARATUS, LIQUID PROCESSING METHOD, AND STORAGE MEDIUM - A liquid processing apparatus of the present disclosure holds and rotate a substrate in a substrate holding unit, ejects an etching liquid while moving a main nozzle of a main nozzle unit between a first position where the etching liquid reaches a center of the substrate and a second position closer to a peripheral side of the substrate than the first position, and then, ejects the etching liquid to the substrate from a sub nozzle provided at a third position closer to the peripheral side of the substrate than the first position at an ejection flow rate higher than that from the main nozzle. | 2015-05-28 |
20150147889 | Tilted Plate For Batch Processing And Methods Of Use - A substrate processing chamber and methods for processing multiple substrates is provided and generally includes a gas distribution assembly, a susceptor assembly to rotate substrates along a path adjacent each of the gas distribution assembly and a gas diverter to change the angle of gas flow in the processing chamber. | 2015-05-28 |
20150147890 | MULTI-MODE THIN FILM DEPOSITION APPARATUS AND METHOD OF DEPOSITING A THIN FILM - A multi-mode thin film deposition apparatus including a reaction chamber, a carrying seat, a showerhead, an inert gas supplying source, a first gas inflow system and a second gas inflow system is provided. The carrying seat is disposed in the reaction chamber. The showerhead has a gas mixing room and gas holes disposed at a side of the gas mixing room. The gas mixing room is connected to the reaction chamber through the plurality of gas holes which faces the carrying seat. The first gas inflow system is connected to the reaction chamber and supplies a first process gas during a first thin film deposition process mode. The inert gas supplying source is connected to the gas mixing room for supplying an inert gas. The second gas inflow system is connected to the gas mixing room to supply a second process gas during a second thin film deposition process mode. | 2015-05-28 |
20150147891 | Method of Manufacturing Semiconductor Device, Substrate Processing Apparatus and Non-Transitory Computer-Readable Recording Medium - A thin film having a high resistance to HF and a low dielectric constant is formed with high productivity. A method of manufacturing a semiconductor device, includes performing a cycle a predetermined number of times, the cycle including: (a) supplying a source gas containing a predetermined element, carbon and a halogen element and having a chemical bond between the predetermined element and carbon to a substrate; and (b) supplying a reactive gas including a borazine compound to the substrate, wherein the cycle is performed under a condition where a borazine ring structure in the borazine compound and at least a portion of the chemical bond between the predetermined element and carbon in the source gas are preserved to form a thin film including the borazine ring structure and the chemical bond between the predetermined element and carbon on the substrate. | 2015-05-28 |
20150147892 | METHOD FOR FABRICATING SEMICONDUCTOR STRUCTURE, AND SOLID PRECURSOR DELIVERY SYSTEM - A method for fabricating a semiconductor structure is provided, including: providing a solid precursor having a first average particle size; solving the solid precursor in an organic solvent into an intermediate; recrystallizing the intermediate to form solid granules, wherein the solid granules has a second average particle size larger than the first average particle size; vaporizing the solid granules to form a film-forming gas; and depositing the film-forming gas on a substrate to form a resistance film. A method for modifying a resistance film source in a semiconductor fabrication and a solid precursor delivery system are also provided. The method for fabricating a semiconductor structure in the present disclosure can remove small particles or ultra-small particles from solid precursor, and does not need extra time to dump cracked solid precursor. | 2015-05-28 |
20150147893 | Precursors for CVD Silicon Carbo-Nitride Films - Classes of liquid aminosilanes have been found which allow for the production of silicon carbo-nitride films of the general formula Si | 2015-05-28 |
20150147894 | Substrate Processing Apparatus, Method of Manufacturing Semiconductor Device and Non-Transitory Computer-Readable Recording Medium - Heating within a plane of a substrate may be uniform while a thermal budget is decreased. A substrate processing apparatus includes a process chamber configured to accommodate a substrate; a substrate mounting unit installed in the process chamber and configured to have the substrate placed thereon; an electromagnetic wave supply unit configured to supply an electromagnetic wave to the substrate placed on the substrate mounting unit; and a choke groove formed on a side surface of the substrate mounting unit. | 2015-05-28 |
20150147895 | Techniques to Convert Signals Routed Through a Fabric Cable Assembly - Examples are disclosed for converting signals routed through a fabric assembly. In some examples, a connector housing may house a paddle card having a first edge portion coupled to a twin-axial cable having first signal pathways capable of routing first signals to/from a fabric controller integrated with a processor/processor package. The paddle card may have a second edge portion that may couple with an external fabric connector including a second plurality of signal pathways. In some examples, first signals received at the first edge portion may be converted to second signals following a coupling of the second edge portion with the external fabric connector. The second signals may then be routed via the second signal pathways included in and/or coupled with the external fabric connector. Other examples are described and claimed. | 2015-05-28 |
20150147896 | ELECTRICAL CONNECTOR - An electrical connector includes a circuit board, a chip module, an isolation portion, and at least one liquid metal conductor. Multiple first conducting portions are disposed on the circuit board, and multiple second conducting portions are disposed on the chip module. The second conducting portions correspond to the first conducting portions. The isolation portion is located between the circuit board and the chip module. An upper surface and a lower surface of the isolation portion urge against the chip module and the circuit board respectively. The isolation portion surrounds, joints, and seals the first conducting portion. The at least one liquid metal conductor is correspondingly disposed between the first conducting portion and the second conducting portion, and electrically conducting the circuit board and the chip module. The liquid metal conductor is gallium or gallium alloy. | 2015-05-28 |
20150147897 | SUPPORT DEVICE FOR ELECTRIFIED INSERT - A holder for supporting electrified inserts that may vary in width, comprises a base having a groove into which the insert can be placed. Two or more gaskets can be positioned in the groove with each gasket including a resilient section adapted to engage the insert so as to retain the insert securely in place within the groove. Each of the gaskets also includes an electrical conductor, such as an electrical wire, which may be embedded in the gasket, in a position where it makes electrical contact with the electrical terminals on the insert. | 2015-05-28 |
20150147898 | CONNECTOR - A connector is mateable with a mating connector along a predetermined direction. The connector comprises a holding member, a plurality of contacts and a plurality of contact prevention members. The holding member includes a holding portion. The plurality of contacts include held portions and main portions, respectively. The held portions are held by the holding portion. The main portions extend from the held portions, respectively, in the predetermined direction. The main portions project over the holding portion in the predetermined direction. Each of the main portions has a tubular shape. Each of the contact prevention members is made of insulator. The contact prevention members occupy insides of the main portions, respectively. The contact prevention members project over the main portions, respectively, in the predetermined direction. | 2015-05-28 |
20150147899 | SOCKET, A PLUG, AN ASSEMBLY, A METHOD OF SETTING A SOCKET AND A METHOD OF RESETTING A SOCKET - There is provided a socket for selectively coupling to a plug. The socket comprising a conforming portion adapted to conform to a first configuration complementary to the plug, wherein the first configuration allows the socket to electrically couple to the plug; and a securing member adjustable to releasably engage at least part of the conforming portion to substantially prevent the conforming portion from changing to a second configuration different from the first configuration, wherein the second configuration substantially prevents the socket from electrically coupling to the plug. There are also provided a plug configured to cooperate with the socket, a plug and socket assembly, a method of setting the socket for selectively coupling to the plug, and a method of resetting the socket programmed to selectively coupling to the plug. | 2015-05-28 |
20150147900 | Plug Connector And Electrical Connector Assembly - A plug connector being insertable into a corresponding socket connector is provided. The plug connector includes a first housing, a lock, and a first insertion device. The first housing includes a plurality of first connection terminal receiving passageways, while the lock is integrally connected with the first housing. The first insertion device formed on the lock. | 2015-05-28 |
20150147901 | CONNECTOR ASSEMBLY AND CONNECTOR PRODUCT - A connector assembly comprising: a first connector having a housing on which an elastic locking piece is suspended; a second connector having a housing on which a locking member mating with the elastic locking piece is formed so as to lock the first and second connectors together when the first and second connectors are mated together; and a connector position assurance device having a first stopper and a second stopper behind the first stopper. A first mating stopper is formed on the elastic locking piece, and a second mating stopper is formed on the housing of the first connector. The connector position assurance device only can be inserted into a first position under the elastic locking piece of the first connector when the first and second connectors are separate from each other. At the first position, the first stopper of the connector position assurance device is abutted against the first mating stopper of the first connector to prevent the connector position assurance device from being further pushed forward, and at the first position, the second stopper of the connector position assurance device is abutted against the second mating stopper of the first connector to prevent the connector position assurance device from being pulled out backward. | 2015-05-28 |
20150147902 | CONNECTOR AND MATING CONNECTOR - An electrical connector is configured to be electrically coupled to a mating connector. The connector includes a housing having a contact chamber and a connector face. The connector further includes a contact connector element accommodated in the contact chamber. The contact connector element includes a primary locking member configured to latch with the contact chamber. The connector also includes a secondary locking member assembled to the housing via the connector face. The secondary locking member is configured to interlock the contact connector element in the housing. | 2015-05-28 |