27th week of 2014 patent applcation highlights part 74 |
Patent application number | Title | Published |
20140189346 | LICENSE SERVER MANAGER - Technology is disclosed for managing provision of licenses in an unsecure communication network (“the technology”). Various embodiments of the technology include creating a secure communication tunnel between a client device of a user requesting a license and a license server that contains the license for a secure transmission of the license from the license server to the client device. After a first successful authentication of the user, the license management server generates and sends temporary credentials to the client device. The client device uses the temporary credentials to setup the secure communication tunnel with the license management server that will be used to access the license server. The client device sends the request to the license server over the secure communication tunnel, which in response transmits the license back to the client device over the secure communication tunnel. | 2014-07-03 |
20140189347 | VIRTUAL PAD - A system and method for communicating information over an insecure communications network include one or more computing devices that may access a first server via the communication network. In operation the first server displays an authentication Web page having a virtual pad with a plurality of characters that may be selected directly from a display of the computing device. | 2014-07-03 |
20140189348 | Integrated Data Deduplication and Encryption - The subject disclosure is directed towards encryption and deduplication integration between computing devices and a network resource. Files are partitioned into data blocks and deduplicated via removal of duplicate data blocks. Using multiple cryptographic keys, each data block is encrypted and stored at the network resource but can only be decrypted by an authorized user, such as domain entity having an appropriate deduplication domain-based cryptographic key. Another cryptographic key referred to as a content-derived cryptographic key ensures that duplicate data blocks encrypt to substantially equivalent encrypted data. | 2014-07-03 |
20140189349 | Decrypting Files for Data Leakage Protection in an Enterprise Network - A method of decrypting an encrypted file within an enterprise network is provided. The method includes identifying by a password collecting module a password entered during a file encryption procedure performed at a terminal and storing the password; receiving an encrypted file by a data leakage protection (DLP) module; and attempting to decrypt the encrypted file with the password by the DLP module. | 2014-07-03 |
20140189350 | SYSTEM AND METHOD FOR EFFICIENTLY ENROLLING, REGISTERING, AND AUTHENTICATING WITH MULTIPLE AUTHENTICATION DEVICES - A system, apparatus, method, and machine readable medium are described for multi-device operations within an authentication framework. For example, one embodiment of a method comprises: detecting N authentication devices on a client, wherein N>1; generating a N cryptographic entities, one for each of the N authentication devices; transmitting a command to the client to register each of the N cryptographic entities into each of the N authentication devices; executing the command on the client and responsively registering each of the N cryptographic entities into each of the respective N authentication devices; and subsequently using at least one of the authentication devices and its associated cryptographic entity for authenticating a user of the client over a network. | 2014-07-03 |
20140189351 | Print Release with End to End Encryption and Print Tracking - A method for encrypting print jobs that includes receiving output data, encrypting the output data with a randomly-generated symmetric session key, generating a session key header by encrypting the randomly-generated symmetric session key using an asymmetric user public key, and encrypting the session key header using a server public key. | 2014-07-03 |
20140189352 | METHOD AND SYSTEM FOR SECURED DATA STORAGE AND SHARING OVER CLOUD BASED NETWORK - The various embodiments herein provide a method and system for secure data storage and sharing over a cloud based network. The method comprises installing a client application on a user device, authenticating a client application user, extracting content from a data source, obtaining content sharing information from a content storage provider, sending a content distribution list and a content usage policy to an application server, encrypting the content by the client application, creating and sharing a secure content file, decrypting the content file, finding the content usage policy and sharing information from the content file, obtaining an updated content usage policy from the application server, authenticating the content recipient using an authentication mechanism, verifying the identity of the content recipient using an identity resolution mechanism, rendering the secure content file to the recipient, enforcing the content usage policy and sending content usage logs to the application server. | 2014-07-03 |
20140189353 | APPARATUS AND METHODS FOR PROVISIONING IN A DOWNLOAD-ENABLED SYSTEM - Apparatus and methods for provisioning of customer premise equipment (CPE) equipped with a secure microprocessor to receive e.g., digital video content by entering unique identification of the CPE at one or more servers located at the headend or other location of a content-based network. In one embodiment, the CPE comprises a download-enabled (e.g., DCAS) host with embedded cable modem and embedded set-top box functionality, and the provisioning includes enabling DOCSIS functionality of the CPE, assigning an IP address to the CPE and providing the CPE with a client image for the conditional access system chosen by the network operator. In one variant, the network operator can deactivate a provisioned device while connected to the network, as well when disconnected from the network. The network operator can also add, delete or replace conditional access client image in a provisioned device. | 2014-07-03 |
20140189354 | SYSTEMS AND METHODS FOR DIGITAL MULTIMEDIA CAPTURE USING HAPTIC CONTROL, CLOUD VOICE CHANGER, AND PROTECTING DIGITAL MULTIMEDIA PRIVACY - Provided are computer implemented methods and systems for multimedia capture and encrypting. According to the method, a first user input is received. Based on the first user input, one or more sensors are initiated to capture multimedia to obtain captured multimedia. The method further comprises receiving a second user input. Upon receiving the second user input, data associated with the first user input and the second user input are analyzed. Based on the analysis, one or more multimedia types are selected for recording from the captured multimedia based on predetermined rules. The selected one or more multimedia types are recorded to a memory. The recorded multimedia types are modified by a cloud-based voice changing unit. Furthermore, the recorded multimedia types and the modified multimedia types are encrypted to prepare the one or more multimedia types for sending to an intended recipient. | 2014-07-03 |
20140189355 | ENCRYPTING GLOBALLY UNIQUE IDENTIFIERS AT COMMUNICATION BOUNDARIES - Systems, methods, and computer-readable storage media for encrypting communications containing or referencing globally unique identifiers to prevent unauthorized access to content item data, such as through spoofing or ancillary information leakage. An example system configured to practice the method identifies a communication, between a storage environment and a client device, associated with a globally unique identifier for a content item stored in at least one of the storage environment and the client device. The content item can be addressable via a globally unique identifier. Prior to transmitting the communication, the system can encrypt a portion of the communication containing the globally unique identifier using an encryption key based on a client-specific key and a secret version-specific key to yield an encrypted communication, and transmit the encrypted communication to the client device. | 2014-07-03 |
20140189356 | METHOD OF RESTRICTING CORPORATE DIGITAL INFORMATION WITHIN CORPORATE BOUNDARY - A method of enforcing a virtual corporate boundary may include a client device requesting sensitive content from a network site on a server device responsive to a user's interaction with the client device. The server device can determine whether the user and/or client device are permitted to access the sensitive content. A secure element on the client device can establish a session key between the server device and the client device. The server device can render the sensitive content and send it to the client device, which can display the content to the user. | 2014-07-03 |
20140189357 | ENCRYPTION AND AUTHENTICATION BASED NETWORK MANAGEMENT METHOD AND APPARATUS - Disclosed are an encryption and authentication-based network management method and apparatus. A network management method according to an embodiment of the present invention includes: generating a public key and a private key for encryption and decryption of network attribute information to be used by a virtual machine positioned in the network server to provide the generated public key to a database; receiving network attribute information encrypted by the database with the public key from the database; and decrypting the received network attribute information with the private key to authenticate the network attribute information. | 2014-07-03 |
20140189358 | MULTIMEDIA DATA PROTECTION - A method of transmitting a media work such as a movie to a client is disclosed. The method includes (a) encrypting the work using a sequence of different keys corresponding to respective temporally spaced segments of the document, (b) transmitting software code containing an algorithm from a security server to the client, the algorithm having a result that is a function of the state of the client, (c) executing the code at the client and returning the result to the security server, (d) determining whether the result is indicative of an unmodified client. The method further includes (e) transmitting a segment from a server to the client, (f) securely streaming a key corresponding to the transmitted segment from a secure remote server to the client, (g) decrypting the segment using the obtained media key, (h) if step (d) indicates a modified client, preventing further keys from being transmitted, otherwise repeating steps (e) to (g) and repeating steps (b) to (d). | 2014-07-03 |
20140189359 | REMOTE AUTHENTICATION AND TRANSACTION SIGNATURES - Authentication devices and methods for generating dynamic credentials are disclosed. The authentication devices include a communication interface for communicating with a security device such as a smart card. A dynamic credential such as a one-time password (OTP) or a message authentication code (MAC) may be generated by receiving from a server an encrypted initialization seed encrypted with an asymmetric encryption algorithm using a public key of a public/private key pair, submitting the encrypted initialization seed to a security device, decrypting at the security device the encrypted initialization seed with a private key of the public/private key pair, returning the decrypted initialization seed to the authentication device, deriving at the authentication device a secret credential generation key from the decrypted initialization seed, and generating the dynamic credential by combining a dynamic variable with the secret credential generation key using a symmetric cryptographic dynamic credential generation algorithm. | 2014-07-03 |
20140189360 | SYSTEM AND METHOD FOR IMPLEMENTING TRANSACTION SIGNING WITHIN AN AUTHENTICATION FRAMEWORK - A system, apparatus, method, and machine readable medium are described for performing transaction signing within an authentication framework. For example, one embodiment of a method comprises: executing an online transaction between a first server and a client; providing transaction details of the online transaction to a second server; generating a signature over the transaction details using a key at the second server; transmitting an authentication request to the client with the signature and the transaction details; authenticating a user on the client to generate authentication data, the authentication data specifying whether the user was successfully authenticated on the client; and transmitting the authentication data, the transaction details, and the signature to the second server; using the transaction details and the key to validate the signature and using the authentication details to authenticate the client at the second server, wherein upon validating the signature and authenticating the client, the second server transmits a confirmation for the transaction to the first server. | 2014-07-03 |
20140189361 | NFORMATION PROCESSING APPARATUS, SIGNATURE GENERATION APPARATUS, INFORMATION PROCESSING METHOD, SIGNATURE GENERATION METHOD, AND PROGRAM - Provided is an information processing apparatus including a message generation unit that generates a message based on a pair of multi-order multivariate polynomials F=(f | 2014-07-03 |
20140189362 | METHOD FOR A SECURED BACKUP AND RESTORE OF CONFIGURATION DATA OF AN END-USER DEVICE, AND DEVICE USING THE METHOD - The method for a backup and restore of configuration data of an end-user device comprises the steps: encrypting the configuration data by using symmetric-key encryption with a symmetrical key, signing the encrypted configuration data with a device private key, and sending the encrypted and signed configuration data to a personal computer of a user of the end-user device, and/or to a storage location of a service provider network, for storage. For restoring of configuration data intended for use within the end-user device, a first or a second public key of an asymmetric key encryption system is used for validating signed configuration data provided by the service provider network or for validating signed configuration data stored on the personal computer of the user. | 2014-07-03 |
20140189363 | SEPARATE CRYPTOGRAPHIC KEYS FOR PROTECTING DIFFERENT OPERATIONS ON DATA - The disclosed embodiments provide a system that processes data. During operation, the system uses a first key to protect a write operation on the data. Next, the system uses a second key to protect a read operation on the data. | 2014-07-03 |
20140189364 | Privacy-Preserving Database System - A database system includes a server, index server and client. In one embodiment the server randomly permutes the order of database records. The server provides to the index server an array of encryption keys by generating a random encryption key corresponding to each permuted database record. The server encrypts each permuted database record with its corresponding encryption key. The index server computes and encrypts a sum of each encryption key and a corresponding random mask and sends a permuted array of masked keys to the server. The index server provides to the client an encrypted database record, and the mask and key corresponding to the encrypted record. The client sends the encrypted sum of the mask and key to the server. The server decrypts the masked key with a public key and sends the decrypted key to the client. The client then recovers the record key and decrypts the record. | 2014-07-03 |
20140189365 | SECURE KEY DERIVATION AND CRYPTOGRAPHY LOGIC FOR INTEGRATED CIRCUITS - A processor of an aspect includes root key generation logic to generate a root key. The root key generation logic includes a source of static and entropic bits. The processor also includes key derivation logic coupled with the root key generation logic. The key derivation logic is to derive one or more keys from the root key. The processor also includes cryptographic primitive logic coupled with the root key generation logic. The cryptographic primitive logic is to perform cryptographic operations. The processor also includes a security boundary containing the root key generation logic, the key derivation logic, and the cryptographic primitive logic. Other processors, methods, and systems are also disclosed. | 2014-07-03 |
20140189366 | Obfuscating Transformations on Data Array Content and Addresses - In a first computer (digital) data obfuscation process, data which is conventionally arranged in a data structure called an array (e.g., a table) and conventionally stored in computer or computer device memory is obfuscated (masked) by logically or mathematically combining the data, entry-by-entry, with a masking value which is computed as a logical or mathematical function of the entry itself or its index in the array, modulo a security value. The complementary unmasking value is a pointer to the entry's address in the table modulo the security value. In a second computer (digital) data obfuscation process, the addresses (location designations) in memory of a data array are themselves obfuscated (masked) by partitioning the array into blocks of entries and shuffling the order of the data entries in each block by a predetermined algorithm, resulting in a shuffled array also differing from the original array in terms of its size (the total number of entries). | 2014-07-03 |
20140189367 | DIGITAL-ENCRYPTION HARDWARE ACCELERATOR - An electronic device for encrypting and decrypting data blocks of a message having n data blocks in accordance with the data encryption standard (DES) has a first data processing channel having a first processing stage for performing encryption and decryption of data blocks of a predefined length, and a second data processing channel having a second processing stage for performing encryption and decryption of data blocks. The electronic device also has a control stage (FSM) for controlling the first processing stage and the second processing stage, so as to perform an encryption or decryption step with the second processing stage on an encrypted/decrypted data block output from the first processing stage, and to control the second processing stage to compute a message authentication code over the encrypted or decrypted message received from the first processing stage block-by-block. | 2014-07-03 |
20140189368 | INSTRUCTION AND LOGIC TO PROVIDE SIMD SECURE HASHING ROUND SLICE FUNCTIONALITY - Instructions and logic provide SIMD secure hashing round slice functionality. Some embodiments include a processor comprising: a decode stage to decode an instruction for a SIMD secure hashing algorithm round slice, the instruction specifying a source data operand set, a message-plus-constant operand set, a round-slice portion of the secure hashing algorithm round, and a rotator set portion of rotate settings. Processor execution units, are responsive to the decoded instruction, to perform a secure hashing round-slice set of round iterations upon the source data operand set, applying the message-plus-constant operand set and the rotator set, and store a result of the instruction in a SIMD destination register. One embodiment of the instruction specifies a hash round type as one of four MD5 round types. Other embodiments may specify a hash round type by an immediate operand as one of three SHA-1 round types or as a SHA-2 round type. | 2014-07-03 |
20140189369 | Instructions Processors, Methods, and Systems to Process Secure Hash Algorithms - A method of an aspect includes receiving an instruction. The instruction indicates a first source of a first packed data including state data elements a | 2014-07-03 |
20140189370 | MEMORY DEVICES, AND SYSTEMS AND METHODS FOR VERIFYING SECURE DATA STORAGE - A memory device includes an input/output (I/O) interface, a secure logic for receiving a storage verifying command including an expected value of secure data via the I/O interface, an I/O logic for receiving an input request for inputting user data into the memory device and/or an output request for outputting user data therefrom and perform one of the input request and/or the output request, and a memory unit including a secure area, accessible by the secure logic, for storing the secure data and a normal area, accessible by the I/O logic, for storing the user data. The secure logic reads the secure data from the secure area in response to the input of the storage verifying command and outputs a storage verifying result to the external device, without outputting the secure data to the external device, according to whether the secure data expected value is identical with the secure data. | 2014-07-03 |
20140189371 | METHOD AND APPARATUS FOR A TRUST PROCESSOR - In an embodiment, an apparatus includes a cryptographic processor within a wireless device. The cryptographic processor includes at least one cryptographic unit. The cryptographic processor also includes a nonvolatile memory to store one or more microcode instructions, wherein at least one of the one or more microcode instructions is related to a sensitive operation. The cryptographic processor also includes a controller to control execution of the one or more microcode instructions by the at least one cryptographic unit, wherein the controller is to preclude execution of the sensitive operation if the apparatus is within an untrusted state. | 2014-07-03 |
20140189372 | COMPUTER IMPLEMENTED METHOD FOR ANALYZING DATA OF A USER WITH THE DATA BEING STORED PSEUDONYMOUSLY IN A DATABASE - The invention relates to a computer implemented method for analyzing data of a first user, wherein an asymmetric cryptographic key pair is associated with the first user, said asymmetric cryptographic key pair comprising a public key and a private key, the data being stored pseudonymously in a database with the data being assigned to an identifier, wherein the identifier comprises the public key, the method comprising:
| 2014-07-03 |
20140189373 | METHOD FOR HARD PARTITIONING THE RESOURCES OF A SECURE COMPUTER SYSTEM - This invention relates to a method for hard partitioning the resources of a secure computer system. The system hardware comprises a hardware mechanism designed to: generate an encryption key with each new program detected by the system, the key being specific to each program, store the said key associated with a program identifier in the system resources, encrypt and store all the data created by the program in the system resources with the key that is specific to it, decrypt the data of the program with the key specific to it in response to a manipulation, call, read and/or write request from a requesting program. | 2014-07-03 |
20140189374 | SYSTEM AND METHOD FOR THE SECURE TRANSMISSION OF DATA - A system for securely transmitting data includes a control device and at least one security module. The control device is configured for producing a cryptographic key using a physically unclonable function (PUF). The at least one security module is configured for communicating with the control device at least one of confidentially and authentically using the cryptographic key. The control device has no storage for storing the cryptographic key. The control device includes at least one hardware device that is configured for providing a specific feature combination. The control device also includes a calculation unit that is configured for producing the cryptographic key using the specific feature combination and the physically unclonable function (PUF). The control device further includes a program-controlled device that is configured for executing a first computer program product, which is configured for performing the encrypted/authenticated communication with the security module via a first and second communication interfaces. | 2014-07-03 |
20140189375 | DISTRIBUTED POWER DELIVERY TO A PROCESSING UNIT - Technology is provided for distributed power delivery to a processing unit on a printed circuit board. In one example, a printed circuit board includes a processing unit coupled to multiple power channels, including first channels on a first side of the processing unit, and second channels on a second side of the processing unit. The printed circuit board further includes a first power supply coupled to the processing unit via the first channels, and a second power supply coupled to the processing unit via the second channels. The processing unit is configured to receive a total current, including currents drawn substantially simultaneously from the first power supply and the second power supply. The total current is about equivalent to a current the processing unit would draw from a single power supply. | 2014-07-03 |
20140189376 | TOTAL PLATFORM POWER CONTROL - Methods and apparatus relating to total platform power control are described. In one embodiment, power consumption by one or more processor cores of a processor and one or more components coupled to the processor are modified based on a total platform power consumption value. The platform, in turn, includes the processor and the one or more components. Other embodiments are also disclosed and claimed. | 2014-07-03 |
20140189377 | APPARATUS AND METHOD FOR INTELLIGENTLY POWERING HETERGENEOU PROCESSOR COMPONENTS - An intelligent power allocation architecture for a processor. For example, one embodiment of a processor comprises: a plurality of processor components for performing a corresponding plurality of processor functions; a plurality of power planes, each power plane associated with one of the processor components; and a power control unit (PCU) to dynamically adjust power to each of the power planes based on user experience metrics, workload characteristics, and power constraints for a current use of the processor. | 2014-07-03 |
20140189378 | TABLE DRIVEN MULTIPLE PASSIVE TRIP PLATFORM PASSIVE THERMAL MANAGEMENT - Methods and apparatus relating to table driven multiple passive trip, platform passive thermal management are described. In one embodiment, the power consumption limit of one or more components of a platform is modified based on one or more thermal relationships between one or more power consuming components of the platform and one or more heat generating components of the platform. Furthermore, a first relationship of the one or more thermal relationships indicates a mapping between a plurality of temperature thresholds and a corresponding plurality of performance limits. Other embodiments are also claimed and disclosed. | 2014-07-03 |
20140189379 | Power Supply Unit with Configurable Output Rails - A power supply unit includes two or more power converters. Each power converter provides power at a corresponding output terminal of the power supply unit. The power supply unit also includes a controller to determine an operating mode of the power supply unit. When the power supply unit is operating in one mode, the controller disables transmission of power at one output teiniinal in response to detecting a fault associated with another output terminal. | 2014-07-03 |
20140189380 | CONTROLLING PARTNER PARTITIONS IN A CLUSTERED STORAGE SYSTEM - A rack-power control module (RPC) module is used for allowing a local storage partition, located on a local server, for controlling a destination storage partition, located on a destination server, by piggybacking commands on power alerts issued by the RPC module in a clustered storage system. | 2014-07-03 |
20140189381 | SEMICONDUCTOR DEVICE HAVING ACTIVE MODE AND STANDBY MODE - In an active mode, a VDD line receives an internal power supply voltage from an external regulator. A VDD_RAM line receives an internal power supply voltage from an internal regulator. A PMOS switch includes a first PMOS transistor having a source and an N-type well connected to the VDD line, and a second PMOS transistor having a source and an N-type well connected to the VDD_RAM line and a drain connected to a drain of the first PMOS transistor. The first PMOS transistor is controlled based on a control command from a system control circuit and a voltage of the VDD_RAM line. The second PMOS transistor is controlled based on the control command and a voltage of the VDD line. | 2014-07-03 |
20140189382 | AUTOMATED SHUTDOWN METHODOLOGY FOR A TIERED SYSTEM - Various aspects of the present invention relate to automated shutdown of a tiered system. In one embodiment, at a host, an instruction is received to execute a command that instructs at least one system at a site and in communication with the host via one or more fibre channels to each execute a script, the script being for automatically shutting down components of the at least one system in an order defined by the script. The command is issued to the at least one system at the site via the one or more fibre channels. | 2014-07-03 |
20140189383 | Low Power Paging of Consumer Electronics - Systems, apparatuses, and methods are configured to monitor signals received via a transmission medium by a paging monitor to detect an activity trigger. Systems, apparatuses, and methods are further configured to, in response to detecting the activity trigger, cause, by the paging monitor, a main receiver to transition from an energy conservation mode to an active mode to monitor the transmission medium for data traffic. | 2014-07-03 |
20140189384 | METHOD AND ARRANGMENT FOR REMOTE CONTROLLING A POWER CONSUMPTION STATE OF A NETWORK DEVICE - The instant invention improves the control of a low-power consumption state of network devices linked to a network switch by a suitable network such as an optical network. It allows for the sleep mode also to shut down the power supplies of the components of the network device necessary for the normal data link layer network communication according to the OSI model and the higher layers of the communication protocols. In the same way, the invention prevents that a disruption of the optical network leads to a sleep mode of the network device. Further, even in a freeze state, it is possible to activate the network device and bring it in a sleep mode. For this purpose, a special communication protocol is provided. | 2014-07-03 |
20140189385 | INTELLIGENT RECEIVE BUFFER MANAGEMENT TO OPTIMIZE IDLE STATE RESIDENCY - Methods and systems may provide for determining a plurality of buffer-related settings for a corresponding plurality of idle states and outputting the plurality of buffer-related settings to a device on a platform. The device may determine an observed bandwidth for a channel associated with a receive buffer and identify a selection of a buffer-related setting from the plurality of buffer-related settings based at least in part on the observed bandwidth. In one example, each buffer-related setting includes a latency tolerance and a corresponding idle duration. | 2014-07-03 |
20140189386 | SUPPLY-VOLTAGE CONTROL FOR DEVICE POWER MANAGEMENT - One embodiment provides a method for reducing leakage current in device logic having an operational supply-voltage threshold, a nonzero data-retention supply-voltage threshold, and two or more on-die transistor switches to switchably connect a voltage source to the device logic. After the logic enters an idle period, one or more of the switches are opened to lower a supply voltage of the logic below the operational supply-voltage threshold but above the data-retention supply-voltage threshold. When the logic exits the idle period, one or more of the switches are closed to raise the supply voltage of the logic above the operational supply-voltage threshold. | 2014-07-03 |
20140189387 | STAGED POWER DISTRIBUTION CONTROL - Various embodiments are directed to restrictions in portable computing device electric power to accommodate reductions in the voltage level of a power source. An apparatus comprises a controller caused to receive configuration data from a main processor circuit specifying a voltage level threshold and selected action to take to reduce electric power to a first component in response to the voltage level falling below the first voltage level threshold, recurringly monitor the voltage level; based on the voltage level falling below the first voltage level threshold, take the first selected action and transmit a signal to the main processor circuit indicating that the voltage level has fallen below the first voltage level threshold and that the first selected action has been taken; transmit the voltage level to the main processor circuit; receive a signal from the main processor circuit to undo the first selected action; and so undo. | 2014-07-03 |
20140189388 | PEER ASSISTED MOBILE DEVICE BATTERY EXTENSION SYSTEM - A system configured to manage battery energy of a mobile device includes a primary mobile device and at least one peer device. The primary mobile device includes a power unit, a main communication module to electrically communicate with a peer device, and a peer assisted module in electrical communication with the power unit and the main communication module. The peer assisted module determines an energy level of the energy unit, and determines a task to be executed by the peer device. The peer device receives the task transmitted from the primary mobile device. The peer device further includes a peer process management module that executes at least one computation that completes the task, and communicates a completed task to the primary mobile device. | 2014-07-03 |
20140189389 | PEER ASSISTED MOBILE DEVICE BATTERY EXTENSION SYSTEM - A system configured to manage battery energy of a mobile device includes a primary mobile device and at least one peer device. The primary mobile device includes a power unit, a main communication module to electrically communicate with a peer device, and a peer assisted module in electrical communication with the power unit and the main communication module. The peer assisted module determines an energy level of the energy unit, and determines a task to be executed by the peer device. The peer device receives the task transmitted from the primary mobile device. The peer device further includes a peer process management module that executes at least one computation that completes the task, and communicates a completed task to the primary mobile device. | 2014-07-03 |
20140189390 | SYSTEM AND METHOD FOR CAUSING REDUCED POWER CONSUMPTION ASSOCIATED WITH THERMAL REMEDIATION - Particular embodiments described herein can offer a method that includes receiving a signal indicating whether at least one device is in a low power mode, determining that the at least one device is in a first thermally benign state based, at least in part, on the signal, and performing a first operation associated with a reduced thermal remediation power consumption. | 2014-07-03 |
20140189391 | SYSTEM AND METHOD FOR CONVEYING SERVICE LATENCY REQUIREMENTS FOR DEVICES CONNECTED TO LOW POWER INPUT/OUTPUT SUB-SYSTEMS - In at least one embodiment described herein, an apparatus is provided that can include means for communicating a latency tolerance value for a device connected to a platform from a software latency register if a software latency tolerance register mode is active. The apparatus may also include means for communicating the latency tolerance value from a hardware latency register if a host controller is active. The latency tolerance value can be sent to a power management controller. More specific examples can include means for communicating a latency tolerance value from the software latency register if the software latency tolerance register mode is not active and the host controller is not active. The apparatus can also include means for mapping a resource space in the software latency register for the device using a BIOS/platform driver. The mapping can be achieved using an advanced configuration and power interface device description. | 2014-07-03 |
20140189392 | COMMUNICATION LINK AND NETWORK CONNECTIVITY MANAGEMENT IN LOW POWER MODE - Methods and apparatus relating to communication link and network connectivity management in low power mode are described. In one embodiment, logic manages one or more external communication network links (also referred as “links”) in response to a determination that a processor has entered a low power consumption state and based on policy information. The logic also blocks/intercepts one or more signals, corresponding to management of the one or more links, that are directed to the processor to allow the processor to stay in the low power consumption. Other embodiments are also claimed and disclosed. | 2014-07-03 |
20140189393 | POWER SUPPLY AND METHOD FOR SUPPLYING POWER TO MOTHERBOARD - A monitored and high-efficiency power supply for a motherboard includes an AC-to-DC conversion circuit, a control circuit, a standby circuit, a main output circuit, a standby output circuit. The AC-to-DC conversion circuit converts an AC source voltage to a DC voltage. When the power supply is in a standby state, the standby circuit is enabled but when the power supply is in a normal working state, the standby circuit is disabled, and the control circuit is enabled to control only the main voltage output to the motherboard. A method for supplying power to a motherboard is also provided. | 2014-07-03 |
20140189394 | ELECTRONIC DEVICE AND POWER-SUPPLY CONTROL METHOD - According to one embodiment, a electronics device includes a setting module, a determination module, a control module. The setting module is configured to set a power consumption reference value for a predetermined period of time. The determination module is configured to determine whether an amount of power consumption of an external power supply exceeds the power consumption reference value in the predetermined period of time. The control module is configured to cause a power reduction process to be performed when the amount of power consumption is determined as exceeding the power consumption reference value, the power reduction process reducing the amount of power consumption of the external power supply. | 2014-07-03 |
20140189395 | INTELLIGENT POWER MANAGEMENT FOR A MULTI-DISPLAY MODE ENABLED ELECTRONIC DEVICE - Particular embodiments described herein provide an apparatus to control power consumption including logic, at least partially including hardware logic, to determine whether an electronic device is using an external display, determine whether a user input has been received by the electronic device within a predetermined time period when the electronic device is using the external display, and control power consumption by a display of the electronic device based at least in part on whether user input has been received within the predetermined time period. | 2014-07-03 |
20140189396 | COMMUNICATION APPARATUS, INFORMATION PROCESSING APPARATUS, CONTROL METHOD FOR COMMUNICATION APPARATUS, CONTROL METHOD FOR INFORMATION PROCESSING APPARATUS, AND COMPUTER-READABLE STORAGE MEDIUM - A communication apparatus includes a connection unit configured to connect the communication apparatus to an external apparatus, a determination unit configured to determine whether the external apparatus is connected to the communication apparatus via the connection unit in a first connection mode, the first connection mode being a mode in which the external apparatus establishes a connection to a pre-registered apparatus, and a control unit configured to decide, based on a determination result obtained by the determination unit, whether to allow an operation for powering off the external apparatus to be performed. | 2014-07-03 |
20140189397 | STATE CONTROL DEVICE, STATE CONTROL METHOD AND PROGRAM - A state control device which controls return from a power saving state to a normal operating state by an extremely simple operation without wastefully consuming power. In a power saving state the functions of an LCD unit (including a backlight) and a touch panel unit are disabled. When a function-enabled acceleration sensor unit detects a shake (motion) of a portable terminal, the functions of the touch panel unit are enabled. When the enabled touch panel unit detects a touch operation, a transition is made to a normal operating state whereby the LCD unit (including a backlight) is set ON for screen display. Therefore, it is unnecessary to press the power supply button provided in a difficult position to operate from the viewpoint of preventing erroneous operation as in conventional technology, and return from the power saving state to the normal operating state can be achieved with a simple operation. | 2014-07-03 |
20140189398 | TECHNIQUES FOR PLATFORM DUTY CYCLING - Various embodiments are generally directed to an apparatus, method and other techniques for detecting active and semi-active workloads during execution on a platform processing device and enabling a duty cycle process to reduce thermal output and power consumption, and align unaligned activity. In various embodiments, the duty cycle processing may be enabled during an active workload when thermal output or power consumption is above a thermal threshold or power consumption threshold that is below an efficient operating point for the platform processing device. The duty cycle processing may also be enabled during semi-active workloads when the workload causes the platform processing device to be underutilized and unaligned. The duty cycle processing may comprise enabling a forced idle period for the platform processing device. Other embodiments are described and claimed. | 2014-07-03 |
20140189399 | METHODS, SYSTEMS AND APPARATUS TO MANAGE POWER CONSUMPTION OF A GRAPHICS ENGINE - Methods and apparatus are disclosed to manage power consumption at a graphics engine. An example method to manage power usage of a graphics engine via an application level interface includes obtaining a policy directive for the graphics engine via the application level interface, the policy directive identifying a threshold corresponding to power consumed by the graphics engine operating in a first graphics state. The example method also includes determining a power consumed by the graphics engine during operation. The example method also includes comparing the power consumed to the threshold of the policy directive, and when the threshold is met, setting the graphics engine in a second graphics state to cause the graphics engine to comply with the policy directive. | 2014-07-03 |
20140189400 | PROCESSING SYSTEM AND ASSOCIATED METHOD - The present invention provides a processing system and associated method; the processing system includes a processing unit, a peripheral unit consuming system resource, a support unit capable of providing the system resource, a buffer capable of storing a portion of the system resource, and a system power manager (SPM). When the processing unit suspends for idle, the peripheral unit consumes the buffer and thus does not need system resource from the support unit, so the support unit and/or the corresponding system resource can be powered down. When the buffer is consumed, the SPM is capable of allocating the system resource for the peripheral unit in response to request of the peripheral unit, so the processing unit does not have to leave idle for allocating the system resource. | 2014-07-03 |
20140189401 | BLOCK-LEVEL SLEEP LOGIC - In one embodiment, a processor includes at least one sleep block and a central sleep controller. The at least one sleep block may include at least one execution unit, at least one processor component, and sleep logic. The central sleep controller may be to program the sleep logic to perform at least one sleep transition for the at least one sleep block, and to operate in a first sleep mode. The sleep logic may be to perform the at least one sleep transition for the at least one sleep block without waking the central sleep controller from the first sleep mode. Other embodiments are described and claimed. | 2014-07-03 |
20140189402 | Apparatus And Method To Manage Energy Usage Of A Processor - In an embodiment, a processor includes at least one processor core and power control logic having energy usage logic to predict an energy usage of the processor and a voltage regulator coupled to the processor, during a low power period according to a first voltage regulator control mode and a second voltage regulator control mode, and to control the voltage regulator based at least in part on the predicted energy usage. Other embodiments are described and claimed. | 2014-07-03 |
20140189403 | PERIODIC ACTIVITY ALIGNMENT - Methods and systems may provide for determining a latency constraint associated with a platform and determine an idle window based on the latency constraint. In addition, a plurality of devices on the platform may be instructed to cease one or more activities during the idle window. In one example, the platform is placed in a sleep state during the idle window. | 2014-07-03 |
20140189404 | ADAPTIVE THERMAL CONTROL OF ELECTRONIC DEVICES - An apparatus includes logic to control heat generation in a device. The device to operate ate leas in one of a first state and a second state, wherein the device to consume more power in the first state than in the second state. The device to connect to a network at least for a portion of time while in the second state. The logic to select a plurality of thermal control solutions to decrease the generation of heat in the device in the second state, the selected thermal control solution to be performed while the device is in the second state to reduce the generated heat to below a predetermined level. | 2014-07-03 |
20140189405 | APPARATUS AND METHOD TO MANAGE ENERGY USAGE OF A PROCESSOR - In an embodiment, a processor includes at least one processor core and power control logic having energy usage logic to predict an energy usage of the processor and a voltage regulator coupled to the processor, during a low power period according to a first voltage regulator control mode and a second voltage regulator control mode, and to control the voltage regulator based at least in part on the predicted energy usage. Other embodiments are described and claimed. | 2014-07-03 |
20140189406 | COMPUTER DEVICE AND METHOD OF POWER MANAGEMENT OF THE SAME - A method of power management of a computer device includes a number of steps. When a decision element determines that the computer device must enter a power saving mode, the decision element generates a power saving mode signal. When an embedded controller detects the power saving mode signal, the embedded controller determines whether an NFC transceiving module is sending or receiving information. If the NFC transceiving module is sending or receiving information, the embedded controller postpones entering into the power saving mode by the computer device until the NFC transceiving module finishes sending or receiving information. | 2014-07-03 |
20140189407 | DATA STORAGE DEVICE AND METHOD FOR OPERATING THE SAME - A data storage device and a method for operating the same are provided. In the data storage device and the method for operating the same, a predetermined number of memory chips are operated based on a usable power limitation when a power supply is supplied from a finite power supply source such as a battery, and as many memory chips as possible are operated in parallel. Accordingly, performance of the data storage device may be improved. | 2014-07-03 |
20140189408 | SYSTEM AND METHOD FOR REDUCING POWER CONSUMPTION - Particular embodiments described herein can offer an apparatus that includes logic, the logic at least partially comprising hardware logic to receive a first notification indicating that at least one first user interaction device has become precluded; and cause, by a processor and absent intermediate operation of operating system software, disabling of at least one second user interaction device based, at least in part, on the first notification. | 2014-07-03 |
20140189409 | SYSTEM AND METHOD FOR PROVIDING UNIVERSAL SERIAL BUS LINK POWER MANAGEMENT POLICIES IN A PROCESSOR ENVIRONMENT - One particular example implementation may include an apparatus that includes logic, at least a portion of which is in hardware, the logic configured to: determine that a first device maintains a link to a platform in a selective suspend state; assign a first latency value to the first device; identify at least one user detectable artifact when a second device exits the selective suspend state; and assign, to the second device, a second latency value that is different from the first value. | 2014-07-03 |
20140189410 | SYSTEMS AND METHODS FOR PREDICTIVE POWER MANAGEMENT IN A COMPUTING CENTER - Aspects and implementations of the present disclosure are directed to systems and methods for predictive power management in a computing center. In general, in some implementations, a system for conserving resources in a multi-processor computing environment monitors usage of the processors in the environment and maintains a sorted list of usage changes that occur in each of a plurality of periodic intervals. The system uses the sorted list to predict, according to configurable parameters, how many processors will need to be available during a subsequent interval. In some implementations, the monitored intervals are consecutive and immediately prior to the subsequent interval. In some implementations, the usage changes during a periodic interval are determined as the difference between a maximum number of active-busy processors during the periodic interval and an initial number of active-busy processors for the periodic interval. | 2014-07-03 |
20140189411 | POWER CONTROL FOR CACHE STRUCTURES - Techniques are disclosed relating to reducing power consumption in integrated circuits. In one embodiment, an apparatus includes a cache having a set of tag structures and a power management unit. The power management unit is configured to power down a duplicate set of tag structures in responsive to the cache being powered down. In one embodiment, the cache is configured to provide, to the power management unit, an indication of whether the cache includes valid data. In such an embodiment, the power management unit is configured to power down the cache in response to the cache indicating that the cache does not include valid data. In some embodiments, the duplicate set of tag structures is located within a coherence point configured to maintain coherency between the cache and a memory. | 2014-07-03 |
20140189412 | TIME SEQUENCE CIRCUIT FOR POWER SUPPLY UNIT - A time sequencing circuit for a power supply unit to ensure the correct sequencing of system voltages for a computer from a power supply unit includes first to fifth resistors, an electronic switch, first to third comparators, and a capacitor. Each of the first to third comparators includes an inverting input terminal, a non-inverting input terminal, and an output terminal When the power supply unit outputs all required voltages, the power supply unit outputs a high-voltage level indicating power good and the computer can start up power good signal. If one of the voltages is not outputted, the power supply unit outputs a low-voltage level good signal until any non-output of voltage is cured. | 2014-07-03 |
20140189413 | DISTRIBUTED POWER MANAGEMENT FOR MULTI-CORE PROCESSORS - A system and method for performing distributed power control in a processor comprising an array of cores enables each core to regulate power at least partially independently. Global power management settings are made accessible to all cores and communication between cores propagates power consumption information between nearest neighbors in the array. Each core attempts to best regulate its own power consumption in accordance with global power consumption information and/or specific instructions from a global power manager. In this manner local opportunistic load balancing may be achieved in a scalable manner suitable for a large array of cores. | 2014-07-03 |
20140189414 | DATA BUS SYNCHRONIZER - A data bus synchronizer includes a plurality of registers arranged in a cascade, configured to generate a synchronized output in response to sampling an asynchronous bus without an enable signal, where the plurality of registers receive a value on the asynchronous bus. A last register of the plurality of registers is configured to generate the synchronized output in response to a load enable signal. The data bus synchronizer further includes a logic block configured to generate the load enable signal on satisfaction of a logic condition. | 2014-07-03 |
20140189415 | MEDIA PERIPHERAL INTERFACE, ELECTRONIC DEVICE WITH MEDIA PERIPHERAL INTERFACE, AND COMMUNICATION METHOD BETWEEN PROCESSOR AND PERIPHERAL DEVICE - A media peripheral interface for communication between a processor and a peripheral device includes a clock port, a plurality of data I/Os, and a data strobe port. The clock port is operative to transfer a clock signal to the peripheral device. The data I/Os are provided for command transfer to the peripheral device and for data transfer to and from the peripheral device. The data strobe port is operative to transfer a data strobe signal to or from the peripheral device according to an instruction that the processor issues to the peripheral device. According to the clock signal, command information transferred via the data I/Os is captured. According to rising edges and falling edges of the data strobe signal, data transferred via the data I/Os are captured. | 2014-07-03 |
20140189416 | PREDICTIVE SEQUENTIAL CALCULATION DEVICE - A calculation device is provided that executes calculations within real-time restrictions. The calculation device implements a step of predicting a processing time of a calculation related to the amount and property of input data based on a prediction model; a step of adjusting the processing time by decreasing the amount of data used for the calculation or decreasing the number of iterative calculations when the processing time exceeds a time slice allocated to the calculation; a step of executes the calculation using the adjusted processing time; a step of updating, as required, the prediction model used for predicting the processing time according to the result of the calculation which is executed in a period where the calculation is not performed while implementing a change of the amount of data or the number of iterative calculations or change to an approximation. | 2014-07-03 |
20140189417 | APPARATUS AND METHOD FOR PARTIAL MEMORY MIRRORING - An apparatus and method are described for performing partial memory mirroring operations. For example, one embodiment of a processor comprises: a processor core for generating a read or write transaction having a system memory address; a home agent identified to service the read or write transaction based on the system memory address; one or more target address decoders (TADs) associated with the home agent to determine whether the system memory address is within a mirrored memory region or a non-mirrored memory region, wherein: if the system memory address is within a mirrored memory region, then the one or more TADs identifying multiple mirrored memory channels for the read or write transaction; and if the system memory address is not within a mirrored memory region, then the one or more TADs identifying a single memory channel for the read or write transaction. | 2014-07-03 |
20140189418 | EXPANDER TO CONTROL MULTIPATHS IN A STORAGE NETWORK - An identification request is received from a host device. A virtual address that identifies at least the first device and a second device is determined. The first device and the second device are coupled together to form a plurality of redundant paths between the host device and a target device. A plurality of target ports associated with the target device are determined. A single virtual target port address is assigned to the plurality of target ports associated with the target device. A first of the plurality of redundant paths between the host device and the target device is designated as an active path. The first of the plurality of redundant paths between the host device and the target device is associated with a first of the plurality of target ports. The virtual address and the virtual target port address are transmitted to the host device. | 2014-07-03 |
20140189419 | METHOD AND APPARATUS FOR PROVIDING COMPUTING RESOURCES - Embodiments of the present invention relate to a method and apparatus for providing computing resources to a user. In one embodiment of the present invention, there is provided a method for providing computing resources to a user, comprising: in response to a request from the user, looking up in a profile repository a profile corresponding to the user's domain information; requesting at least one computing resource associated with the profile; integrating the at least one computing resource into a virtual datacenter; and providing the virtual datacenter to the user; wherein the at least one computing resource is physically deployed in a distributed manner. In one embodiment of the present invention, there is provided an apparatus for providing computing resources to a user. | 2014-07-03 |
20140189420 | MEMORY SYSTEM - A memory system includes a volatile first storing unit, a nonvolatile second storing unit in which data is managed in a predetermined unit, and a controller that writes data requested by a host apparatus in the second storing unit via the first storing unit and reads out data requested by the host apparatus from the second storing unit to the first storing unit and transfers the data to the host apparatus. The controller includes a management table for managing the number of failure areas in a predetermined unit that occur in the second storing unit and switches, according to the number of failure areas, an operation mode in writing data in the second storing unit from the host apparatus. | 2014-07-03 |
20140189421 | Non-Volatile Memory Program Failure Recovery Via Redundant Arrays - Non-volatile memory program failure recovery via redundant arrays enables higher programming bandwidth and/or reduced latency in some storage subsystem implementations, e.g. a solid-state disk. Data to program N portions of a plurality of non-volatile memories is received at a non-volatile memory controller. The data includes particular data to program a particular one of the N portions. The particular data is stored in an allocated buffer associated with the non-volatile memory controller. Programming the particular data to a particular one of the non-volatile memories is begun. Redundancy information sufficient to recover from failures of M of the N portions is updated. The allocated buffer is freed. At least one of the storing, the beginning programming, the updating, and the freeing is in response to the receiving of the particular data. The freeing is prior to the particular non-volatile memory completing the programming. | 2014-07-03 |
20140189422 | INFORMATION PROCESSING APPARATUS AND STORED INFORMATION ANALYZING METHOD - An information processing apparatus includes: a dividing unit that divides a storage region in accordance with storage region management information, the storage region management information and type information; a setting unit that selects a first division region from division regions indicative of the divided storage region and that puts the first division region in a stand-by state; a detecting unit that detects an abnormality in information processing when the information processing is performed using a second division region of the division regions; a controlling unit that puts the second division region in the stand-by state and that causes the first division region, which has been in the stand-by state, to recover; and an analyzing unit that adds the second division region that is in the stand-by state to a physical address space, and that analyzes information stored in the second division region. | 2014-07-03 |
20140189423 | TWO LEVEL ADDRESSING IN STORAGE CLUSTERS - Digital objects are stored and accessed within a fixed content storage cluster by using a page mapping table and a pages index. A stream is read from the cluster by using a portion of its unique identifier as a key into the page mapping table. The page mapping table indicates a node holding a pages index indicating where the stream is stored. A stream is written by storing the stream on any suitable node and then updating a pages index stored within the cluster responsible for knowing the location of digital objects having unique identifiers that fall within a particular address range. The cluster recovers from a node failure by first replicating streams from the failed node and reallocating a page mapping table to create a new pages index. The remaining nodes send records of the unique identifiers corresponding to objects they hold to the new pages index. | 2014-07-03 |
20140189424 | Apparatus and Method for Parity Resynchronization in Disk Arrays - A method for parity resynchronization in disk arrays, in which an intent log comprising a list of addresses of pieces of data stored in a data write cache is generated. The pieces of data of the data write cache are written to a disk while the pieces of data are withdrawn from the data write cache. When power supply is interrupted during writing of the data to the disk, a processor supplies power to the disk to resume an operation of the disk, checks whether parity mismatch has occurred on the data of the disk corresponding to the data address list, and corrects a parity mismatch block using a parity block. When the consistency of data is damaged by unexpected power interruption, data being written is compared with a pre-stored intent log, shortening the time required for parity resynchronization. | 2014-07-03 |
20140189425 | LIBRARY CONTROLLER AND METHOD FOR CONTROLLING LIBRARY DEVICE - A library controller includes a data storage and a processor. The processor is configured to receive a plurality of data from a host device and write the received plurality of data to a first data buffer included in a first drive. The processor is configured to instruct, upon occurrence of a first write error, an operating unit to demount a recording medium from the first drive and mount the recording medium into a second drive. The processor is configured to receive unwritten data including the partial data from the first drive to store the received unwritten data in the data storage. The unwritten data is data stored in the first data buffer and not yet written to the recording medium. The processor is configured to read the unwritten data stored in the data storage to write the read unwritten data to a second data buffer included in the second drive. | 2014-07-03 |
20140189426 | APPARATUS AND METHOD FOR FAST FAILURE HANDLING OF INSTRUCTIONS - A processor is described comprising: instruction failure logic to perform a plurality of operations in response to a detected instruction execution failure, the instruction failure logic to be used for instructions which have complex failure modes and which are expected to have a failure frequency above a threshold, wherein the operations include: detecting an instruction execution failure and determining a reason for the failure; storing failure data in a destination register to indicate the failure and to specify details associated with the failure; and allowing application program code to read the failure data and responsively take one or more actions responsive to the failure, wherein the instruction failure logic performs its operations without invocation of an exception handler or switching to a low level domain on a system which employs hierarchical protection domains. | 2014-07-03 |
20140189427 | LIVE ERROR RECOVERY - A packet is identified at a port of a serial data link, and it is determined that the packet is associated with an error. Entry into an error recovery mode is initiated based on the determination that the packet is associated with the error. Entry into the error recovery mode can cause the serial data link to be forced down. In one aspect, forcing the data link down causes all subsequent inbound packets to be dropped and all pending outbound requests and completions to be aborted during the error recovery mode. | 2014-07-03 |
20140189428 | QUERYING AND REPAIRING DATA - Aspects of the subject matter described herein relate to querying and repairing data. In aspects, a component may detect that data on storage has become corrupted. In response, the component may request data from one or more redundant copies of the data and may determine which of the redundant copies, if any, are not corrupted. If a non-corrupted copy is found, the component may send a request that the corrupted data be repaired and may identify the non-corrupted copy to use to repair the corrupted data. | 2014-07-03 |
20140189429 | METHOD AND SYSTEM FOR IMPLEMENTING CONSISTENCY GROUPS WITH VIRTUAL MACHINES - Disclosed is an approach for implementing disaster recovery for virtual machines. Consistency groups are implemented for virtual machines, where the consistency group link together two or more VMs. The consistency group includes any set of VMs which need to be managed on a consistent basis in the event of a disaster recovery scenario. | 2014-07-03 |
20140189430 | SYSTEM, METHODS AND APPARATUS USING VIRTUAL APPLIANCES IN A SEMICONDUCTOR TEST ENVIRONMENT - In one embodiment, a semiconductor test control system includes a computer system having a plurality of hardware resources; a hypervisor installed on the computer system; and a test floor controller installed on the computer system. The hypervisor virtualizes the hardware resources and provides each of at least one virtual appliance with access to a respective virtual set of the hardware resources. Each virtual set of the hardware resources places its respective virtual appliance in controlling communication with at least a first aspect of a semiconductor test system, thereby enabling the respective virtual appliance to test a respective type of semiconductor device. The test floor controller is in controlling communication with i) at least a second aspect of the semiconductor test system, and ii) each of the at least one virtual appliance. | 2014-07-03 |
20140189431 | METHOD AND SYSTEM FOR MONITORING TRANSACTION EXECUTION ON A COMPUTER NETWORK AND COMPUTER STORAGE MEDIUM - A method and system for monitoring transaction execution on a computer network, and a computer storage medium are provided. The method for monitoring transaction execution on a computer network in accordance with an embodiment of the disclosure, including the steps of: acquiring monitoring data of a transaction executing on a computer network, and abstracting abnormal data from the monitoring data; acquiring an abnormal service based on the abnormal data; and locating a source of execution failure of the transaction in architecture layers of the transaction constructed on the computer network based on the abnormal service. | 2014-07-03 |
20140189432 | DATA RECOVERY USING A CLOUD-BASED REMOTE DATA RECOVERY CENTER - A Remote Metadata Center provides Distaster Recovery (DR) testing and metadata backup services to multiple business organizations. Metadata associated with local data backups performed at business organizations is transmitted to the Remote Metadata Center. Corresponding backup data is stored in a data storage system that is either stored locally at the business organization or at a data storage facility that is at a different location than the Remote Metadata Center and the business organization. DR testing can be staged from the Remote Data Center using the metadata received and optionally with assistance from an operator at the business organization and/or the data storage facility. | 2014-07-03 |
20140189433 | MEMORY SUBSYSTEM PERFORMANCE BASED ON IN-SYSTEM WEAK BIT DETECTION - A memory subsystem can test a memory device in situ, testing the performance of parameters of operation the device in the system it is built into during production. Thus, the system can detect the specific values that will work for one or more operating parameters for the memory device in actual runtime. A test component embedded in the memory subsystem can perform a stress test and identify specific bits or lines of memory that experience failure under one or more stresses. The system can then map out the failed bits or lines to prevent the bits/lines from being used in runtime of the system. | 2014-07-03 |
20140189434 | SYSTEM AND METHOD FOR ACHIEVING HIGH PERFORMANCE DATA FLOW AMONG USER SPACE PROCESSES IN STORAGE SYSTEMS - Fault isolation capabilities made available by user space can be provided for a embedded network storage system without sacrificing efficiency. By giving user space processes direct access to specific devices (e.g., network interface cards and storage adapters), processes in a user space can initiate Input/Output requests without issuing system calls (and entering kernel mode). The multiple user spaces processes can initiate requests serviced by a user space device driver by sharing a read-only address space that maps the entire physical memory one-to-one. In addition, a user space process can initiate communication with another user space process by use of transmit and receive queues similar to transmit and receiver queues used by hardware devices. And, a mechanism of ensuring that virtual addresses that work in one address space reference the same physical page in another address space is used. | 2014-07-03 |
20140189435 | System and method to extend the capabilities of a web browser of a web application issue root cause determination techniques - Disclosed is a system and method for extending the web application root cause determination functionality to a web browser. In one aspect, the present invention plots the network topology diagram for the web application by executing network trace commands. In another aspect, the present invention allows user to upload their web application network topology diagram. In another aspect, the present invention allows user to build their web application network topology diagram using UI Devices Toolkit. The present invention collects the information relating to the web application issue from various entities such as network infrastructure devices, servers through ICMP, SNMP, TRAP, SYS/APPLOG, HTTP and Network traffic analysis. In one aspect, the present invention highlights the entity in the web application network topology diagram based on the collected information and provides the experts recommended suggestion for the issue through Internet web search query. | 2014-07-03 |
20140189436 | FAULT DETECTION AND LOCALIZATION IN DATA CENTERS - Systems and Methods for detection and localization of performance faults in data centers are described. In one embodiment, a method comprises identifying a performance fault in a data center upon detection of the performance fault at any of a plurality of monitors in the data center, wherein the plurality of monitors are placed at monitor nodes, amongst a plurality of nodes, in the data center. Further, the method comprises evaluating a fault vector for the data center upon identification of the performance fault, wherein the fault vector is evaluated based on a fault indicator corresponding to each of the plurality of monitors. Based on the comparison of the fault vector with signatures of each of the plurality of nodes, one or ore faulty nodes, amongst the plurality of nodes in the data center, are determined as likely root cause of the performance fault. | 2014-07-03 |
20140189437 | Multi-Tier Trace - The disclosure relates to methods and systems for trace solutions in a computer processing system. More specifically, the disclosure relates to methods and systems for a multi-tier trace architecture. A method for separating raw trace data includes receiving raw trace data from one of more CPUs and/or busses in the system, separating the raw trace data into high bandwidth trace information (HBTI) and low bandwidth trace information (LBTI), recording the HBTI on an on-chip trace buffer until a specific event is triggered, and providing in parallel the LBTI over an off-chip trace interface. In one embodiment, the raw trace data are provided to a separate HBTI trace unit and a separate LBTI respectively. The HBTI trace unit processes the HBTI and generates a HBTI message, and the LBTI trace unit processes the LBTI and generates a LBTI message. | 2014-07-03 |
20140189438 | MEMORY LEAK DETECTION - In accordance with aspects of the disclosure, systems and methods are provided for monitoring one or more classes for detecting suspected memory leaks in a production environment. The systems and methods may include identifying which of the one or more classes hold at least one static or non-static field of collection or array type, accessing the one or more classes that hold the at least one static or non-static fields of collection or array type, and tracking a size for each field of each class by periodically sampling the size of each field over an interval, processing the size data for each field of each class, and detecting suspected memory leaks of each class by identifying which of the one or more fields of each class exhibits suspect behavior in the size over the interval. | 2014-07-03 |
20140189439 | BANKING OF RELIABILITY METRICS - In one embodiment, a processor includes at least one functional block and banking logic. The banking logic may be to determine an average reliability metric associated with the at least one functional block. The banking logic may also be to, if the average reliability metric exceeds a required level, implement a reduced reliability mode in the at least one functional block, where the reduced reliability mode is associated with a reduction in the average reliability metric. Other embodiments are described and claimed. | 2014-07-03 |
20140189440 | PREDICTING A TIME OF FAILURE OF A DEVICE - The present disclosure relates generally to the field of predicting a time of failure of a device. In various examples, predicting a time of failure of a device may be implemented in the form of methods and/or algorithms. | 2014-07-03 |
20140189441 | INFORMATION PROCESSING APPARATUS AND SERVER MANAGEMENT METHOD - An information processing apparatus includes an instruction unit and a calculation unit, and instructs a plurality of physical servers to start to provide or stop providing service. The calculation unit monitors the operating status of equipment that is installed in each of a plurality of chassis each housing one or a plurality of physical servers and that is used for operations of the physical servers. Then, the calculation unit calculates an equipment error probability indicating how likely the physical servers housed in a chassis are to fail to provide service due to an error in the equipment of the chassis. The instruction unit instructs physical servers to start to provide or stop providing the service, based on the equipment error probabilities of the plurality of chassis. | 2014-07-03 |
20140189442 | MESSAGE SERVICE DOWNTIME - The description relates to addressing the downtime of a message service. One example can include determining that an error occurred during a message send process. A decision can be made whether the error is a suspicious error or a non-suspicious error. In an instance where the error is a suspicious error, any resend attempts can be limited to a number of times defined by a crash count threshold. | 2014-07-03 |
20140189443 | HOP-BY-HOP ERROR DETECTION IN A SERVER SYSTEM - A server system performs error detection on a hop-by-hop basis at multiple compute nodes, thereby facilitating the detection of a compute node experiencing failure. The server system communicates a packet from an originating node (the originating node) to a destination node by separating the packet into multiple flow control digits (flits) and routing the flits using a series of hops over a set of intermediate nodes. The packet's final flit includes error detection information, such as checksum data. As each intermediate node receives the final flit, it performs error detection using the error detection information. The pattern of nodes that detect an error indicates which intermediate node has experienced a failure. | 2014-07-03 |
20140189444 | METHOD OF DETECTING AN ERROR OF A MULTI-TIME PROGRAMMABLE OPERATION, AND ORGANIC LIGHT EMITTING DISPLAY DEVICE EMPLOYING THE SAME - A method of detecting an error of a multi-time programmable (MTP) operation in which each gamma-offset and each header-bit at predetermined reference gray-levels are written in a MTP memory device while the MTP operation is performed on a pixel circuit, the each header-bit indicating whether or not the each gamma-offset is written in the MTP memory device, and it is detected whether or not the MTP operation is performed on the pixel circuit based on a logical operation between the header-bits at the predetermined reference gray-levels read from the MTP memory device when the MTP operation is finished on the pixel circuit. | 2014-07-03 |
20140189445 | SIGNALING SOFTWARE RECOVERABLE ERRORS - Embodiments of an invention for signaling software recoverable errors are disclosed. In one embodiment, a processor includes a first unit, a programmable indicator, and a second unit. The first unit is to detect a poison error. The programmable indicator is to indicate whether the poison error is signaled as a machine check error or as one of a fault and a system management interrupt. The second unit is to signal the poison error as one of a fault and a system management error responsive to the programmable indicator. | 2014-07-03 |