29th week of 2009 patent applcation highlights part 6 |
Patent application number | Title | Published |
20090179164 | CONTROL VALVE, AND CONTROL VALVE FOR VARIABLE DISPLACEMENT COMPRESSOR USING THE CONTROL VALVE - [PROBLEMS] To provide a small-sized control valve in which a pressure introduced into a pressure-sensitive part can control a valve opening according to the small change of thrust by a solenoid. | 2009-07-16 |
20090179165 | Automated water delivery systems with feedback control - A water delivery system includes a water input port, a control circuit, and a valve device. The water input port is constructed to be coupled to a water conduit receiving water from a remotely located water source. The valve device includes an actuator located near and connected to the water input port; wherein the valve device is constructed to receive control signals from the controller for providing water to a water delivery unit. The controller may be battery operated. The actuator may be a latching actuator, a non-latching actuator, or an isolated latching actuator. The controller may include a microcontroller coupled and to a sensor. The system may include a communication interface constructed and arranged to provide data to the microcontroller. The control circuit may include a power consumption controller. The control circuit includes a voltage regulator. | 2009-07-16 |
20090179166 | Electromagnetically Operatable Valve - An electromagnetically operatable valve, in particular a fuel injector for fuel injection systems of internal combustion engines, includes a magnetic circuit having a core, a solenoid, an armature, which operates a valve closing body cooperating with a fixed valve seat and is drawn against the core when the solenoid is excited, and is held on the valve closing body by a closing body carrier representing a part of a valve needle. The spherical valve closing body is secured on the closing body carrier in a non-positive manner due to the shape of the corresponding connecting surfaces. The valve is suitable in particular for use in fuel injection systems of mixture-compressing, externally ignited internal combustion engines. | 2009-07-16 |
20090179167 | Inflation/deflation adaptor assembly for inflating and deflating inflatable cargo dunnage bags - An inflation/deflation assembly, which can be mounted upon the inflation valve assembly of an inflatable bag, so as to permit both the inflation and deflation of the inflatable as may be desired. The inflation/deflation assembly comprises an outer housing, and a control rod is rotatably disposed within the housing so as to be rotatably movable between two positions angularly spaced apart from each other. When the control rod is disposed, for example, at a first one of the two positions, the inflatable bag can be inflated, whereas, when the control rod is disposed at the second one of the two positions, the inflatable bag can be deflated. | 2009-07-16 |
20090179168 | METHODS AND APPARATUS FOR ADJUSTING A SPRING LOAD IN AN ACTUATOR - Methods and apparatus for adjusting a spring load in an actuator are described. An example actuator includes a housing and a plate. Further, the example actuator includes one or more springs disposed in the housing to apply a force to the plate. Additionally, the example actuator includes a spring load adjuster having a collar extending through and movably engaged to the plate to enable an adjustment of the position of the collar relative to the plate to change a load provided by the one or more springs. | 2009-07-16 |
20090179169 | SEAL ASSEMBLY FOR USE WITH VALVES HAVING A TWO-PIECE CAGE - A seal assembly for use with valves having a two-piece cage is described. An example seal assembly includes a body defining a bore extending along an axis to slidably receive a closure member. The body includes a first portion removably coupled to a second portion. The first portion includes a first groove and the second portion includes a second groove. The first and second grooves form a sealing surface when the first portion couples to the second portion. The example seal assembly further includes at least one sealing member disposed adjacent the sealing surface to provide a seal against the closure member and a biasing element to bias the sealing member toward the sealing surface. | 2009-07-16 |
20090179170 | Semispherical Valve for Reciprocating Compressor and Pumps - A valve for inlet or outlet of gas and liquid for compressors and pumps comprises a semispherical seal element reciprocating between the stop surfaces and the opposed seating surface. A single spring engages the seal element to bias the seal element toward its seating surfaces. | 2009-07-16 |
20090179171 | CONTROL OF MATERIALS AND POROUS MAGNETIC PARTICLES - The present invention uses externally applied electromagnetic stimulus to control and heat porous magnetic particles and material associated with the particles. The particles contain magnetic material, such as superparamagnetic iron oxide and are associated with a material. Application of a DC magnetic field allows them to be moved with their associated material, and application of an AC RF electromagnetic field allows them to be heated with their associated material. The material can be associated with the particles by being contained in the pores of the particles, or in other cases the particles can adhere to the associated material, which can be an aqueous droplet. The present invention also provides a multi-layer porous magnetic particle. The particle includes a host layer having pores sized to accept magnetic nanoparticles. Magnetic nanoparticles are infused within pores of the host layer An encoding layer includes pores that define a spectral code. The pores in the encoding layer are sized to substantially exclude the magnetic nanoparticles. The encoding layer can also be a multi-layer, exhibiting, for example, a complex spectral code. | 2009-07-16 |
20090179172 | POLISHING COMPOSITION - To provide a polishing composition which can satisfy both suppression of the surface topography and a high stock removal rate, in a polishing step in the production of a wiring structure. | 2009-07-16 |
20090179173 | Water Softening Method - This invention relates to a method of water-softening using a water-softening product and products useful in such methods. The invention describes improved products and processes for their preparation wherein a water-softening composition is held between a water permeable water-insoluble web. | 2009-07-16 |
20090179174 | FLUORINE-CONTAINING CURABLE COMPOSITION - A fluorine-containing curable composition containing (A) A fluorine-containing amino compound having primary or secondary amino groups at both ends, said compound being represented by the formula (1): | 2009-07-16 |
20090179175 | METHOD FOR THE INDUSTRIAL USE OF TYROSOL AND HYDROXYTYROSOL CONTAINED IN THE SOLID BY- PRODUCTS OF INDUSTRIAL OLIVE CRUSHING - The invention relates to a method for using the natural biophenols, tyrosol and hydroxytyrosol, contained in the industrial by-products that result from the crushing and processing of olives, whether from three-phase or two-phase presses, and the husks and cakes thereof. The method produces a mixture of the two biophenols with a purity of more than 90% and yields of between 0.1 and 1.5% depending on the product and the processed raw material. The invention essentially comprises the selective extraction and fractionation of the resulting mixtures using solvents. | 2009-07-16 |
20090179176 | Fluorescent substance- or contrast medium-containing latex polymer particles, and a process to produce the same - This invention provides a method to effectively incorporate inorganic fluorescent substance or inorganic contrast medium into latex polymer particles which are used for diagnostic test or the like, and also provides thus produced fluorescent substance-containing latex polymer particles which show decreased non-specific adsorption of protein or the like. Said latex polymer particles are produced by making latex-forming monomer, macromer which has at least a hydrophilic polymer segment and an inorganic fluorescent substance or an inorganic contrast medium co-existent simultaneously in an aqueous medium, and subjecting them to a polymerization reaction. | 2009-07-16 |
20090179177 | HYDROGEN ODORANTS AND ODORANT SELECTION METHOD - The present invention provides a method for evaluating the properties of hydrogen to improve the safety of hydrogen fuel, and provides a method for selecting proper odorants for hydrogen. Odorized hydrogen containing suitable odorants in appropriate concentrations with hydrogen are also provided. | 2009-07-16 |
20090179178 | COMPOSITION AND METHOD FOR EXTENDING USEFUL LIFE OF INFLATED ARTICLES - A method for enhancing the useful life of inflated articles such as a pneumatic tire includes shipping a concentrate to the location of the tire, adding a diluent to the concentrate to form a composition, and introducing some or all of the composition into the inflation chamber of the tire. Concentrates and compositions, useful in this (and other) methods also are provided. | 2009-07-16 |
20090179179 | BIASABLE TRANSFER COMPOSITION AND MEMBER - The invention provides a conductivity control agent comprised of a polymeric material containing diphosphonium bis(sulfoarylcarbonyloxy) glycol salts as conductivity control agent. The conductivity control agents can be used with semi-conductive rolls, belts and other biasable members. The inclusion of the conductivity control agent in the polymeric or polyurethane elastomers extends the electrical life of the polymeric biasable member in low humidity environments. Additionally, the resistivity of the elastomeric polymer on the biasable member is controlled to a desirable value by adjusting the conductivity control agent level in the elastomers. | 2009-07-16 |
20090179180 | Curable Organopolysiloxane Composition and Semiconductor Device - A curable organopolysiloxane composition comprises at least the following components: an organopolysiloxane (A) represented by the following general formula: R | 2009-07-16 |
20090179181 | SILICON BASED COMPOSITE MATERIAL - A composite material having utility as an anode for lithium ion batteries comprises silicon, a transition metal, a ceramic and an electrically conductive diluent such as carbon. In particular instances, the ceramic is electrically conductive, and may comprise vanadium carbide or tungsten carbide. The transition metal may, in some instances, comprise iron. The material may be fabricated by grinding together a starting mixture of the components, and grinding may be accomplished in a high impact ball milling process, and the grinding step may cause partial alloying of the silicon with the metal and/or carbon. Further disclosed is a method for making the material as well as electrodes which incorporate the material. | 2009-07-16 |
20090179182 | Fencing for residential and commercial use - The fence provides for a plurality of wires that are twisted together in pairs at a plurality of spaced elongated windings and spread to form openings. The spaced elongated windings lie in spaced parallel lines extending longitudinally in the mesh fence. The fence also includes a plurality of spaced apart parallel wires, wherein each of the plurality of spaced apart parallel wires extend through the spaced elongated windings lying in a line. Ones of the plurality of spaced apart parallel wires are conductive wires that are coupled to a connector to supply electricity to at least one electrical device. | 2009-07-16 |
20090179193 | CARBON NANOTUBE BASED INTEGRATED SEMICONDUCTOR CIRCUIT - Gate electrodes are formed on a semiconducting carbon nanotube, followed by deposition and patterning of a hole-inducing material layer and an electron inducing material layer on the carbon nanotube according to the pattern of a one dimensional circuit layout. Electrical isolation may be provided by cutting a portion of the carbon nanotube, forming a reverse biased junction of a hole-induced region and an electron-induced region of the carbon nanotube, or electrically biasing a region through a dielectric layer between two device regions of the carbon nanotube. The carbon nanotubes may be arranged such that hole-inducing material layer and electron-inducing material layer may be assigned to each carbon nanotube to form periodic structures such as a static random access memory (SRAM) array. | 2009-07-16 |
20090179194 | ORGANIC THIN FILM TRANSISTORS - An organic thin film transistor has a gate dielectric layer which is formed from a block copolymer. The block copolymer comprises a polar block and a nonpolar block. The resulting dielectric layer has good adhesion to the gate electrode and good compatibility with the semiconducting layer. | 2009-07-16 |
20090179195 | Organic Luminescence Transistor Device and Manufacturing Method Thereof - The invention is an organic luminescence transistor device including: a substrate; an assistance electrode layer provided on a side of an upper surface of the substrate; an insulation film provided on a side of an upper surface of the assistance electrode layer; a first electrode provided locally on a side of an upper surface of the insulation film, the first electrode covering an area of a predetermined size; an electric-charge-injection inhibiting layer provided on an upper surface of the first electrode, the electric-charge-injection inhibiting layer having a shape larger than that of the first electrode in a plan view; an electric-charge injection layer provided on the side of an upper surface of the insulation film at an area not provided with the first electrode or the electric-charge-injection inhibiting layer and on an upper surface of the electric-charge-injection inhibiting layer; a luminescent layer provided on an upper surface of the electric-charge injection layer; and a second electrode layer provided on a side of an upper surface of the luminescent layer. | 2009-07-16 |
20090179196 | Pyrene-Based Organic Compound, Transistor Material and Light-Emitting Transistor Device - The object is to provide a light-emitting transistor material which is high in both luminescent property and mobility when used as a light-emitting transistor device. | 2009-07-16 |
20090179197 | DEVICE - A device is provided by use of a helical substituted polyacetylene. The device comprises a structure comprised of a helical substituted polyacetylene having a helical main chain, and a pair of electrodes for applying a voltage or electric current to the structure, wherein the molecule of the helical substituted polyacetylene has a length larger than the distance between the pair of the electrodes. | 2009-07-16 |
20090179198 | THIN FILM TRANSISTOR COMPRISING NOVEL CONDUCTOR AND DIELECTRIC COMPOSITIONS - The invention relates to thin film transistors comprising novel dielectric layers and novel electrodes comprising metal compositions that can be provided by a dry thermal transfer process. | 2009-07-16 |
20090179199 | FIELD EFFECT TRANSISTOR WITH AMORPHOUS OXIDE LAYER CONTAINING MICROCRYSTALS - A novel amorphous oxide applicable, for example, to an active layer of a TFT is provided. The amorphous oxide comprises microcrystals. | 2009-07-16 |
20090179200 | Semiconductor device - A self emission silicon emission display is provided at a low price, which contains silicon and oxygen which exist in abundance on the earth as the main component and which can be easily formed by conventional silicon process. A light emission element includes a first electrode for injecting electrons, a second electrode for injecting holes, and a light emission part electrically connected to the first electrode and the second electrode, where the light emission part includes amorphous or polycrystalline silicon consisting of a single layer or plural layers and where the dimension of the silicon in at least one direction is controlled to be several nanometers. | 2009-07-16 |
20090179201 | Laser Chalcogenide Phase Change Device - A laser activated phase change device for use in an integrated circuit comprises a chalcogenide fuse configured to connect a first patterned metal line and a second patterned metal line and positioned between an inter layer dielectric and an over fuse dielectric. The fuse interconnects active semiconductor elements manufactured on a substrate. A method for activating the laser activated phase change device includes selecting a laser condition of a laser based on characteristics of the fuse and programming a phase-change of the fuse with the laser by direct photon absorption until a threshold transition temperature is met. | 2009-07-16 |
20090179202 | THIN FILM TRANSISTOR ARRAY PANEL FOR A LIQUID CRYSTAL DISPLAY AND A METHOD FOR MANUFACTURING THE SAME - Simplified method of manufacturing liquid crystal displays. A gate wire including a gate line, a gate pad and a gate electrode is formed on the substrate by using the first mask. A gate insulating layer, a semiconductor layer, a ohmic contact layer and a metal layer are sequentially deposited to make a quadruple layers, and patterned by a dry etch of using the second mask. At this time, the quadruple layers is patterned to have a matrix of net shape layout and covering the gate wire. An opening exposing the substrate is formed in the display area and a contact hole exposing the gate pad is formed in the peripheral area. Next, ITO is deposited and a photoresist layer coated on the ITO. Then, the ITO layer is patterned by using the third mask and a dry etch, and the data conductor layer and the ohmic contact layer not covered by the ITO layer is dry etched. After depositing a passivation layer, a opening is formed by using the fourth mask and the exposed semiconductor layer through the opening is etched to separate the semiconductor layer under the adjacent data line. | 2009-07-16 |
20090179213 | PHOSPHOR COATING SYSTEMS AND METHODS FOR LIGHT EMITTING STRUCTURES AND PACKAGED LIGHT EMITTING DIODES INCLUDING PHOSPHOR COATING - Methods are disclosed including applying a layer of binder material onto an LED structure. A luminescent solution including an optical material suspended in a solution is atomized using a flow of pressurized gas, and the atomized luminescent solution is sprayed onto the LED structure including the layer of binder material using the flow of pressurized gas. | 2009-07-16 |
20090179214 | LIGHT EITTING DEVICE WITH MAGNETIC FIELD - A light emitting device with magnetic field includes a light-emitting structure and a first magnetic-source layer. The light-emitting structure includes a first doped structural layer, a second doped structural layer, an active layer between the two doped structural layers, a first electrode, and a second electrode. The first magnetic-source layer is integrated with the light-emitting structure to produce a magnetic field in the light-emitting structure. The magnetic field transversely shifts a driving current of the light-emitting structure to redistribute in the light-emitting structure. | 2009-07-16 |
20090179215 | Semiconductor light emitting device and fabrication method for the semiconductor light emitting device - A semiconductor light emitting device includes a first metal layer placed on the p-type semiconductor layer on the substrate, and includes a first pattern width W | 2009-07-16 |
20090179216 | LIGHT EITTING DEVICE WITH MAGNETIC FIELD - A light emitting device with magnetic field includes a light emitting device, a thermal conductive material layer and a magnetic layer. The thermal conductive material layer is coupled with the light emitting device to dissipate heat generated by the light emitting device. The magnetic layer is coupled with thermal conductive material layer to produce a magnetic filed on the light emitting device. | 2009-07-16 |
20090179217 | LIGHT-EMITTING DEVICE WITH MAGNETIC FIELD - A light-emitting device with magnetic-source includes a light emitting stack structure. The light emitting stack structure has a first electrode and a second electrode distributed at a light output side of the light emitting stack structure. A magnetic-source layer is engaged with the light emitting stack structure to provide a magnetic field to the light emitting stack structure in a substantially perpendicular direction to the light emitting stack structure. Alternatively, a method for improving light emitting performance of a light-emitting device includes applying a magnetic field to the light-emitting device at a direction substantially perpendicular to a light emitting area of the light-emitting device. | 2009-07-16 |
20090179218 | LIGHT EMITTING DEVICE PACKAGE - A light emitting device package including an light emitting device and at least one magnetic source is provided. The light emitting device includes a first doped type layer, a second doped type layer, and a light emitting layer. The light emitting layer is located between the first doped type layer and the second doped type layer. The magnetic source is disposed beside the light emitting device for applying a magnetic field to the light emitting device. | 2009-07-16 |
20090179219 | SIDE VIEW TYPE LED PACKAGE - In a side view type light emitting diode (LED) package, a lead frame portion and lead frame electrical contact portions are exposed outside a package body to serve as an additional heat dissipation path. The side view type LED package includes an LED chip, a package body having a side surface with an opening for receiving the LED chip, and lead frames for applying a current to the LED chip. The lead frames include inner leads electrically connected to the LED chip within the package body; electrical contact lower legs extending from the inner leads to a lower portion of the package body and exposed outside the package body in the vicinity of a lower surface of the package body perpendicular to the side surface; and a heat dissipation means extending, separately from the electrical contact lower legs, from at least one of the inner leads outside the package body. | 2009-07-16 |
20090179220 | SEMICONDUCTOR LIGHT-EMITTING DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR LIGHT-EMITTING DEVICE, AND LAMP - The present invention provides a semiconductor light-emitting device capable of effectively emitting ultraviolet light and a method of manufacturing the same. | 2009-07-16 |
20090179221 | SEMICONDUCTOR LIGHT EMITTING DEVICE - Provided is a semiconductor light emitting device. The semiconductor light emitting device comprises a first conductive type clad layer having a composition ratio of aluminum increased at a predetermined rate, an active layer on the first conductive type clad layer, and a second conductive type semiconductor layer on the active layer. | 2009-07-16 |
20090179222 | SILICON CONTROLLED RECTIFIER - A silicon controlled rectifier structure of polygonal layouts is provided. The polygonal first conductive type doped region is located in the middle of the polygonal second conductive type well. The first conductive type well shaped as a polygonal ring surrounds the second conductive type well and the second conductive type doped region is located within the first conductive type well and shaped as a polygonal ring concentric to the first conductive type well. | 2009-07-16 |
20090179233 | MICRO-ELECTRO-MECHANICAL SYSTEMS (MEMS) DEVICE - The present invention provides a MEMS device, be implemented on many MEMS device, such as MEMS microphone, MEMS speaker, MEMS accelerometer, MEMS gyroscope. The MEMS device includes a substrate. A dielectric structural layer is disposed over the substrate, wherein the dielectric structural layer has an opening to expose the substrate. A diaphragm layer is disposed over the dielectric structural layer, wherein the diaphragm layer covers the opening of the dielectric structural layer to form a chamber. A conductive electrode structure is adapted in the diaphragm layer and the substrate to store nonvolatile charges. | 2009-07-16 |
20090179234 | FIELD EFFECT TRANSISTOR - A field effect transistor having a T-gate ( | 2009-07-16 |
20090179235 | SEMICONDUCTOR DEVICE, DC/DC CONVERTER AND POWER SUPPLY - A semiconductor device in which the self-turn-on phenomenon is prevented that can significantly improve power conversion efficiency. The semiconductor device is a system-in-package for power supply applications in which a high-side switch, a low-side switch, and two drivers are included in a single package. The device includes an auxiliary switch disposed between the gate and source of said low-side switch, and a low-side MOSFET | 2009-07-16 |
20090179236 | Recess Etch for Epitaxial SiGe - A PMOS transistor and a method for fabricating a PMOS transistor. The method may include providing a semiconductor wafer having a PMOS transistor gate stack, source/drain extension regions, and active regions. The method may also include forming epi sidewalls, performing a ex-situ recess etch, and performing an in-situ recess etch. The ex-situ recess etch and the in-situ recess etch form recessed active regions. The PMOS transistor is formed by a method using ex-situ and in-situ etch and has epitaxial SiGe regions with a greatest width at the surface of the semiconductor wafer. | 2009-07-16 |
20090179237 | CMOS image sensor and method for fabricating the same - CMOS image sensor and method for fabricating the same, the CMOS image sensor including a second conductive type semiconductor substrate having an active region and a device isolation region defined therein, wherein the active region has a photodiode region and a transistor region defined therein, a device isolating film in the semiconductor substrate of the device isolation region, a first conductive type impurity region in the semiconductor substrate of the photodiode region, the first conductive type impurity region being spaced a distance from the device isolation film, and a second conductive type first impurity region in the semiconductor substrate between the first conductive type impurity region and the device isolation film, thereby reducing generation of a darkcurrent at an interface between the photodiode region and a field region. | 2009-07-16 |
20090179238 | Image pickup element performing image detection of high resolution and high image quality and image pickup apparatus including the same - In a pixel part, in a first active region, a photodiode and a transferring transistor are formed. In a second active region, a resetting transistor is formed. In a pixel part, in a first active region, a photodiode and a transferring transistor are formed. In a second active region, an amplifying transistor is formed. The first and second active regions are respectively the same in shape in image pixel parts. The resetting transistor and the amplifying transistor are shared by the pixel parts. | 2009-07-16 |
20090179239 | CMOS image sensors and methods of manufacturing the same - A complementary metal-oxide-semiconductor image sensor may include: a semiconductor substrate; a photodiode formed on a first portion of the semiconductor substrate; a transfer gate formed on the semiconductor substrate, near the photodiode, to transfer optical charges accumulated in the photodiode; a floating diffusion area formed on a second portion of the semiconductor substrate, on an opposite side of the transfer gate from the photodiode, to accommodate the optical charges; and/or a channel area formed under the transfer gate and contacting a side of the photodiode to transfer the optical charges. The transfer gate may be formed, at least in part, of transparent material. A method of manufacturing a complimentary metal-oxide-semiconductor image sensor may include: forming the photodiode; forming the floating diffusion area, separate from the photodiode; and/or forming the transfer gate, near the photodiode, to transfer optical charges accumulated in the photodiode. | 2009-07-16 |
20090179240 | DEVICE FOR DETECTING/STORING ELECTROMAGNETIC BEAMS, METHOD FOR MAKING SAME, AND USE THEREOF AND IMAGER INCORPORATING SAME - The invention concerns a device for detecting and storing electromagnetic beams, an imager incorporating same, a method for making said device and use thereof. The inventive device comprises a field-effect phototransistor including: two source and drain contact electrodes, an electrical conduction unit which is connected to the two contact electrodes and which is coated with a photosensitive polymeric coating capable of absorbing the beams, of detecting, of generating in response the loads detected by said unit and of storing said loads, and a gate electrode which is capable of controlling the electric current in the unit as well as spatially distributing the loads in said coating and which is separated from said unit by a gate dielectric. Said device is configured such that the conduction unit comprises at least one semiconductive nanotube or nanowire capable of supplying an electric signal representing a modification of the conductivity of the phototransistor having been exposed to a beam, and that the gate dielectric has a thickness and a permittivity ε, which satisfy ε | 2009-07-16 |
20090179241 | Photosensor and photo IC equipped with same - The present invention provides a photosensor formed in a semiconductor substrate having a silicon substrate, an insulating layer formed over the silicon substrate, and a silicon semiconductor layer formed over the insulating layer, comprising an ultraviolet photosensitive element formed in the silicon semiconductor layer, and at least one visible light photosensitive element formed in the silicon substrate. | 2009-07-16 |
20090179242 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - Embodiments relate to an image sensor. According to embodiments, an image sensor may include a metal interconnection and readout circuitry over a first substrate, a metal layer over the metal interconnection, and an image sensing device electrically connected to the metal layer. According to embodiments, an electric field may not be generated on and/or over an Si surface. This may contribute to a reduction in a dark current of a 3D integrated CMOS image sensor. | 2009-07-16 |
20090179253 | Oxide-nitride-oxide stack having multiple oxynitride layers - A semiconductor device including an oxide-nitride-oxide (ONO) structure having a multi-layer charge storing layer and methods of forming the same are provided. Generally, the method involves: (i) forming a first oxide layer of the ONO structure; (ii) forming a multi-layer charge storing layer comprising nitride on a surface of the first oxide layer; and (iii) forming a second oxide layer of the ONO structure on a surface of the multi-layer charge storing layer. Preferably, the charge storing layer comprises at least two silicon oxynitride layers having differing stoichiometric compositions of Oxygen, Nitrogen and/or Silicon. More preferably, the ONO structure is part of a silicon-oxide-nitride-oxide-silicon (SONOS) structure and the semiconductor device is a SONOS memory transistor. Other embodiments are also disclosed. | 2009-07-16 |
20090179254 | Memory Device With Improved Performance And Method Of Manufacturing Such A Memory Device - Non-volatile memory device on a semiconductor substrate, comprising a semiconductor base layer, a charge storage layer stack, and a control gate; the base layer comprising source and drain regions and a current-carrying channel region being positioned in between the source and drain regions; the charge storage layer stack comprising a first insulating layer, a charge trapping layer and a second insulating layer, the first insulating layer being positioned above the current-carrying channel region, the charge trapping layer being above the first insulating layer and the second insulating layer being above the charge trapping layer; the control gate being positioned above the charge storage layer stack; the charge storage layer stack being arranged for trapping charge in the charge trapping layer by direct tunneling of charge carriers from the current-carrying channel region through the first insulating layer, wherein the current-carrying channel region is a p-type channel for p-type charge carriers, and the material of at least one of the current-carrying channel region and/or the source and drain regions is in an elastically strained state. | 2009-07-16 |
20090179255 | Method for forming gate oxide of semiconductor device - The method for forming a triple gate oxide of a semiconductor device includes the steps of defining a first region, a second region and a third region, forming a first oxide film and forming a second oxide film on the first oxide film, blocking the first region and selectively removing portions the second oxide film and the first oxide film, forming a third oxide film on the semiconductor substrate, blocking the first region and the second region and selectively removing a portion of the third oxide film and forming a fourth oxide film on the semiconductor substrate and then forming a nitride film thereon, wherein a gate oxide having a triple structure is formed in the first region, a gate oxide having a double structure is formed in the second region and a gate oxide having a double structure is formed in the third region. | 2009-07-16 |
20090179256 | MEMORY HAVING SEPARATED CHARGE TRAP SPACERS AND METHOD OF FORMING THE SAME - A silicon-oxide-nitride-oxide-silicon (SONOS) memory and the corresponding forming method are disclosed. The memory includes a plurality of select gate structures arranged in an array, a plurality of charge trap spacers that do not contact each other, and a plurality of word lines. The word lines can directly contact the select gates' surfaces of the select gate structures. All of the select gate structures disposed in one line can share two charge trap spacers, and the two charge trap spacers are disposed on the opposed sidewalls of these select gate structures. | 2009-07-16 |
20090179257 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor memory device includes a first columnar semiconductor layer and a plurality of first conductive layers formed such that a charge storage layer for storing charges is sandwiched between the first conductive layers and the first columnar semiconductor layer. Also, the non-volatile semiconductor memory device includes a second columnar semiconductor layer and a second conductive layer formed such that an insulating layer is sandwiched between the second conductive layer and the second columnar semiconductor layer, the second conductive layer being repeatedly provided in a line form by providing a certain interval in a first direction perpendicular to a laminating direction. A first sidewall conductive layer being in contact with the second conductive layer and extending in the first direction is formed on a sidewall along a longitudinal direction of the second conductive layer. | 2009-07-16 |
20090179258 | NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device includes: a nitride semiconductor structure portion including a first layer made of an n-type group III nitride semiconductor, a second layer made of a group III nitride semiconductor containing a p-type impurity provided on the first layer and an n-type region formed on a part of the second layer, and having a wall surface extending over the first layer, a body region of the second layer other than the n-type region and the n-type region; a gate insulating film formed such that the gate insulating film is opposed to the body region on the wall surface; a gate electrode formed such that the gate electrode is opposed to the body region through the gate insulating film; a source electrode formed such that the source electrode is electrically connected to the n-type region; a drain electrode formed such that the drain electrode is electrically connected to the first layer; and a body electrode formed such that the body electrode is electrically connected to the body region. | 2009-07-16 |
20090179259 | SEMICONDUCTOR DEVICE WITH (110)-ORIENTED SILICON - A method of forming a semiconductor device on a heavily doped P-type (110) semiconductor layer over a metal substrate includes providing a first support substrate and forming a P-type heavily doped (110) silicon layer overlying the first support substrate. At least a top layer of the first support substrate is removable by a selective etching process with respect to the P-type heavily doped (110) silicon layer. A vertical semiconductor device structure is formed in and over the (110) silicon layer. The vertical device structure includes a top metal layer and is characterized by a current conduction in a <110> direction. The method includes bonding a second support substrate to the top metal layer and removing the first support substrate using a mechanical grinding and a selective etching process to expose a surface of the P-type heavily doped (110) silicon layer and to allow a metal layer to be formed on the surface | 2009-07-16 |
20090179260 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device, includes: forming a first and a second trench regions adjacent from each other in a first conductivity type semiconductor base; forming a second conductivity type semiconductor region in the semiconductor base between the first and second trench regions; forming a mask on the second conductivity type semiconductor region, the mask covering a central portion between the first and second trench regions; performing ion implantation of a first conductivity type impurity in the second conductivity type semiconductor region with the mask to form a first conductivity type first region and a first conductivity type second region separated from the first conductivity type first region; and performing heat treatment to diffuse the impurity in the first and second regions and to form a connection region between the first and second regions, connection region being shallower than the first and second regions after the heat treatment. | 2009-07-16 |
20090179261 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - Provided is a manufacturing method of a semiconductor device wherein the generation of voids is prevented in aluminum-based electrodes or the like. The method is suitable for manufacturing a semiconductor device adapted for vehicles, which is required to have a high reliability. However, it is very difficult that power semiconductor devices such as power MOSFETs, in particular, trench gate type power MOS devices are formed without having any void since the thickness of aluminum-based electrodes thereof is as large as about 3500 to 5500 nm (2.5 μm or more). In the present invention, a method is provided wherein at the time of forming an aluminum-based electrode metal film positioned over a wafer and having a thickness of 2.5 μm or more over a highland/lowland-repeated region in a line and space form by sputtering, the temperature of the wafer is set to 400° C. or higher and lower than 500° C. | 2009-07-16 |
20090179262 | Floating Body Memory Cell with a Non-Overlapping Gate Electrode - An integrated circuit includes a memory cell with a transistor. The transistor includes first and second doped portions, and a third portion disposed between the first and second doped portions. The first and the second doped portions and the third portion are disposed in a semiconductor substrate. The transistor further includes a gate electrode adjacent to the third portion, the gate electrode being insulated from the third portion. The gate electrode does not overlap at least one of the first and second doped portions, and a line connecting the first and the second portions extends substantially perpendicular to a surface of the substrate. | 2009-07-16 |
20090179273 | SEMICONDUCTOR DEVICE - A semiconductor device according to the present invention includes: a first region having a first conductive type; a plurality of second regions having a second conductive type that differs from the first conductive type, and formed to be arranged in the first region; a plurality of third regions having the first conductive type and formed in the second regions; an electrode forming a channel between the first region and the third region; and a plurality of extended second regions having the second conductive type, arranged in the first region such as to individually include one of the second regions and having an impurity density that is lower than an impunity density of the second regions. | 2009-07-16 |
20090179274 | Semiconductor Device and Method for Fabricating the Same - A semiconductor device and a method for fabricating the same is disclosed, in which one line is formed from a main gate to a sidewall gate, so that it is possible to scale a transistor below nano degree, and the semiconductor device includes a semiconductor substrate; a device isolation layer for dividing the semiconductor substrate into a field region and an active region; a main gate on a predetermined portion of the active region of the semiconductor substrate; a sidewall gate at both sides of the main gate on the semiconductor substrate; a main gate insulating layer between the main gate and the semiconductor substrate; a sidewall gate insulating layer between the sidewall gate and the semiconductor substrate; an insulating interlayer between the main gate and the sidewall gate; a first silicide layer on the surface of the main gate and the sidewall gate, to electrically connect the main gate with the sidewall gate; and source and drain regions at both sides of the sidewall gate in the active region of the semiconductor substrate. | 2009-07-16 |
20090179275 | SEMICONDUCTOR MEMORY DEVICE JUNCTION AND METHOD OF FORMING THE SAME - The present invention relates to semiconductor memory device junction and a method of forming the same. The semiconductor memory device junction may include a semiconductor substrate having gate lines formed thereon, and a junction having first and second junction elements formed by implanting impurities of a different mass into the semiconductor substrate between the gate lines. The method of forming a semiconductor memory device junction may include providing a semiconductor substrate having gate lines, forming an auxiliary layer along a surface of the semiconductor substrate including the gate lines, implanting impurities into the semiconductor substrate between gate lines to form a first junction element, and implanting impurities into the semiconductor substrate to form a second junction element, wherein the impurities implanted to form the first junction element and the second junction element have different masses. | 2009-07-16 |
20090179276 | Resistor Ballasted Transistors - A semiconductor chip comprises low voltage complementary metal oxide semiconductor (CMOS) sectors and high voltage lateral double diffused metal oxide semiconductor (LDMOS) sectors and at least one transistor within at least one of the low voltage CMOS sectors. The transistor has a semiconducting channel region within a substrate. A gate conductor is above the top layer of substrate, and the gate conductor is positioned above the channel region. A source/drain region is included in the substrate on a first side of the gate conductor and a lateral source/drain region is included in the substrate on a second side of the gate conductor opposite the first side. The lateral source/drain region is positioned a greater distance from the gate conductor than the source/drain region is positioned from the gate conductor. The embodiments herein also include a source/drain ballast resistor in the substrate between the lateral source/drain region and the gate conductor. | 2009-07-16 |
20090179277 | Semiconductor device and method for manufacturing the same - A semiconductor device according to the present invention includes: a semiconductor layer; an element separating portion, formed in a top layer portion of the semiconductor layer and separating, in the semiconductor layer, a first element forming region for forming a first conductive type MOSFET and a second element forming region for forming a second conductive type MOSFET; a first gate insulating film, selectively formed on a top surface of the semiconductor layer in the first element forming region; a first gate electrode, formed on the first gate insulating film; a first sidewall, formed at a periphery of the first gate insulating film and the first gate electrode; a second gate insulating film, selectively formed on a top surface of the semiconductor layer in the second element forming region; a second gate electrode, formed on the second gate insulating film; and a second sidewall, formed at a periphery of the second gate insulating film and the second gate electrode. The first sidewall includes: a base, contacting the top surface of the semiconductor layer; and a main body, formed on the base and protruding laterally beyond a peripheral edge of the base. | 2009-07-16 |
20090179278 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - In a p-type MOS transistor, a gate electrode is partially removed by a predetermined wet etching, so that an upper portion of the gate electrode is formed to be lower than an upper portion of a sidewall insulation film. As a result of such a constitution, in spite of formation of a tensile stress (TSEL) film leading to deterioration of characteristics of a p-type MOS transistor by nature, stresses applied from the TESL film to the gate electrode and the sidewall insulation film are dispersed as indicated by broken arrows in the drawing, and consequently, a compressive stress is applied to a channel region, so that a compressive strain is introduced. As stated above, in the p-type MOS transistor, in spite of formation of the TESL film, in reality, a strain to improve characteristics of the p-type MOS transistor is given to the channel region. | 2009-07-16 |
20090179279 | METAL GATE ELECTRODE STABILIZATION BY ALLOYING - Stabilized metal gate electrode for complementary metal-oxide-semiconductor (“CMOS”) applications and methods of making the stabilized metal gate electrodes are disclosed. Specifically, the metal gate electrodes are stabilized by alloying wherein the alloy comprises a metal selected from the group consisting of Re, Ru, Pt, Rh, Ni, Al and combinations thereof and an element selected from the group consisting of W, V, Ti, Ta and combinations thereof. | 2009-07-16 |
20090179280 | HIGH THRESHOLD NMOS SOURCE-DRAIN FORMATION WITH As, P AND C TO REDUCE DAMAGE - Pipe defects in n-type lightly doped drain (NLDD) regions and n-type source/drain (NDS) regions are associated with arsenic implants, while excess diffusion in NLDD and NSD regions is mainly due to phosphorus interstitial movement. Carbon implanatation is commonly used to reduce phosphorus diffusion in the NLDD, but contributes to gated diode leakage (GDL). In high threshold NMOS transistors GDL is commonly a dominant off-state leakage mechanism. This invention provides a method of forming an NMOS transistor in which no carbon is implanted into the NLDD, and the NSD is formed by a pre-amorphizing implant (PAI), a phosphorus implant and a carbon species implant. Use of carbon in the NDS allows a higher concentration of phosphorus, resulting in reduced series resistance and reduced pipe defects. An NMOS transistor with less than 1·10 | 2009-07-16 |
20090179281 | Schottky barrier source/drain N-MOSFET using ytterbium silicide - An N-type Schottky barrier Source/Drain Transistor (N-SSDT) that uses ytterbium silicide (YbSi | 2009-07-16 |
20090179282 | METAL GATE DEVICE WITH REDUCED OXIDATION OF A HIGH-K GATE DIELECTRIC - Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer and reduced oxidation of a substrate beneath the high-k gate dielectric layer. An oxygen barrier, or capping, layer on the high-k gate dielectric layer and metal gate may prevent such oxidation during processes such as spacer formation and annealing of ion implanted regions. | 2009-07-16 |
20090179303 | Vertical Bipolar Transistor - A vertical heterobipolar transistor comprising a substrate of semiconductor material of a first conductivity type and an insulation region provided therein, a first semiconductor electrode arranged in an opening of the insulation region and comprising monocrystalline semiconductor material of a second conductivity type, which is either in the form of a collector or an emitter, and which has a first heightwise portion and an adjoining second heightwise portion which is further away from the substrate interior in a heightwise direction, wherein only the first heightwise portion is enclosed by the insulation region in lateral directions perpendicular to the heightwise direction, a second semiconductor electrode of semiconductor material of the second conductivity type, which is in the form of the other type of semiconductor electrode, a base of monocrystalline semiconductor material of the first conductivity type, and a base connection region having a monocrystalline portion which in a lateral direction laterally surrounds the second heightwise portion, which is further towards the substrate interior as viewed from the base, of the first semiconductor electrode, and which rests with its underside directly on the insulation region. | 2009-07-16 |
20090179304 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In the manufacture of semiconductor devices, cracking of a resin member caused during cutting and defects in the external appearance are prevented. | 2009-07-16 |
20090179305 | SUBSTRATE AND MANUFACTURING METHOD OF THE SAME - According to the present invention, on a double-sided substrate | 2009-07-16 |
20090179306 | ADVANCED LOW k CAP FILM FORMATION PROCESS FOR NANO ELECTRONIC DEVICES - A carbon-rich silicon carbide-like dielectric film having a carbon concentration of greater than, or equal to, about 30 atomic % C and a dielectric constant of less than, or equal to, about 4.5 is provided. In some embodiments, the dielectric film may optionally include nitrogen. When nitrogen is present, the carbon-rich silicon carbide-like dielectric film has a concentration nitrogen that is less than, or equal, to about 5 atomic % nitrogen. The carbon-rich silicon carbide-like dielectric film can be used as a dielectric cap layer in an interconnect structure. The inventive dielectric film is highly robust to UV curing and remains compressively stressed after UV curing. Moreover, the inventive dielectric film has good oxidation resistance and prevents metal diffusion into an interconnect dielectric layer. The present invention also provides an interconnect structure including the inventive dielectric film as a dielectric cap. A method of fabricating the inventive dielectric film is also provided. | 2009-07-16 |
20090179307 | INTEGRATED CIRCUIT SYSTEM EMPLOYING FEED-FORWARD CONTROL - An integrated circuit system that includes: providing a substrate and a material layer; measuring a parameter of the material layer; and correlating the thickness of an anti-reflective layer to the measured parameter of the material layer for critical dimension control. | 2009-07-16 |
20090179308 | Method of Manufacturing a Semiconductor Device - According to one embodiment of the present invention, a method of manufacturing a semiconductor device is provided. The method includes: forming a semiconductor structure; forming a stress liner over the semiconductor structure; and changing the stress properties of at least a part of the stress liner. | 2009-07-16 |
20090179309 | Power semiconductor component with trench- type second contact region - A power semiconductor component and method for producing it. The component has a semiconductor base body with a first doping and a pn junction formed by a contact region having a second doping with a doping profile in the base body. The second contact region is arranged at a second surface of the base body and extends into the base body. The base body has a trench-type cutout with an edge area and a base area, wherein the base area is formed as a second partial area of the second surface, and wherein the second contact region extends from the base area via the edge area as far as a first partial area. Furthermore, the pn junction has a curvature adjacent to the edge area. | 2009-07-16 |
20090179310 | Pillar devices and methods of making thereof - A method of making a semiconductor device includes providing an insulating layer containing a plurality of openings, forming a first semiconductor layer in the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the first semiconductor layer, such that first conductivity type second portions of the first semiconductor layer remain in lower portions of the plurality of openings in the insulating layer, and upper portions of the plurality of openings in the insulating layer remain unfilled. The method also includes forming a second semiconductor layer in the upper portions of the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the second semiconductor layer located over the insulating layer. The second conductivity type second portions of the second semiconductor layer remain in upper portions of the plurality of openings in the insulating layer to form a plurality of pillar shaped diodes in the plurality of openings. | 2009-07-16 |
20090179311 | SEMICONDUCTOR COMPONENT AND METHOD FOR PRODUCING THE SAME - A semiconductor component of semiconductor chip size includes a semiconductor chip. The semiconductor chip has a metallic coating that completely covers the side edges, the rear side and the top side, on which surface-mountable external contacts are arranged. One embodiment includes power semiconductor components, wherein the metallic coating connects a rear side electrode to one of the surface-mountable external contacts on the top side of a power semiconductor chip. | 2009-07-16 |
20090179312 | INTEGRATED CIRCUIT PACKAGE-ON-PACKAGE STACKING SYSTEM - An integrated circuit package-on-package stacking method includes forming a leadframe interposer including: forming a leadframe having a lead; forming a molded base only supporting the lead; and singulating the leadframe interposer from the leadframe. | 2009-07-16 |
20090179313 | FLEX CLIP CONNECTOR FOR SEMICONDUCTOR DEVICE - A semiconductor die package. The semiconductor die package includes a semiconductor die having a first surface comprising a die contact region, and a second surface. It also includes a leadframe structure having a die attach pad and a lead structure, where the semiconductor die is attached to the die attach pad. It also includes a flex clip connector comprising a flexible insulator, a first electrical contact region, and a second electrical contact region. The first electrical contact region of the flex clip connector is coupled to the die contact region and the second electrical contact region of the flex clip connector is coupled to the lead structure. | 2009-07-16 |
20090179314 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LEADFINGER SUPPORT - An integrated circuit package system including forming a leadframe having a lead with a leadfinger support of a predetermined height, and attaching an integrated circuit die with an electrical interconnect at a predetermined collapse height determined by the predetermined height of the leadfinger support. | 2009-07-16 |
20090179315 | Semiconductor Die Packages Having Solder-free Connections, Systems Using the Same, and Methods of Making the Same - Disclosed are spring structures that provide solderless electrical connections in semiconductor die packages. An exemplary spring structure comprises a first portion adapted to make an electrical connection to a conductive region of a semiconductor die, a second portion adapted to make an electrical connection to a conductive region of a leadframe, and a third portion disposed between the first and second portions. During a molding process, the third portion is compressively strained to impart forces to the first and second portions that maintain these portions in contact with the conductive regions of the die and leadframe. After the molding material sets, the third portion remains in a state of compressive strain, and imparts forces on the first and second portions that maintain the electrical connections. The spring structure may be made of less expensive materials, and does not require cleaning, fluxing, or reflowing, thereby reducing manufacturing cost and time. | 2009-07-16 |
20090179316 | FLEXIBLE SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A flexible semiconductor device and a fabrication method thereof are disclosed. The method includes the steps of providing a CMOS (complementary metal-oxide semiconductor) chip having a silicon substrate, wherein an IC (integrated circuit) is formed on the silicon substrate; mounting the chip on a carrier board via the IC-laden side of the chip, wherein the IC-laden side of the chip is in contact with the carrier board; thinning the silicon substrate; forming a resilient plastic layer made of PDMS (polydimethylsiloxane) on the thinned silicon substrate; and removing the carrier board. The chip is flexible enough to expose testing pads on the front of the chip so as to facilitate wire bonding and probing. The resilient plastic layer enables uniform distribution of stress exerted on the chip and thereby guards the chip from cracking. | 2009-07-16 |
20090179317 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - It is made possible to restrict warpage at the time of resin cure and achieve a smaller thickness. A semiconductor device includes: a first chip including a MEMS device and a first pad formed on an upper face of the MEMS device, the first pad being electrically connected to the MEMS device; a second chip including a semiconductor device and a second pad formed on an upper face of the semiconductor device, the second pad being electrically connected to the semiconductor device; and an adhesive portion having a stacked structure, and bonding a side face of the first chip and a side face of the second chip, the stacked structure including a first adhesive film formed by adding a first material constant modifier to a first resin, and a second adhesive film formed by adding a second material constant modifier to a second resin. | 2009-07-16 |
20090179318 | MULTI-CHANNEL STACKABLE SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME, AND STACKING SUBSTRATE APPLIED TO THE SEMICONDUCTOR DEVICE - A multi-channel stackable semiconductor device and a method for fabricating the same, and a stacking substrate applied to the semiconductor device are provided. A plurality of stacking substrates and package members having known good dies are provided. Each stacking substrate includes a first surface, an opposite second surface, a plurality of electrical bond pads and ball pads formed on the first surface, and a plurality of electrical terminals formed on the second surface. The ball pads are electrically connected to the electrical terminals by conductive structures formed in the stacking substrate. A plurality of corresponding connection paths are provided between at least one of the electrical bond pads and at least some of the ball pads, so as to allow each of the electrical bond pads to be selectively electrically connected to the ball pads. A package member is mounted on and electrically connected to each stacking substrate. | 2009-07-16 |
20090179319 | STACKED SEMICONDUCTOR PACKAGE ASSEMBLY HAVING HOLLOWED SUBSTRATE - A stackable package substrate has an opening shaped and dimensioned to accommodate but not contact a mold cap of a package upon which the stackable package is to be mounted. On the die attach surface, the frame substrate accommodates a die attach margin adjacent at the edge of the opening; and a row of wire bond sites arranged along at an outer frame edge, for electrical interconnection. The frame substrate accommodates z-interconnect ball pads arranged to align with corresponding z-interconnect pads on the substrate of a package. A stackable package has a frame substrate. A stacked package assembly includes a second package mounted on a first package using peripheral solder ball z-interconnect, in which the first package includes a die enclosed by a mold cap and in which the second package includes one die mounted on the frame substrate. | 2009-07-16 |
20090179320 | INTEGRATED CIRCUIT INCORPORATING WIRE BOND INDUCTANCE - The invention relates to the field of electronics, more particularly to the wire bonds incorporated into an integrated circuit package such as a quad flat pack, a ball grid array or hybrid style module. The present invention takes the normally undesirable wire bond inductance and uses it in an operational circuit where positive inductance is required. The circuit in which the wire bond inductance is used is located primarily in the integrated circuit die housed in the integrated circuit package, but may also include off-die components. In one example, a wire bond is used as the required series inductance in a discrete circuit impedance inverter which consists of two shunt-to-ground negative inductances and one series positive inductance. One of the negative inductances is located on-die, while the other is located off-die. | 2009-07-16 |
20090179321 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device, having a first semiconductor region, and a second semiconductor region; mounted with a first electrode pad on a semiconductor substrate main surface at the inside surrounded by the third semiconductor region, mounted in the second semiconductor region, and a multilayer substrate having first and second wiring layers, to take out an electrode of the semiconductor chip; joining the first wiring layer part for the first electrode, mounted on the multilayer substrate, in a region opposing to the semiconductor substrate main surface at the inside surrounded by the third semiconductor region, and the first electrode pad, by a conductive material; joining the first wiring layer part for the first electrode, and the second wiring layer at a conductive part; and extending the second wiring layer to the outside of a region opposing the semiconductor substrate main surface at the inside surrounded by the third semiconductor region. | 2009-07-16 |
20090179322 | ELECTRONIC PACKAGE METHOD AND STRUCTURE WITH CURE-MELT HIERARCHY - Disclosed herein are embodiments of electronic package incorporating a thermal interface material (e.g., a metal TIM) that is positioned between a lid and a chip on a substrate. The TIM has a predetermined (i.e., repeatable) minimum thickness and is further registered to the top surface of the chip (i.e., the TIM has an essentially symmetric shape and does not extend vertically along the sidewalls of the chip). Also, disclosed herein are embodiments of a method of forming such an electronic package that uses a hierarchical heating process that cures a lid sealant, thereby securing the lid to the substrate, and then reflows (i.e., melts and cools) the TIM, thereby adhering the TIM to both the chip and lid. This hierarchical heating process ensures that the TIM has the above-mentioned characteristics (i.e., a predetermined minimum thickness and registration to the top surface of the chip) and further provides robust process windows for high-yield, low-cost electronic package manufacturing. | 2009-07-16 |
20090179333 | SOLDER CONTACTS AND METHODS OF FORMING SAME - An integrated circuit that comprises a substrate and a structured layer on the substrate. The structured layer comprises an opening to the substrate, a first field and a second field on the substrate, wherein the first field and the second field, at least in part, overlap with the opening. The integrated circuit further comprises a first material in the area of the first field and a second material in the area of the second field. The first material impedes a wetting by a solder material, and the second provides a wetting by the solder material. | 2009-07-16 |
20090179334 | APPARATUS FOR FACILITATING PROXIMITY COMMUNICATION BETWEEN CHIPS - One embodiment of the present invention provides a system for facilitating proximity communication between semiconductor chips. The system includes a base chip and a bridge chip, each of which includes an active face upon which active circuitry and signal pads reside, and a back face opposite the active face. The active face of the bridge chip is bonded to the active face of the base chip. Then, an identified portion of the active face of the bridge chip is thinned via etching and is removed by planarizing the back face of the bridge chip, thereby creating an opening in the bridge chip that exposes a portion of the active face of the base chip. | 2009-07-16 |
20090179335 | PRINTED CIRCUIT BOARD AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - A printed circuit board (PCB) and a semiconductor package that are configured to prevent delamination and voids. In one example embodiment, the semiconductor package includes a PCB having a base substrate on which conductive patterns are formed and which includes an interior region having a die paddle for receiving a semiconductor chip and an exterior region disposed outside the interior region. The PCB also includes a first solder resist formed on a portion of the base substrate corresponding to the interior region and a second solder resist formed on a portion of the base substrate corresponding to the exterior region. The second solder resist may also have a greater surface roughness than the surface roughness of the first solder resist. | 2009-07-16 |
20090179336 | Electronic Module and a Method of Assembling Such a Module - The module is of the type comprising an electronic component provided with a conductive face that is electrically connected to a connection member of the component by means of a conductor that is corrugated at least in part so as to define an alternating sequence of oppositely-directed arcs, a first series of arcs being connected to the conductive face of the electronic component. The conductor also includes a second series of arcs opposite to the arcs of the first series and interposed between the arcs of the first series, the second series of arcs being connected to the conductive face of the connection member. | 2009-07-16 |
20090179337 | Quick-attach steam dispersion tubes and method of attachment - A steam dispersion system is disclosed. The steam dispersion system includes a header and a mounting plate spaced from the header. A steam dispersion tube including a first end and a second end and an interior cavity defined between the first end and the second end is mounted between the mounting plate and the header. The steam dispersion tube defines a longitudinal axis. A biasing structure is mounted between the mounting plate and the header, wherein the biasing structure applies a biasing force on the steam dispersion tube along a direction parallel to the longitudinal axis of the steam dispersion tube when mounted between the header and the mounting plate. | 2009-07-16 |
20090179338 | ACTIVE WEATHER STATION SYSTEM - An active weather system includes a main weather station unit, a humidifier unit and a remote sensor. The main weather station unit has a main housing with a humidity sensor that detects a level of humidity in an area surrounding the main weather station unit. The humidifier unit includes a housing with a nest for removably mounting the main housing. The humidifier unit also includes a water tank and a humidifier. The humidifier vaporizes water from the water tank when the humidity sensor detects a level of humidity lower than a preset level. Electrical contacts in the nest of the humidifier housing and the main weather station electrically connect the units when the main housing is mounted in the nest. The remote sensor may be placed away from the main unit, such as outdoors, to sense temperature and/or humidity in its environment. The remote sensor includes a transmitter, which sends the temperature and/or humidity information it detects to the main weather station unit. | 2009-07-16 |
20090179339 | Lens molding gasket - A lens molding gasket comprising one integral membrane serving as a mold shell, and a seating for a removable mold shell. | 2009-07-16 |
20090179340 | Lens molds with coating - The present invention generally relates to a contact lens forming mold and to a method of producing contact lenses with higher production yield and improved quality. By coating a contact lens forming mold with a nano-structured fluorine-containing inorganic polycondensate coating solution the number of lens holes, such as voids or areas of non uniform thickness of a contact lens therein produced is substantially decreased. | 2009-07-16 |
20090179341 | SONICATION METHODS FOR SCREENING AND PREPARING SOLID FORMS - Methods for screening and preparing solid forms are described herein. Such methods comprise sonicating a solid paste to provide a sonicated paste. The sonicated paste may be analyzed for the presence of solid forms. | 2009-07-16 |
20090179342 | Process for In-molding Labels onto Plastic During a Hybrid Thermoforming-injection Molding Process - A hybrid thermoform-injection molding process for fusing labels during the molding process onto plastic parts having multiple contours and/or holes, different wall thickness and depths is presented. In the preferred embodiment, a label made of the same material as the plastic piece to which it is to be applied is fixed into a shape corresponding to that of the final desired shape through thermoforming. The label is then placed into a second mold where it is fused to plastic in an injection molding process to form a final product. | 2009-07-16 |
20090179353 | Method of manufacturing a three-dimensional object - A method of manufacturing a three-dimensional object is provided, in which the object is solidified layer by layer by solidifying a building material by means of a beam of a gas laser at locations in each layer corresponding to the cross section of the object, wherein the power of the laser is measured and the power of the laser is controlled according to the measured value, characterized in that the power measurement takes place in a time window, in which a change of the power occurs, and an input control signal of the laser is controlled according to the measured values. | 2009-07-16 |