29th week of 2013 patent applcation highlights part 13 |
Patent application number | Title | Published |
20130181223 | ELECTRIC CIRCUIT - A transistor has variation in a threshold voltage or mobility due to accumulation of factors such as variation in a gate insulating film which is caused by a difference of a manufacturing process or a substrate to be used and variation in a crystal state of a channel formation region. The present invention provides an electric circuit which is arranged such that both electrodes of a capacitance device can hold a voltage between the gate and the source of a specific transistor. Further, the present invention provides an electric circuit which has a function capable of setting a potential difference between both electrodes of a capacitance device so as to be a threshold voltage of a specific transistor. | 2013-07-18 |
20130181224 | SEMICONDUCTOR STRUCTURE - A semiconductor structure includes a barrier layer, a spacer structure, and a channel layer. The barrier layer includes a group III nitride. The spacer structure includes first and second aluminum nitride layers and an intermediate layer. The intermediate layer includes a group III nitride and is between the first and second aluminum nitride layers. The intermediate layer has a first free charge carrier density at an interface with the second aluminum nitride layer. The spacer structure is between the barrier layer and the channel layer. The channel layer includes a group III nitride and has a second free charge carrier density at an interface with the first aluminum nitride layer of the spacer structure. The first aluminum nitride layer, the intermediate layer, and the second aluminum nitride layer have layer thicknesses so the first free charge carrier density is less than 10% of the second free charge carrier density. | 2013-07-18 |
20130181225 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a metal substrate including a metal base plate, an insulating sheet located on the metal base plate, and a wiring pattern located on the insulating sheet, and a semiconductor element located on the metal substrate. The semiconductor element is sealed with a molding resin. The molding resin extends to side surfaces of the metal substrate. On the side surfaces of the metal substrate, the insulating sheet and the wiring pattern are not exposed from the molding resin, whereas the metal base plate includes a projecting portion exposed from the molding resin. | 2013-07-18 |
20130181226 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - There are provided a semiconductor device in which a drain leak current can be reduced in the transistor operation while high vertical breakdown voltage is achieved and a method for producing the semiconductor device. In the semiconductor device, an opening | 2013-07-18 |
20130181227 | LED Package with Slanting Structure and Method of the Same - The LED package comprises a substrate with a first conductive type through-hole and a second conductive type through-hole through the substrate; a reflective layer formed on an upper surface of the substrate; a LED die having first conductive type pad and second conductive type pad, wherein the first conductive type pad is aligned with the first conductive type through-hole; a slanting structure of dielectric layer formed adjacent at least one side of the LED die for carrying conductive traces; a conductive trace formed on upper surface of the slanting structure to offer path between the second conductive type pad and the conductive type through-hole; and a refilling material within the first conductive type through-hole and second conductive type through-hole. | 2013-07-18 |
20130181228 | POWER SEMICONDUCTOR MODULE AND METHOD OF MANUFACTURING THE SAME - First chip main surfaces of first semiconductor chips are bonded to a heat spreader, and second chip main surfaces of the first semiconductor chips are bonded to a first electrode. First chip main surfaces of second semiconductor chips are bonded to a heat spreader, and second chip main surfaces of the second semiconductor chips are bonded to a first electrode. A plurality of electrodes are provided by a lead frame. An insulating member is provided on a side opposite to the chips when viewed from the heat spreader. An insulating substrate is provided on a side opposite to the chips when viewed from the first electrodes. | 2013-07-18 |
20130181229 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A MOSFET includes: a substrate having a first trench formed therein, the first trench opening on a side of one main surface; a gate insulating film; and a gate electrode. The substrate includes an n type source region, a p type body region, an n type drift region, and a p type deep region making contact with the body region and extending to a region deeper than the first trench. The first trench is formed such that a distance between the wall surface and the deep region increases with increasing distance from the main surface of the substrate. | 2013-07-18 |
20130181230 | SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR SUBSTRATE MANUFACTURING METHOD - A semiconductor substrate includes: a silicon substrate; a monocrystalline silicon carbide film formed on a surface of the silicon substrate; and a stress relieving film formed on the surface of the silicon substrate opposite from the side on which the monocrystalline silicon carbide film is formed, and that relieves stress in the silicon substrate by applying compressional stress to the silicon substrate surface on which the stress relieving film is formed, wherein a plurality of spaces is present in the monocrystalline silicon carbide film in portions on the side of the silicon substrate and along the interface between the monocrystalline silicon carbide film and the silicon substrate. | 2013-07-18 |
20130181231 | MICROPIPE-FREE SILICON CARBIDE AND RELATED METHOD OF MANUFACTURE - Micropipe-free, single crystal, silicon carbide (SiC) and related methods of manufacture are disclosed. The SiC is grown by placing a source material and seed material on a seed holder in a reaction crucible of the sublimation system, wherein constituent components of the sublimation system including the source material, reaction crucible, and seed holder are substantially free from unintentional impurities. By controlling growth temperature, growth pressure, SiC sublimation flux and composition, and a temperature gradient between the source material and the seed material or the SiC crystal growing on the seed material during the PVT process, micropipe-inducing process instabilities are eliminated and micropipe-free SiC crystal is grown on the seed material. | 2013-07-18 |
20130181232 | Optocoupler with Surface Functional Coating Layer - Various embodiments of methods and devices are provided for an optocoupler comprising an optically reflective compound comprising silicone and inner and outer surfaces. A molding compound surrounds and encapsulates at least portions of the outer surfaces of the optically reflective compound to form an enclosure. A surface functional coating layer is provided in the optically reflective compound to promote adhesion and increase breakdown voltages between inner walls of the enclosure and the outer surfaces of the optically reflective compound. | 2013-07-18 |
20130181233 | SILICON PHOTONICS WAFER USING STANDARD SILICON-ON-INSULATOR PROCESSES THROUGH SUBSTRATE REMOVAL OR TRANSFER - Processing for a silicon photonics wafer is provided. A silicon photonics wafer that includes an active silicon photonics layer, a thin buried oxide layer, and a silicon substrate is received. The thin buried oxide layer is located between the active silicon photonics layer and the silicon substrate. An electrical CMOS wafer that includes an active electrical layer is also received. The active silicon photonics layer of the silicon photonics wafer is flip chip bonded to the active electrical layer of the electrical CMOS wafer. The silicon substrate is removed exposing a backside surface of the thin buried oxide layer. A low-optical refractive index backing wafer is added to the exposed backside surface of the thin buried oxide layer. The low-optical refractive index backing wafer is a glass substrate or silicon substrate wafer. The silicon substrate wafer includes a thick oxide layer that is attached to the thin buried oxide layer. | 2013-07-18 |
20130181234 | LIGHTING DEVICES WITH PRESCRIBED COLOUR EMISSION - Optical conversion layers based on semiconductor nanoparticles for use in lighting devices, and lighting devices including same. In various embodiments, spherical core/shell seeded nanoparticles (SNPs) or nanorod seeded nanoparticles (RSNPs) are used to form conversion layers with superior combinations of high optical density (OD), low re-absorbance and small FRET. In some embodiments, the SNPs or RSNPs form conversion layers without a host matrix. In some embodiments, the SNPs or RSNPs are embedded in a host matrix such as polymers or silicone. The conversion layers can be made extremely thin, while exhibiting the superior combinations of optical properties. Lighting devices including SNP or RSNP-based conversion layers exhibit energetically efficient superior prescribed colour emission | 2013-07-18 |
20130181235 | Organic Light-Emitting Display Device and Method of Manufacturing the Same - In an organic light-emitting display device and a method of manufacturing the same, the organic light-emitting display device includes: a substrate; an organic light-emitting unit that includes a plurality of organic light-emitting devices formed on the substrate; and an encapsulation unit that seals the organic light-emitting unit. The encapsulation unit includes: a barrier layer and a planarization layer that are stacked on the organic light-emitting unit; and a cover layer that is disposed between the barrier layer and the planarization layer to cover a crack occurring in each of the organic light-emitting devices. | 2013-07-18 |
20130181236 | LIGHT EMITTING DEVICE AND LIGHTING EQUIPMENT - A light emitting device has a base comprising at least one pair of leads having a silver-containing layer on their surfaces and being secured by a resin molded body, a light emitting element mounted on said leads, a protective film made of an inorganic material that covers the upper surface of said base, and a sealing resin disposed on the base surface via said protective film. The sealing resin has a first resin that covers said light emitting element, and a second resin having a higher hardness than said first resin that covers the boundaries between said resin molded body and said leads. | 2013-07-18 |
20130181237 | Light Emitting Systems and Methods - A light emitting system and related method are disclosed. | 2013-07-18 |
20130181238 | ELECTRONIC DEVICES WITH YIELDING SUBSTRATES - In accordance with certain embodiments, a semiconductor die is adhered directly to a yielding substrate with a pressure-activated adhesive notwithstanding any nonplanarity of the surface of the semiconductor die or non-coplanarity of the semiconductor die contacts. | 2013-07-18 |
20130181239 | SEMICONDUCTOR LIGHT EMITTING DEVICE - Disclosed is a semiconductor light emitting device. The semiconductor light emitting device comprises a first semiconductor layer, a second semiconductor layer, an active layer formed between the first semiconductor layer and the second semiconductor layer, a first reflective electrode on the first semiconductor layer to reflect incident light, and a second reflective electrode on the second semiconductor layer to reflect the incident light. | 2013-07-18 |
20130181240 | COMPOSITE SUBSTRATE, MANUFACTURING METHOD THEREOF AND LIGHT EMITTING DEVICE HAVING THE SAME - The present invention relates to a manufacturing method of a composite substrate. The method includes the steps of: providing a substrate; providing a precursor of group III elements and a precursor of nitrogen (N) element alternately in an atomic layer deposition (ALD) process or a plasma-enhanced atomic layer deposition (PEALD) process so as to deposit a nitride buffer layer on the substrate; and annealing the nitride buffer layer on the substrate at a temperature in the range of 300° C. to 1600° C. | 2013-07-18 |
20130181241 | METHOD OF MOLDING STRUCTURES IN A PLASTIC SUBSTRATE - A method of manufacturing a substrate, characterized by a first surface and a second surface, for use in a semiconductor device is provided. The method includes providing a mold having a first template and/or a second template corresponding to a first texture and a second texture respectively. Then, the method includes injection molding a material for the substrate in the mold, to form the substrate, such that the material is injection molded to create the first texture on the first surface and/or the second texture on the second surface. The first texture and/or the second texture facilitate light extraction or light trapping in the semiconductor device. | 2013-07-18 |
20130181242 | ORGANIC ELECTROLUMINESCENT DEVICE AND METHOD FOR MANUFACTURING THEREOF - Disclosed is an organic electroluminescent device and a method for manufacturing thereof, the device including a light emitting part in which a substrate, a first electrode, an organic light emitting layer and a second electrode, and a nano structure including a first opening part randomly distributed between the substrate and the first electrode, wherein the nano structure includes at least anyone of polyimide, epoxy, polycarbonate, PVC, PVP, polyethylene, polyacryl and perylene, each having a refractive index in the range of 1.3˜1.5, whereby a light extraction can be improved by restricting a reflective light from an interface between the substrate and the first electrode. | 2013-07-18 |
20130181243 | Solid State Lighting Device - A solid state lighting device, including: a housing, which has a reflective cup inside; a solid state light source, placed inside the housing; a transparent adhesive material, used to seal the solid state light source in the housing; and a multi-layer fluorescent structure, placed on the transparent adhesive material and having a fluorescent layer or a phosphor layer sandwiched by two transparent adhesive layers, so as to absorb light beams from the solid state light source and then emit light of longer wavelengths. | 2013-07-18 |
20130181244 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD OF FORMING ELECTRODE - A semiconductor light-emitting device having an electrode that can be manufactured by a simple method and is unlikely to deteriorate, and a method for forming the electrode are provided. The semiconductor light-emitting device according to the present invention has a semiconductor layered structure having a light-emitting layer that emits light by supplying electric power and an electrode formed on the semiconductor layered structure. The electrode has a reflection layer that reflects light exiting from the light-emitting layer, a barrier layer formed on the upper side and side surface of the reflection layer, and a pad layer formed only on the top surface of the barrier layer. | 2013-07-18 |
20130181245 | LIGHT-EMITTING DEVICE - A light-emitting device including: a light-emitting stacked layer having first conductivity type semiconductor layer, a light-emitting layer formed on the first conductivity type semiconductor layer, and a second conductivity type semiconductor layer formed on the light-emitting layer, wherein the upper surface of the second conductivity type semiconductor layer is a textured surface; a first planarization layer formed on a first part of the upper surface of the second conductivity type semiconductor layer; a first transparent conductive oxide layer formed on the first planarization layer and a second part of the second conductivity type semiconductor layer, including a first portion in contact with the first planarization layer and a second portion having a first plurality of cavities in contact with the second conductivity type semiconductor layer;; and a first electrode formed on the first portion of the first transparent conductive oxide layer. | 2013-07-18 |
20130181246 | ILLUMINATING DEVICE WITH LED SURFACE LIGHT SOURCE COVERED WITH OPTICAL FILM - The present invention provides an LED light source, and particularly provides an illuminating device with an LED surface light source covered with an optical film. The device includes: an LED point light source, an illuminator, and a heat sink; wherein the illuminator is an optically transparent solid geometry with an optical film covering the outer surface thereof; wherein at least one outer surface of the solid geometry is an incident surface and at least one outer surface of the solid geometry is an emergence surface; and the optical film is a solid optical medium film; and the LED point light source is fixed on the heat sink, matching with the incident surface of the illuminator. | 2013-07-18 |
20130181247 | Semiconductor Component and Method for Producing a Semiconductor Component - A semiconductor component includes at least one optoelectronic semiconductor chip and a connecting carrier having a connecting surface on which the semiconductor chip is disposed. A reflective coating and a limiting structure are formed on the connecting carrier. The limiting structure at least partially encloses the semiconductor chip in the lateral direction, and the reflective coating at least partially extends in the lateral direction between a side surface of the semiconductor chip and the limiting structure. | 2013-07-18 |
20130181248 | Optoelectronic Semiconductor Component - An optoelectronic semiconductor component comprising a light source, a housing and electrical connections, wherein the light source emits primary radiation having a peak wavelength in the range of 420 to 460 nm and having a flank of the primary emission which extends into the range less than 420 nm, wherein the radiation of the flank range or of part thereof is converted into visible radiation by an additive phosphor. | 2013-07-18 |
20130181249 | LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME, AND LIGHT EMITTING UNIT - A light emitting device includes: a laminated body including a first-conductivity type semiconductor layer, a light emitting layer, and a second-conductivity type semiconductor layer in this order; a contact layer provided in contact with the second-conductivity type semiconductor layer at least at a peripheral edge of the second-conductivity type semiconductor layer; a first electrode electrically connected to the first-conductivity type semiconductor layer; a second electrode provided nearer to the first-conductivity type semiconductor layer than the second-conductivity type semiconductor layer; and a conductor electrically connecting the second electrode and the contact layer to each other. | 2013-07-18 |
20130181250 | LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - By using a light emitting device including an insulating substrate and a light emitting unit formed on the insulating substrate, the light emitting unit including: a plurality of linear wiring patterns disposed on the insulating substrate in parallel with one another, a plurality of light emitting elements that are mounted between the wiring patterns while being electrically connected to the wiring patterns, and a sealing member for sealing the light emitting elements, as well as a method for manufacturing thereof, it becomes possible to provide a light emitting device that achieves sufficient electrical insulation and has simple manufacturing processes so that it can be manufactured at a low cost, and a method for manufacturing the same. | 2013-07-18 |
20130181251 | LED MODULE - An LED module includes: a package having electrodes provided on the outer surface of opposing sidewalls, and a light-emitting element connected to the electrodes and mounted on the package; a base member having a copper metal; an insulating layer stacked on the surface of the base member and having an insulating material; and a conductive wiring pattern connected to the electrodes by soldering and formed on the surface of the insulating layer. The insulating layer has a through-hole formed by removing a part of the section where the package is positioned, and a heat dissipation unit formed by soldering between the back surface of the package and the base member, which face one another with the through-hole interposed therebetween. | 2013-07-18 |
20130181252 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor layer; a first type of a first semiconductor element that is arranged in a first element region of the semiconductor layer, has first and second main electrodes, and switches current; and a second type of a second semiconductor element that is arranged in a second element region of the semiconductor layer, has third and fourth main electrodes, and freewheels the current. The first and second element regions are adjacent in a direction orthogonal to a direction in which current flows, and are formed in a loop shape over the entire element region when the semiconductor layer is viewed from above. The first main electrode is electrically connected to the third main electrode, and the second main electrode is electrically connected to the fourth main electrode. When the semiconductor layer is viewed from above, a ratio of a length of the first main electrode to a length of the second main electrode is larger than a ratio of a length of the third main electrode to a length of the fourth main electrode. | 2013-07-18 |
20130181253 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - The present invention discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure is formed in a first conductive type substrate, which has an upper surface. The semiconductor structure includes: a protected device, at least a buried trench, and at least a doped region. The protected device is formed in the substrate. The buried trench is formed below the upper surface with a first depth, and the buried trench surrounds the protected device from top view. The doped region is formed below the upper surface with a second depth, and the doped region surrounds the buried trench from top view. The second depth is not less than the first depth. | 2013-07-18 |
20130181254 | SEMICONDUCTOR DEVICE - In a semiconductor device having a semiconductor substrate on which a diode and an IGBT are formed, a cathode region of the diode and a collector region of the IGBT are formed in a range exposed to one surface of the semiconductor substrate. On the surface, a first conductor layer that is in contact with the cathode region, and a second conductor layer that is in contact with the collector region are formed. The work function of the second conductor layer is larger than the work function of the first conductor layer. | 2013-07-18 |
20130181255 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - There is provided a vertical GaN-based semiconductor device in which the on-resistance can be decreased while the breakdown voltage characteristics are improved using a p-type GaN barrier layer. The semiconductor device includes a regrown layer | 2013-07-18 |
20130181256 | SEMICONDUCTOR DEVICES - In an embodiment, a semiconductor device is provided. The semiconductor device may include a substrate having a main processing surface, a first source/drain region comprising a first material of a first conductivity type, a second source/drain region comprising a second material of a second conductivity type, wherein the second conductivity type is different from the first conductivity type, a body region electrically coupled between the first source/drain region and the second source/drain region, wherein the body region extends deeper into the substrate than the first source/drain region in a first direction that is perpendicular to the main processing surface of the substrate, a gate dielectric disposed over the body region, and a gate region disposed over the gate dielectric, wherein the gate region overlaps with at least a part of the first source/drain region and with a part of the body region in the first direction. | 2013-07-18 |
20130181257 | APPARATUS FOR FLEXIBLE ELECTRONIC INTERFACES AND ASSOCIATED METHODS - A semiconductor die includes at least one flexible interface block. The flexible interface block includes at least one interconnect, and at least one buffer coupled to the at least one interconnect. The flexible interface block further includes a routing interface coupled to circuitry integrated in the semiconductor die, and a controller coupled to provide communication between the routing interface and the at least one buffer. | 2013-07-18 |
20130181258 | IMAGE SENSOR AND METHOD OF MANUFACTURING - An image sensor includes a substrate having opposite first and second sides, a multilayer structure on the first side of the substrate, and a photo-sensitive element on the second side of the substrate. The photo-sensitive element is configured to receive light that is incident upon the first side and transmitted through the multilayer structure and the substrate. The multilayer structure includes first and second light transmitting layers. The first light transmitting layer is sandwiched between the substrate and the second light transmitting layer. The first light transmitting layer has a refractive index that is from 60% to 90% of a refractive index of the substrate. The second light transmitting layer has a refractive index that is lower than the refractive index of the first light transmitting layer and is from 40% to 70% of the refractive index of the substrate. | 2013-07-18 |
20130181259 | STEP-LIKE SPACER PROFILE - Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a step-like or tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode, etching the spacer material to form a first spacer on each side of the gate electrode, and pulling back the first spacers to form second spacers which have a step-like profile. Embodiments further include depositing a second spacer material over the gate electrode and the second spacers, and etching the second spacer material to form a third spacer on each second spacer, the second and third spacers forming an outwardly tapered composite spacer. | 2013-07-18 |
20130181260 | METHOD FOR FORMING N-SHAPED BOTTOM STRESS LINER - Semiconductor devices with n-shaped bottom stress liners are formed. Embodiments include forming a protuberance on a substrate, conformally forming a sacrificial material layer over the protuberance, forming a gate stack above the sacrificial material layer on a silicon layer, removing the sacrificial material layer to form a tunnel, and forming a stress liner in the tunnel conforming to the shape of the protuberance. Embodiments further include forming a silicon layer over the sacrificial material layer and lining the tunnel with a passivation layer prior to forming the stress liner. | 2013-07-18 |
20130181261 | BORDERLESS CONTACT STRUCTURE - A borderless contact structure or partially borderless contact structure and methods of manufacture are disclosed. The method includes forming a gate structure and a space within the gate structure, defined by spacers. The method further includes blanket depositing a sealing material in the space, over the gate structure and on a semiconductor material. The method further includes removing the sealing material from over the gate structure and on the semiconductor material, leaving the sealing material within the space. The method further includes forming an interlevel dielectric material over the gate structure. The method further includes patterning the interlevel dielectric material to form an opening exposing the semiconductor material and a portion of the gate structure. The method further includes forming a contact in the opening formed in the interlevel dielectric material. | 2013-07-18 |
20130181262 | Performing Treatment on Stressors - A method includes forming a gate stack over a semiconductor substrate, wherein the gate stack includes a gate dielectric and a gate electrode over the gate dielectric. A portion of the semiconductor substrate adjacent to the gate stack is recessed to form a recess. A semiconductor region is epitaxially grown in the recess. The semiconductor region is implanted with a p-type impurity or an n-type impurity. A dry treatment is performed on the semiconductor region. | 2013-07-18 |
20130181263 | Methods of Forming a Dielectric Cap Layer on a Metal Gate Structure - Disclosed herein are various methods of forming isolation structures on FinFETs and other semiconductor devices, and the resulting devices that have such isolation structures. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate, wherein the trenches define a fin for a FinFET device, forming a layer of insulating material in the trenches, wherein the layer of insulating material covers a lower portion of the fin but not an upper portion of the fin, forming a protective material on the upper portion of the fin, and performing a heating process in an oxidizing ambient to form a thermal oxide region on the covered lower portion of the fin. | 2013-07-18 |
20130181264 | SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF - A semiconductor structure includes at least a fin-shaped structure, a gate, a source/drain region, an interdielectric layer and an epitaxial structure. At least a fin-shaped structure is located on a bottom substrate. The gate covers the fin-shaped structure. The source/drain region is located in the fin-shaped structure next to the gate. The interdielectric layer covers the gate and the fin-shaped structure, wherein the interdielectric layer has a plurality of contact holes, respectively exposing at least a part of the source/drain region. The epitaxial structure is located in each of the contact holes, directly contacts and is only located on the source/drain region. Additionally, a semiconductor process formed said semiconductor structure is also provided. | 2013-07-18 |
20130181265 | Methods of Forming a Gate Cap Layer Above a Replacement Gate Structure and a Semiconductor Device That Includes Such a Gate Structure and Cap Layer - Disclosed herein are various methods of forming a gate cap layer above a replacement gate structure, and a device having such a cap layer. In one example, a device disclosed herein includes a replacement gate structure having a dished upper surface, sidewall spacers positioned proximate the replacement gate structure and a gate cap layer positioned above the replacement gate structure, wherein the gate cap layer has a bottom surface that corresponds to the dished upper surface of the replacement gate structure. | 2013-07-18 |
20130181266 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - In a method of fabricating a semiconductor device on a substrate having thereon a conductive layer, the conductive layer is patterned to form a plurality of opened regions. A gate insulation layer is formed on a side wall of each of the opened regions. A pillar pattern is formed in each opened region. On each pillar pattern, a gate electrode, which encloses the pillar pattern, is formed by removing the conductive layer between the pillar patterns. | 2013-07-18 |
20130181267 | WAFER FILL PATTERNS AND USES - A semiconductor device includes an active region including an element formed in a double etch, double exposure method and an inactive region including one or more fills, at least one of the one or more fills including a cut-away hole formed therein, where the cut-away holes expose a layer in the inactive region used for an endpoint detection. | 2013-07-18 |
20130181268 | PHOTOELECTRIC CONVERSION APPARATUS, IMAGE PICKUP SYSTEM, AND METHOD FOR MANUFACTURING PHOTOELECTRIC CONVERSION APPARATUS - A photoelectric conversion section contains a semiconductor element having a laminated structure which contains an electroconductor, a semiconductor, and an insulator provided between the electroconductor and the semiconductor, in which the insulator is a silicon oxide film containing nitrogen in a main portion located between the electroconductor and the semiconductor. | 2013-07-18 |
20130181269 | DECOUPLING CAPACITOR AND METHOD OF MAKING SAME - A device comprises a semiconductor substrate having first and second implant regions and an electrode above and between the first and second implant regions of a first dopant type. A contact structure is in direct contact with the first and second implant regions and the electrode. A third implant region has a second dopant type different from the first dopant type. A bulk contact is provided on the third implant. | 2013-07-18 |
20130181270 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a capacitor, the capacitor includes: a first semiconductor region of a first conductivity type; a second semiconductor region of the first conductivity type disposed on the first semiconductor region, the second semiconductor region having a higher first-conductivity-type impurity concentration than the first semiconductor region; a third semiconductor region of the first conductivity type disposed on the second semiconductor region, the third semiconductor region including a contact region and having a higher first-conductivity-type impurity concentration than the second semiconductor region; a dielectric film disposed on the third semiconductor region; and an upper electrode disposed on the dielectric film beside the contact region. | 2013-07-18 |
20130181271 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device capable of increasing ON current while reducing channel resistance and allowing transistors to operate independently and stably, having a fin formed to protrude from the bottom of a gate electrode trench, a gate insulating film covering the surfaces of the gate electrode trench and the fin, a gate electrode embedded in a lower part of the gate electrode trench and formed to stride over the fin via the gate insulating film, a first impurity diffusion region arranged on a first side face, and a second impurity diffusion region arranged on a second side face. | 2013-07-18 |
20130181272 | IC DIE, SEMICONDUCTOR PACKAGE, PRINTED CIRCUIT BOARD AND IC DIE MANUFACTURING METHOD - In an example embodiment, an integrated circuit (IC) comprises a substrate separating one of a source and drain from a semiconductor region. The IC comprises a vertical transistor including the source or drain. A gate electrode is formed in a trench extending into the semiconductor region; the gate electrode is electrically insulated from the semiconductor region by a dielectric lining in the trench and the other of said source or drain in the semiconducting region. An insulating trench terminates the vertical transistor; a vertical capacitor region (V-Cap) is adjacent to the vertical transistor; a first capacitor plate of the V-Cap comprises the source or drain separated from the semiconductor region by the substrate; the V-Cap further comprises at least one trench extending into the semiconductor region; the at least one trench comprises an electrically insulating liner material insulating a conductive material defining a second capacitor plate separated from the first capacitor plate. | 2013-07-18 |
20130181273 | METHOD OF MAKING A NON-VOLATILE DOUBLE GATE MEMORY CELL - A method of making a non-volatile double-gate memory cell. A gate of the control transistor is formed with a relief on a substrate. A control gate of the memory transistor is formed with a layer of a semiconductor material covering relief. The method includes chemical mechanical polishing (CMP) so as to strip, above the relief another layer and part of the layer of a semiconductor material; stripping of the remaining other layer on both sides of the relief, etching of the layer of a semiconductor material so as to strip this material above the relief and to leave only a pattern on at least one sidewall of the relief. | 2013-07-18 |
20130181274 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a substrate and a first transistor. The substrate has a major surface. The first transistor is provided on the major surface. The first transistor includes a first stacked body, first and second conductive sections, a first gate electrode, and a first gate insulating film. The first stacked body includes first semiconductor layers and first insulating layers alternately stacked. The first semiconductor layers have a side surface. The first conductive section is electrically connected to one of the first semiconductor layers. The second conductive section is apart from the first conductive section and electrically connected to the one of the first semiconductor layers. The first gate electrode is provided between the first and second conductive sections and opposed to the side surface. The first gate insulating film is provided between the first gate electrode and the first semiconductor layers. | 2013-07-18 |
20130181275 | MANUFACTURING METHOD OF NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND A NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - A nonvolatile semiconductor storage device has a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, multiple floating gate electrodes formed on the gate insulating film, an inter-electrode insulating film formed on the multiple floating gate electrodes, and word lines formed on the inter-electrode insulating film. The word lines have lower and upper layers containing polysilicon doped with an impurity and are formed with a separating layer between the lower layer and the upper layer. A portion of the separating layer is located between multiple floating gate electrodes, and the height of the lower layer is less than the height of the upper layer. | 2013-07-18 |
20130181276 | NON-SELF ALIGNED NON-VOLATILE MEMORY STRUCTURE - A non-self aligned non-volatile memory structure includes a semiconductor substrate; a first gate insulation layer on said semiconductor substrate; a floating gate on first gate insulation layer; two doped regions in said semiconductor substrate, which are respectively on two sides of said first gate insulation layer, and adjoining said first gate insulation layer; a second gate insulation layer on said floating gate; and a control gate on said second gate insulation layer. Width of said control gate on said floating gate is less than that of said floating gate, and width of said control gate not on said floating gate is equal to or greater than width of said floating gate. Through the two non-self aligned gates, the non-volatile memory does not need to meet the requirement of gate line-to-line alignment, thus reducing complexity and cost of manufacturing process. | 2013-07-18 |
20130181277 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THEREOF - A semiconductor device includes a semiconductor substrate having a first opening and a second opening adjacent thereto. A first dielectric layer is disposed in a lower portion of the first opening. A charge-trapping dielectric layer is disposed in an upper portion of the first opening to cover the first dielectric layer. A doping region of a predetermined conductivity type is formed in the semiconductor substrate adjacent to the first opening and the second opening, wherein the doping region of the predetermined conductivity type has a polarity which is different from that of the charges trapped in the charge-trapping dielectric layer. A gate electrode is disposed in a lower portion of the second opening. A method for fabricating the semiconductor device is also disclosed. | 2013-07-18 |
20130181278 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE DEVICE - Provided is a non-volatile memory device that includes a substrate including a plurality of active regions extending in a first direction and a plurality of element isolation trenches disposed between the active regions, a plurality of tunnel insulating layer patterns and a plurality of storage layer patterns sequentially disposed on the substrate, a plurality of blocking insulating layers and a plurality of gate electrodes disposed on the storage layer patterns and extending in a second direction perpendicular to the first direction, and first insulating layers including air gaps disposed between the active regions on the element isolation trenches and extending in the first direction, wherein the active regions include first active regions and second active regions adjacent to the first active regions, wherein a width of first air gaps is different from a width of second air gaps. | 2013-07-18 |
20130181279 | SONOS STRUCTURE AND MANUFACTURING METHOD THEREOF - The invention provides an SONOS structure and a manufacturing method thereof The manufacturing method comprises: forming a tunneling oxide layer on a substrate; depositing a Si-rich silicon nitride layer above the tunneling oxide layer, wherein the Si/N content ratio of the Si-rich silicon nitride layer is constant; depositing a graded silicon nitride layer having graded silicon content above the Si-rich silicon nitride layer; and depositing a blocking oxide layer; wherein the silicon content of the graded silicon nitride layer is reduced in the direction from the Si-rich silicon nitride layer to the blocking oxide layer. According to the present invention, the Si-rich silicon nitride layer provides shallower trapping levels, which is beneficial to trap the charges and improve the programming and erasing speed. Furthermore, the charge retention time increases due to the constrained charges in the deep trapping levels, thus the reliability of the device enhances. | 2013-07-18 |
20130181280 | PSEUDO SELF ALIGNED RADHARD MOSFET AND PROCESS OF MANUFACTURE - A Vertical Power MOSFET (VDMOS) device with special features that enable the Power MOSFET or IGBT device to withstand harsh radiation environments and the process of making such a device is described. All implanted and diffused layers are “self aligned” to a “Sacrificial Poly” layer, which later on is removed, preparing the wafers for a “late gate” oxide to be grown. A starting material with graded doping profile in the epitaxial layer on the substrate is shown to increase the SEB capability of the Power MOSFET. | 2013-07-18 |
20130181281 | Semiconductor Transistor Having Trench Contacts and Method for Forming Therefor - Embodiments described herein relate to semiconductor transistors having trench contacts, in particular to semiconductor transistors having a field electrode below a gate electrode, and to related methods for producing semiconductor transistors having trench contacts. | 2013-07-18 |
20130181282 | FIELD EFFECT TRANSISTOR WITH SELF-ALIGNED SOURCE AND HEAVY BODY REGIONS - A field effect transistor includes a plurality of trenches extending into a semiconductor region of a first conductivity type. The plurality of trenches includes a plurality of gated trenches and a plurality of non-gated trenches. A body region of a second conductivity extends in the semiconductor region between adjacent trenches. A dielectric material fills a bottom portion of each of the gated and non-gated trenches. A gate electrode is disposed in each gated trench. A conductive material of the second conductivity type is disposed in each non-gated trench such that the conductive material and contacts corresponding body regions along sidewalls of the non-gated trench. | 2013-07-18 |
20130181283 | SWITCHING ELEMENT - In a switching element, a first region that is exposed on an upper surface of a semiconductor substrate, a second region that is exposed on the upper surface of the substrate and extends to below the first region, and a third region that is formed below the second region, are formed on the substrate. A trench is formed in the upper surface of the substrate. A gate electrode has a first portion that extends from a depth of the first region to a depth of the third region at at least a portion in the trench formed in an area where the first region is exposed, and a second portion that is formed to a depth of the second region, and does not reach the depth of the third region, at at least a portion in the trench formed in an area where the second region is exposed. | 2013-07-18 |
20130181284 | Method for Forming Self-Aligned Trench Contacts of Semiconductor Components and A Semiconductor Component - A method for producing a semiconductor component is described. The method includes providing a semiconductor body having a first surface and being comprised of a first semiconductor material extending to the first surface. At least one trench extends from the first surface into the semiconductor body and includes a gate electrode insulated from the semiconductor body and arranged below the first surface. The method further includes: forming a second insulation layer on the first surface with a recess that overlaps in projection onto the first surface with the conductive region; forming a mask region in the recess; etching the second insulation layer selectively to the mask region and the semiconductor body to expose the semiconductor body at the first surface; depositing a third insulation layer on the first surface; and etching the third insulation layer so that a semiconductor mesa of the semiconductor body arranged next to the a least one trench is exposed at the first surface. | 2013-07-18 |
20130181285 | Lateral DMOS Device with Dummy Gate - An LDMOS transistor with a dummy gate comprises an extended drift region formed over a substrate, a drain region formed in the extended drift region, a channel region formed in the extended drift region, a source region formed in the channel region and a dielectric layer formed over the extended drift region. The LDMOS transistor with a dummy gate further comprises an active gate formed over the channel region and a dummy gate formed over the extended drift region. The dummy gate helps to reduce the gate charge of the LDMOS transistor while maintaining the breakdown voltage of the LDMOS transistor. | 2013-07-18 |
20130181286 | HIGH VOLTAGE DEVICE - A method of forming a device is presented. The method includes providing a substrate having a device region which includes a source region, a gate and a drain region defined thereon. The method also includes implanting the gate. The gate comprises one or more doped portions with different dopant concentrations. A source and a drain are formed in the source region and drain region. The drain is separated from the gate on a second side of the gate and the source is adjacent to a first side of the gate. | 2013-07-18 |
20130181287 | HIGH VOLTAGE DEVICE - A method of forming a device is disclosed. A substrate having a device region is provided. The device region comprises a source region, a gate and a drain region defined thereon. A drift well is formed in the substrate adjacent to a second side of the gate. The drift well underlaps a portion of the gate with a first edge of the drift well beneath the gate. A secondary portion is formed in the drift well. The secondary portion underlaps a portion of the gate with a first edge of the secondary portion beneath the gate. The first edge of the secondary portion is offset from the first edge of the drift well. A gate dielectric of the gate comprises a first portion having a first thickness and a second portion having a second thickness. The second portion is over the secondary portion. | 2013-07-18 |
20130181288 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device including a gate electrode formed over a first region of a semiconductor substrate of a first conduction type; a source region and a drain region of the first conduction type formed on both sides of the gate electrode; a channel dope layer of a second conduction type formed in at least a region on a side of the source region of a channel region, the channel dope layer having a concentration gradient of a concentration of a dopant impurity of the second conduction type, which decrease toward the drain region; a first well of the second conduction type having a concentration gradient of a concentration of a dopant impurity of the second conduction type, which decrease toward the drain region; and a second well of the second conduction type formed in the first region, connected to the first well and positioned below the first well. | 2013-07-18 |
20130181289 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate having a diffusion region. A transistor is formed within the diffusion region. A power rail is disposed outside the diffusion region. A contact layer is disposed above the substrate and below the power rail. A via is disposed between the contact layer and the power rail to electrically connect the contact layer to the power rail. The contact layer includes a first length disposed outside the diffusion region and a second length extending from the first length into the diffusion region and electrically connected to the transistor. | 2013-07-18 |
20130181290 | Selective Amorphization for Electrical Signal Isolation and Linearity in SOI Structures - Provided is a structure for improved electrical signal isolation between adjacent devices situated in a top semiconductor layer of the structure and a method for the structure's fabrication. The structure comprises a gate situated on the top semiconductor layer, the top semiconductor layer situated over a base oxide layer, and the base oxide layer situated over a handle wafer. The top surface of the handle wafer is amorphized by an inert implant of Xenon or Argon to reduce carrier mobility in the handle wafer and improve electrical signal isolation between the adjacent devices situated in the top semiconductor layer. | 2013-07-18 |
20130181291 | SILICON OXYNITRIDE FILM AND METHOD FOR FORMING SAME, AND SEMICONDUCTOR DEVICE - An insulating film that does not contain hydrogen or free fluorine and has good film properties is provided. A silicon oxynitride film includes silicon, nitrogen, oxygen, and fluorine, wherein the elemental percentage (N+O+F)/Si of the total (N+O+F) of nitrogen (N), oxygen (0), and fluorine (F) to silicon (Si) is in a range of 1.93 to 1.48, and in the silicon oxynitride film, an elemental percentage of silicon ranges from 0.34 to 0.41, an elemental percentage of nitrogen ranges from 0.10 to 0.22, an elemental percentage of oxygen ranges from 0.14 to 0.38, and an elemental percentage of fluorine ranges from 0.17 to 0.24. The film can be formed on a substrate by inductive coupling type plasma CVD whereby a plasma is generated by inductive coupling using a silicon tetrafluoride gas, a nitrogen gas, and an oxygen gas as a material gas. | 2013-07-18 |
20130181292 | LOCAL INTERCONNECTS COMPATIBLE WITH REPLACEMENT GATE STRUCTURES - After forming replacement gate structures that are embedded in a planarized dielectric layer on a semiconductor substrate, a contact-level dielectric layer is deposited over a planar surface of the planarized dielectric layer and the replacement gate structures. Substrate contact via holes are formed through the contact-level dielectric layer and the planarized dielectric layer, and metal semiconductor alloy portions are formed on exposed semiconductor materials. Gate contact via holes are subsequently formed through the contact-level dielectric layer. The substrate contact via holes and the gate contact via holes are simultaneously filled with a conductive material to form substrate contact structures and gate contact structures. The substrate contact structures and gate contact structures can be employed to provide local interconnect structures that provide electrical connections between two components that are laterally spaced on the semiconductor substrate. | 2013-07-18 |
20130181293 | DIFFUSION BARRIER FOR OPPOSITELY DOPED PORTIONS OF GATE CONDUCTOR - A method patterns a polysilicon gate over two immediately adjacent, opposite polarity transistor devices. The method patterns a mask over the polysilicon gate. The mask has an opening in a location where the opposite polarity transistor devices abut one another. The method then removes some (a portion) of the polysilicon gate through the opening to form at least a partial recess (or potentially a complete opening) in the polysilicon gate. The recess separates the polysilicon gate into a first polysilicon gate and a second polysilicon gate. After forming the recess, the method dopes the first polysilicon gate using a first polarity dopant and dopes the second polysilicon gate using a second polarity dopant having an opposite polarity of the first polarity dopant. | 2013-07-18 |
20130181294 | METHOD FOR FABRICATION OF AN INTEGRATED CIRCUIT IN A TECHNOLOGY REDUCED WITH RESPECT TO A NATIVE TECHNOLOGY, AND CORRESPONDING INTEGRATED CIRCUIT - The technological fabrication of the integrated circuit includes a fabrication of the integrated circuit in a reduced technological version of a native technology including at least a first dimensional compensation applied to the reduced channel length and to the reduced channel width of each transistor originating from a transistor, referred to as a “minimum transistor”, designed in the native technology and having in this native technology an initial channel length equal to a minimum length for the native technology and an initial channel width equal to a minimum width for the native technology. The fabrication obtains a transistor having a channel length equal, to a given precision, to the initial channel length and a channel width equal, to a given precision, to the initial channel width. | 2013-07-18 |
20130181295 | ANALOG SIGNAL COMPATIBLE CMOS SWITCH AS AN INTEGRATED PERIPHERAL TO A STANDARD MICROCONTROLLER - At least one analog signal compatible complementary metal oxide semiconductor (CMOS) switch circuit is incorporated with digital logic circuits in an integrated circuit. The integrated circuit may further comprise a digital processor and memory, e.g., microcontroller, microprocessor, digital signal processor (DSP), programmable logic array (PLA), application specific integrated circuit (ASIC), etc., for controlling operation of the at least one analog signal compatible CMOS switch for switching analog signals, e.g., audio, video, serial communications, etc. The at least one analog signal compatible CMOS switch may have first and second states, e.g., single throw “on” or “off”, or double throw common to a or b, controlled by a single digital control signal of either a logic “0” or a logic “1”. | 2013-07-18 |
20130181296 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a semiconductor substrate with a p-type conductivity, a buried layer with an n-type conductivity provided on the semiconductor substrate, a back gate layer with a p-type conductivity provided on the buried layer, a drain layer with an n-type conductivity provided on the back gate layer, a source layer with an n-type conductivity provided spaced from the drain layer, a gate electrode provided in a region immediately above a portion of the back gate layer between the drain layer and the source layer, and a drain electrode in contact with a part of an upper surface of the drain layer. A thickness of the drain layer in a region immediately below a contact surface between the drain layer and the drain electrode is half a total thickness of the back gate and drain layers in the region. | 2013-07-18 |
20130181297 | SRAM Cells and Arrays - Static random access memory (SRAM) cells and SRAM cell arrays are disclosed. In one embodiment, an SRAM cell includes a pull-up transistor. The pull-up transistor includes a Fin field effect transistor (FinFET) that has a fin of semiconductive material. An active region is disposed within the fin. A contact is disposed over the active region of the pull-up transistor. The contact is a slot contact that is disposed in a first direction. The active region of the pull-up transistor is disposed in a second direction. The second direction is non-perpendicular to the first direction. | 2013-07-18 |
20130181298 | ADVANCED TRANSISTORS WITH PUNCH THROUGH SUPPRESSION - An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×10 | 2013-07-18 |
20130181299 | Strain Engineering in Three-Dimensional Transistors Based on Strained Isolation Material - In a three-dimensional transistor configuration, a strain-inducing isolation material is provided, at least in the drain and source areas, thereby inducing a strain, in particular at and in the vicinity of the PN junctions of the three-dimensional transistor. In this case, superior transistor performance may be achieved, while in some illustrative embodiments even the same type of internally stressed isolation material may result in superior transistor performance of P-channel transistors and N-channel transistors. | 2013-07-18 |
20130181300 | Control Fin Heights in FinFET Structures - A device includes a substrate, an isolation region at a top surface of the substrate, and a semiconductor fin over the isolation region. The semiconductor fin has a fin height smaller than about 400 Å, wherein the fin height is measured from a top surface of the semiconductor fin to a top surface of the isolation region | 2013-07-18 |
20130181301 | METHOD FOR MANUFACTURING A FIELD-EFFECT SEMICONDUCTOR DEVICE FOLLOWING A REPLACEMENT GATE PROCESS - A method of manufacturing a semiconductor device is disclosed. In one aspect, the method includes: forming a dummy gate over a substrate layer; forming first gate insulating spacers adjacent to sidewalls of the dummy gate and over the substrate layer, the first spacers having two sidewalls and two surface profiles where the sidewalls meet the substrate layer; forming a source and drain region using the surface profiles; forming second gate insulating spacers adjacent to the sidewalls of the first spacers and over the source and drain regions; removing the dummy gate and the first spacers, thereby forming a first recess; depositing a dielectric layer in the first recess along the side walls of the second spacers and over the substrate layer, thereby forming a second recess; and depositing a gate electrode in the second recess. | 2013-07-18 |
20130181302 | METHOD FOR MAKING A SUSPENDED MEMBRANE STRUCTURE WITH BURIED ELECTRODE - A microsystem and/or nanosystem type device is disclosed, comprising:
| 2013-07-18 |
20130181303 | DIE ATTACH STRESS ISOLATION - A microstructure device package includes a package housing configured and adapted to house a microstructure device. A bracket is housed in the package housing. The bracket includes a bracket base with a first bracket arm and a second bracket arm each extending from the bracket base. A channel is defined between the first and second bracket arms. The first bracket aim defines a first mounting surface facing inward with respect to the channel. The second bracket aim defines a second mounting surface facing outward with respect to the channel. The second mounting surface of the bracket is mounted to the package housing. A microstructure device is mounted to the first mounting surface in the channel. The bracket is configured and adapted to isolate the microstructure device from packaging stress imparted from the package housing on the second mounting surface of the bracket. | 2013-07-18 |
20130181304 | METHODS AND APPARATUS FOR MAGNETIC SENSOR HAVING NON-CONDUCTIVE DIE PADDLE - Methods and apparatus to provide an integrated circuit package having a conductive leadframe, a non-conductive die paddle mechanically coupled to the leadframe, and a die disposed on the die paddle and electrically connected to the leadframe. With this arrangement, eddy currents are reduced near the magnetic field transducer to reduce interference with magnetic fields. | 2013-07-18 |
20130181305 | MAGNETORESISTIVE ELEMENT AND MAGNETIC RANDOM ACCESS MEMORY - A magnetoresistive element according to an embodiment includes: a first ferromagnetic layer having changeable magnetization substantially perpendicular to a film plane; a second ferromagnetic layer having fixed magnetization substantially perpendicular to the film plane; a first nonmagnetic layer provided between the first ferromagnetic layer and the second ferromagnetic layer; a third ferromagnetic layer provided on the opposite side of the second ferromagnetic layer from the first nonmagnetic layer, the third ferromagnetic layer having magnetization substantially parallel to the film plane, the third ferromagnetic layer generating a rotating magnetic field when spin-polarized electrons are injected thereinto; and a second nonmagnetic layer provided between the second ferromagnetic layer and the third ferromagnetic layer. | 2013-07-18 |
20130181306 | NON-VOLATILE MEMORY WITH STRAY MAGNETIC FIELD COMPENSATION - A method and apparatus for stray magnetic field compensation in a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM). In some embodiments, a first tunneling barrier is coupled to a reference structure that has a perpendicular anisotropy and a first magnetization direction. A recording structure that has a perpendicular anisotropy is coupled to the first tunneling barrier and a nonmagnetic spacer layer. A compensation layer that has a perpendicular anisotropy and a second magnetization direction in substantial opposition to the first magnetization direction is coupled to the nonmagnetic spacer layer. Further, the memory cell is programmable to a selected resistance state with application of a current to the recording structure. | 2013-07-18 |
20130181307 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - According to an embodiment, a method of manufacturing a semiconductor device is provided. The method of manufacturing a semiconductor device includes forming a blocking film by a material including at least carbon on an upper surface of a second element among a first element and the second element formed on a semiconductor substrate, the blocking film configured to inhibit the second element from turning into salicide. | 2013-07-18 |
20130181308 | METHODS OF FABRICATING DILUTE NITRIDE SEMICONDUCTOR MATERIALS FOR USE IN PHOTOACTIVE DEVICES AND RELATED STRUCTURES - Dilute nitride III-V semiconductor materials may be formed by substituting As atoms for some N atoms within a previously formed nitride material to transform at least a portion of the previously formed nitride into a dilute nitride III-V semiconductor material that includes arsenic. Such methods may be employed in the fabrication of photoactive devices, such as photovoltaic cells and photoemitters. The methods may be carried out within a deposition chamber, such as a metalorganic chemical vapor deposition (MOCVD) or a vapor phase epitaxy (HVPE) chamber. | 2013-07-18 |
20130181309 | IMAGE PICKUP APPARATUS AND IMAGE PICKUP SYSTEM - An image pickup apparatus includes photoelectric conversion units each including a first semiconductor region of a first conductivity type and a semiconductor region of a second conductivity type disposed in contact with the first semiconductor region, a potential barrier formed between photoelectric conversion units, and a contact plug disposed in an image sensing area. The number of contact plugs is smaller than the number of photoelectric conversion units. The photoelectric conversion units include first and second photoelectric conversion units and are arranged such that at least two first photoelectric conversion units are adjacent in a first direction. The potential barrier includes a first part formed between the two first photoelectric conversion units disposed adjacently and a second part formed between first and second photoelectric conversion units adjacent to each other. The contact plug is located closer to the first part than to the second part. | 2013-07-18 |
20130181310 | SEMICONDUCTOR APPARATUS AND IMAGE SENSOR PACKAGE USING THE SAME - A semiconductor apparatus and an image sensor package. The image sensor package includes a semiconductor apparatus including a body having a first surface and a second surface which face each other, a first trench formed in the first surface of the body, a second trench formed in the second surface of the body, a third trench formed in a bottom surface of the second trench, and an aperture connecting the first trench to the third trench, a transparent member placed in the third trench and covering the aperture, a mounting board placed under the second surface of the body, and an image sensor chip placed between the mounting board and the transparent member and surrounded by the second trench. | 2013-07-18 |
20130181311 | IMAGE SENSOR UNIT, IMAGE READING APPARATUS, IMAGE FORMING APPARATUS, AND MANUFACTURING METHOD - An image sensor unit includes: sensor substrates on which a plurality of sensor chips are mounted; rod-lens arrays that focus light from an original on the sensor substrates; and a frame body that houses the plurality of sensor substrates and the plurality of rod-lens arrays. The frame body is divided into a first frame and a second frame. A side surface of the rod-lens array in a sub-scan direction is fixed only by the first frame, and the plurality of rod-lens arrays are arranged in the main-scan direction. | 2013-07-18 |
20130181312 | SURFACE PASSIVATION BY QUANTUM EXCLUSION USING MULTIPLE LAYERS - A semiconductor device has a multilayer doping to provide improved passivation by quantum exclusion. The multilayer doping includes at least two doped layers fabricated using MBE methods. The dopant sheet densities in the doped layers need not be the same, but in principle can be selected to be the same sheet densities or to be different sheet densities. The electrically active dopant sheet densities are quite high, reaching more than 1×10 | 2013-07-18 |
20130181313 | IMAGE PICKUP UNIT AND METHOD OF MANUFACTURING THE SAME - An image pickup device and a method of the same are described herein. By way of first example, the image pickup device includes a seal member having a first surface, the first surface of the seal member including a concave portion, and an optical device coupled to a second surface of the seal member, the second surface of the seal member being opposite from the first surface of the seal member. By way of a second example, the image pickup device includes a seal member having a first surface, the first surface being a polished surface, and an optical device coupled to a second surface of the seal member, the second surface of the seal member being opposite from the first surface of the seal member. | 2013-07-18 |
20130181314 | SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME - A semiconductor package includes a light transmissive cover having a conductive pattern, a substrate having a cavity, a semiconductor chip in the cavity of the substrate and electrically connected to the conductive pattern arranged on the light transmissive cover, and a blocking pattern between the light transmissive cover and the substrate. | 2013-07-18 |
20130181315 | SILICON PHOTOELECTRIC MULTIPLIER - A cell for a silicon-based photoelectric multiplier may comprise a first layer of a first conductivity type and a second layer of a second conductivity type formed on the first layer. The first layer and the second layer may form a first p-n junction. The cell may be processed by an ion implantation act wherein parameters of the ion implantation are selected such that due to an implantation-induced damage of the crystal lattice, an absorption length of infrared light of a wavelength in a range of − | 2013-07-18 |
20130181316 | SOLID-STATE IMAGING DEVICE, IMAGING APPARATUS, SUBSTRATE, SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SOLID-STATE IMAGING DEVICE - A solid-state imaging device is a solid-state imaging device in which a first substrate formed on a first semiconductor wafer and a second substrate formed on a second semiconductor wafer are bonded via connect that electrically connects the substrates, wherein the first substrate includes photoelectric conversion units, the second substrate includes an output circuit that acquires a signal generated by the photoelectric conversion unit via the connector and outputs the signal, and dummy connectors that support the first and second bonded substrates are further arranged in a substrate region in which the connectors are not arranged in a substrate region of at least one of the first substrate and the second substrate. | 2013-07-18 |
20130181317 | SEMICONDUCTOR UNIT, METHOD OF MANUFACTURING THE SEMICONDUCTOR UNIT, SOLID-STATE IMAGE PICKUP UNIT, AND ELECTRONIC APPARATUS - A semiconductor unit includes: a first device substrate including a first semiconductor substrate and a first wiring layer, in which the first wiring layer is provided on one surface side of the first semiconductor substrate; a second device substrate including a second semiconductor substrate and a second wiring layer, in which the second device substrate is bonded to the first device substrate, and the second wiring layer is provided on one surface side of the second semiconductor substrate; a through-electrode penetrating the first device substrate and a part or all of the second device substrate, and electrically connecting the first wiring layer and the second wiring layer to each other; and an insulating layer provided in opposition to the through-electrode, and penetrating one of the first semiconductor substrate and the second semiconductor substrate. | 2013-07-18 |
20130181318 | HIGHLY EFFICIENT CMOS TECHNOLOGY COMPATIBLE SILICON PHOTOELECTRIC MULTIPLIER - The present disclosure relates to photodetectors with high efficiency of light detection, and may be used in a wide field of applications, which employ the detection of very weak and fast optical signals, such as industrial and medical tomography, life science, nuclear, particle, and/or astroparticle physics etc. A highly efficient CMOS-technology compatible Silicon Photoelectric Multiplier may comprise a substrate and a buried layer applied within the substrate. The multiplier may comprise cells with silicon strip-like quenching resistors, made by CMOS-technology, located on top of the substrate and under an insulating layer for respective cells, and separating elements may be disposed between the cells. | 2013-07-18 |
20130181319 | Trench Schottky Barrier Diode and Manufacturing Method Thereof - The present invention discloses a trench Schottky barrier diode (SBD) and a manufacturing method thereof. The trench SBD includes: an epitaxial layer, formed on a substrate; multiple mesas, defined by multiple trenches; a field plate, formed on the epitaxial layer and filled in the multiple trenches, wherein a Schottky contact is formed between the field plate and top surfaces of the mesas; a termination region, formed outside the multiple mesas and electrically connected to the field plate; a field isolation layer, formed on the upper surface and located outside the termination region; and at least one mitigation electrode, formed below the upper surface outside the termination region, and is electrically connected to the field plate through the field isolation layer, wherein the mitigation electrode and the termination region are separated by part of a dielectric layer and part of the epitaxial layer. | 2013-07-18 |
20130181320 | Manufacturing Techniques for Workpieces with Varying Topographies - Some embodiments relate to a method for processing a workpiece. In the method, an anti-reflective coating layer is provided over the workpiece. A first patterned photoresist layer, which has a first photoresist tone, is provided over the anti-reflective coating layer. A second patterned photoresist layer, which has a second photoresist tone opposite the first photoresist tone, is provided over the first patterned photoresist layer. An opening extends through the first and second patterned photoresist layers to allow a treatment to be applied to the workpiece through the opening. Other embodiments are also disclosed. | 2013-07-18 |
20130181321 | SOI Structure and Method for Utilizing Trenches for Signal Isolation and Linearity - Disclosed is a structure for improved electrical signal isolation between adjacent devices situated in a top semiconductor layer of the structure and an associated method for the structure's fabrication. The structure comprises a first portion of a trench extending through the top semiconductor layer and through a base oxide layer below the top semiconductor layer. A handle wafer is situated below the base oxide layer and a second portion of the trench, having sloped sidewalls, extends into the handle wafer. The sloped sidewalls are amorphized by an implant, for example, Xenon or Argon, to reduce carrier mobility in the handle wafer and improve electrical signal isolation between the adjacent devices situated in the top semiconductor layer. | 2013-07-18 |
20130181322 | Electrical Signal Isolation and Linearity in SOI Structures - Disclosed are a structure for electrical signal isolation between adjacent devices situated in a top semiconductor layer of the structure and an associated method for the structure's fabrication. The structure includes a trench extending through the top semiconductor layer and into a base oxide layer below the top semiconductor layer. A handle wafer is situated below the base oxide layer and a void is disposed in the handle wafer below the trench. A bottom opening of the trench connects the main body of the trench with the void forming a continuous cavity including the main body, the bottom opening of the trench, and the void such that the void improves electrical signal isolation between the adjacent devices situated in the top semiconductor layer. Unetched portions of the handle wafer are then available to provide mechanical support to the top semiconductor layer. | 2013-07-18 |