29th week of 2013 patent applcation highlights part 56 |
Patent application number | Title | Published |
20130185527 | Asymmetrically-Arranged Memories having Reduced Current Leakage and/or Latency, and Related Systems and Methods - Asymmetrically-arranged memories having reduced current leakage and/or latency, and related systems and methods are disclosed. In one embodiment, a memory comprises a memory access interface (MAI). The memory further comprises a first memory portion(s) accessible by the MAI. The first memory portion(s) has a first latency and a first current leakage. The memory further comprises a second memory portion(s) accessible by the MAI. To provide an asymmetrical memory arrangement, the first latency of the first memory portion(s) is increased such that the second memory portion(s) has a second latency greater than or equal to the first latency and a second current leakage greater than the first current leakage. Accordingly, the overall current leakage of the memory is reduced while not increasing overall latency of the memory. The first and second memory portion(s) may each be comprised of one or more memory sub-bank(s) and/or one or more memory bank(s). | 2013-07-18 |
20130185528 | RUNTIME DYNAMIC PERFORMANCE SKEW ELIMINATION - For runtime dynamic performance skew elimination in a computer environment, an exemplary computer environment is configured for calculating a rank heats by utilizing a plurality of fine-grained statistics collected at an extent granularity, including considering bandwidth (BW) and input/outputs per second (IOPS) metrics. An adaptive data placement plan is generated to relocate the data. | 2013-07-18 |
20130185529 | AUTOMATED DEPLOYMENT OF SOFTWARE FOR MANAGED HARDWARE IN A STORAGE AREA NETWORK - In one aspect of the present description, a systems manager based upon a common model of information protocol or standard includes automated storage area network (SAN) expansion management which permits additional provider modules to be automatically installed if needed in response to devices being added to the SAN. In addition, the automated SAN expansion management permits installed provider modules to be automatically configured in response to devices being added to the SAN. Still further, in another aspect, the automated SAN expansion management can automatically determine if a suitable host processor exists to host installation of a new provider module and if not, the automated SAN expansion management can automatically deploy a suitable host processor such as a virtual server to host installation of a new provider module. Other features and aspects may be realized, depending upon the particular application. | 2013-07-18 |
20130185530 | Method And Apparatus For A Frugal Cloud File System - Various embodiments provide a method and apparatus of providing a frugal cloud file system that efficiently uses the blocks of different types of storage devices with different properties for different purposes. The efficient use of the different types of available storage devices reduces the storage and bandwidth overhead. Advantageously, the reduction in storage and bandwidth overhead achieved using the frugal cloud file system reduces the economic costs of running the file system while maintaining high performance. | 2013-07-18 |
20130185531 | METHOD AND APPARATUS TO IMPROVE EFFICIENCY IN THE USE OF HIGH PERFORMANCE STORAGE RESOURCES IN DATA CENTER - Systems and methods described herein are directed to determining a partial migration plan to execute based on a policy. In situations where the performance of the virtual volumes is insufficient, the virtual volume should be migrated to a different storage pool or have high-performance media added to its current storage pool. A management program creates several migration plans for execution, which may include more than one partial migration plans. The plans may indicate the original storage subsystem, the target storage subsystem and a number of pages. The management program selects one of the plans, and proceeds to execute the selected plan. | 2013-07-18 |
20130185532 | APPARATUS, SYSTEM, AND METHOD FOR LOG STORAGE - A storage controller is configured to append data to a sequential log. The data may be appended sequentially within erase regions of the non-volatile storage medium. An order of the sequential log may be defined by, inter alia, the order in which the erase regions are filled and/or the sequential order of physical storage locations and/or addresses within the erase regions. The erase regions may comprise sequence information which may be applied in response to recovering the erase regions, appending data to the erase regions, or the like. Data appended to the sequential log may be associated with source parameters, which may include a virtual identifier of the data. The physical storage location of the data on the non-volatile storage medium may be independent of the source parameters. The sequential log may, therefore, comprise a set of mappings between virtual identifiers and physical storage locations. | 2013-07-18 |
20130185533 | SYSTEM FOR BACKING UP AND RESTORING THE FUNCTIONALITIES OF AN INFORMATION TECHNOLOGY SYSTEM - A system for backing up and restoring the functionalities of an information technology system which comprises an electronic computer, the electronic computer comprising elements for accessing the data communications network, a first hard disk, a removable slider which is adapted to contain the first hard disk, a first data bank; an operations center being adapted to retrieve instructions from the data bank which are adapted to be processed by the computer on the basis of a unique identifier associated with the electronic computer, the computer being further adapted to perform operations for backing up a restore point on elements for backing up data which are present on the first hard disk, on the basis of the instructions, and operations for restoring the data on the first hard disk on the basis of a choice made by a user. | 2013-07-18 |
20130185534 | SYSTEMS AND METHODS FOR VIRTUALIZING STORAGE SYSTEMS AND MANAGING DATA INDEPENDENTLY - Method, data processing systems, and computer program products are provided for virtualizing and managing a storage virtualization system (SVS) in a storage management architecture. Source data is copied from the source storage media to target data in a target storage media based on a predefined copy policy in a copy mapping table. A relation between the source data and the target data is tracked in a copy mapping table. It is determined if a copy of the requested data exists using the copy mapping table. | 2013-07-18 |
20130185535 | APPARATUS AND METHOD FOR PROCESSING NON-SEQUENTIALLY STORED DATA - An apparatus and method for processing non-sequentially stored data is provided. The data processing apparatus may include an order information mapping unit to map transmission order information to data, an address list generating unit to generate an address list including addresses of the data arranged sequentially based on the transmission order information, and a data processing unit to process the data corresponding to each of the addresses based on an address order of the address list. | 2013-07-18 |
20130185536 | HASH-BASED MANAGING OF STORAGE IDENTIFIERS - Managing storage identifiers in a pool is facilitated by providing a hashing-based management protocol in association with a stack which accommodates storage identifiers of the pool. The hashing-based management protocol includes: based on a request, popping a storage identifier from the stack without evaluating for update of a hash link associated with the stack, potentially allowing the hash link to become inconsistent with storage identifiers remaining in the stack; and based on return of a freed storage identifier to the stack, hashing the freed storage identifier and identifying whether there is an inconsistency in the hash link related to return of the freed storage identifier, and based on identifying the inconsistency, one of updating the hash link to remove the inconsistency, or indicating, where ascertained, that the freed storage identifier is a duplicate storage identifier. | 2013-07-18 |
20130185537 | HASH TABLE USING HASH TABLE BANKS - A hash table method and structure comprises a processor that receives a plurality of access requests for access to a storage device. The processor performs a plurality of hash processes on the access requests to generate a first number of addresses for each access request. Such addresses are within a full address range. Hash table banks are operatively connected to the processor. The hash table banks form the storage device. Each of the hash table banks has a plurality of input ports. Specifically, each of the hash table banks has less input ports than the first number of addresses for each access request. The processor provides the addresses to the hash table banks, and each of the hash table banks stores pointers corresponding to a different limited range of addresses within the full address range (each of the different limited range of addresses is less than the full address range). | 2013-07-18 |
20130185538 | PROCESSOR WITH INTER-PROCESSING PATH COMMUNICATION - A processor includes a scalar processor core and a vector coprocessor core coupled to the scalar processor core. The scalar processor core is configured to retrieve an instruction stream from program storage. The instruction stream includes scalar instructions executable by the scalar processor core and vector instructions executable by the vector coprocessor core. The scalar processor core is configured to pass the vector instructions to the vector coprocessor core. The vector coprocessor core configured to process a plurality of data values in parallel while executing each vector instruction passed by the scalar processor core. The vector coprocessor core includes a plurality of processing paths arranged in parallel to process the data values. Each of the processing paths includes an execution unit. Each of the execution units is configured to communicate a result of processing to each other of the execution units. | 2013-07-18 |
20130185539 | PROCESSOR WITH TABLE LOOKUP AND HISTOGRAM PROCESSING UNITS - A processor includes a scalar processor core and a vector coprocessor core coupled to the scalar processor core. The scalar processor core is configured to retrieve an instruction stream from program storage, and pass vector instructions in the instruction stream to the vector coprocessor core. The vector coprocessor core includes a register file, a plurality of execution units, and a table lookup unit. The register file includes a plurality of registers. The execution units are arranged in parallel to process a plurality of data values. The execution units are coupled to the register file. The table lookup unit is coupled to the register file in parallel with the execution units. The table lookup unit is configured to retrieve table values from one or more lookup tables stored in memory by executing table lookup vector instructions in a table lookup loop. | 2013-07-18 |
20130185540 | PROCESSOR WITH MULTI-LEVEL LOOPING VECTOR COPROCESSOR - A processor includes a scalar processor core and a vector coprocessor core coupled to the scalar processor core. The scalar processor core includes a program memory interface through which the scalar processor retrieves instructions from a program memory. The instructions include scalar instructions executable by the scalar processor and vector instructions executable by the vector coprocessor core. The vector coprocessor core includes a plurality of execution units and a vector command buffer. The vector command buffer is configured to decode vector instructions passed by the scalar processor core, to determine whether vector instructions defining an instruction loop have been decoded, and to initiate execution of the instruction loop by one or more of the execution units based on a determination that all of the vector instructions of the instruction loop have been decoded. | 2013-07-18 |
20130185541 | BITSTREAM BUFFER MANIPULATION WITH A SIMD MERGE INSTRUCTION - Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block. | 2013-07-18 |
20130185542 | EXTERNAL AUXILIARY EXECUTION UNIT INTERFACE TO OFF-CHIP AUXILIARY EXECUTION UNIT - An external Auxiliary Execution Unit (AXU) interface is provided between a processing core disposed in a first programmable chip and an off-chip AXU disposed in a second programmable chip to integrate the AXU with an issue unit, a fixed point execution unit, and optionally other functional units in the processing core. The external AXU interface enables the issue unit to issue instructions to the AXU in much the same manner as the issue unit would be able to issue instructions to an AXU that was disposed on the same chip. By doing so, the AXU on the second programmable chip can be designed, tested and verified independent of the processing core on the first programmable chip, thereby enabling a common processing core, which has been designed, tested, and verified, to be used in connection with multiple different AXU designs. | 2013-07-18 |
20130185543 | GENERAL PURPOSE EMBEDDED PROCESSOR - The invention provides an embedded processor architecture comprising a plurality of virtual processing units that each execute processes or threads (collectively, “threads”). One or more execution units, which are shared by the processing units, execute instructions from the threads. An event delivery mechanism delivers events—such as, by way of non-limiting example, hardware interrupts, software-initiated signaling events (“software events”) and memory events—to respective threads without execution of instructions. Each event can, per aspects of the invention, be processed by the respective thread without execution of instructions outside that thread. The threads need not be constrained to execute on the same respective processing units during the lives of those threads—though, in some embodiments, they can be so constrained. The execution units execute instructions from the threads without needing to know what threads those instructions are from. | 2013-07-18 |
20130185544 | PROCESSOR WITH INSTRUCTION VARIABLE DATA DISTRIBUTION - A vector processor includes a plurality of execution units arranged in parallel, a register file, and a plurality of load units. The register file includes a plurality of registers coupled to the execution units. Each of the load units is configured to load, in a single transaction, a plurality of the registers with data retrieved from memory. The loaded registers corresponding to different execution units. Each of the load units is configured to distribute the data to the registers in accordance with an instruction selectable distribution. The instruction selectable distribution specifies one of plurality of distributions. Each of the distributions specifies a data sequence that differs from the sequence in which the data is stored in memory. | 2013-07-18 |
20130185545 | HIGH-PERFORMANCE CACHE SYSTEM AND METHOD - A digital system includes a processor core and a cache control unit. The processor core can be coupled to a first memory containing data and a second memory with a faster speed than the first memory, and is configured to execute a segment of instructions having at least one instruction accessing the data from the second memory using a base register. The cache control unit is configured to be coupled to the first memory, the second memory, and the processor core to fill the data from the first memory to the second memory before the processor core executes the instruction accessing the data, and is further configured to examine the segment of instructions to extract instruction information containing at least data access instruction information and last register updating instruction information and to create a track corresponding to the segment of instructions based on the extracted instruction information. | 2013-07-18 |
20130185546 | Method For Checking the Operability of a Digital Signal Processing Unit of a Position Sensor and Position Encoder - A method for checking the operability of a digital signal processing unit of a position sensor, wherein the digital signal processing unit executes an instruction queue of N instructions one after another in sequences, wherein an additional number of x instructions is executed by the digital signal processing unit during each sequence, wherein the additional instructions are provided in a unit different from the memory, and that the results of the additional instructions are stored. The results of the additional instructions are read by a microcomputer. The results of the additional instructions are compared by the microcomputer with the expected results achieved by execution of identical additional instructions by the microcomputer or with expected results stored in the microcomputer. This includes a position encoder comprising a digital signal processing unit for calculating position information. | 2013-07-18 |
20130185547 | SIGNAL RESET CIRCUIT FOR WIRELESS COMMUNICATION SYSTEMS - A wireless network reset system is disclosed. The system couples or connects to a power supply line. A microcontroller software module senses a signal from a Wi-Fi module that indicates a halting of a processor function. A reset module executes a reset based on the halting of the processor function. | 2013-07-18 |
20130185548 | Multiple System Images for Over-The-Air Updates - In one embodiment, a mobile device performs an over-the-air firmware update by writing the updated firmware to a inactive system image partition, and rebooting the device. The security of the OTA update is maintained through checking a plurality of security signatures in an OTA manifest, and the integrity of the data is maintained by checking a hash value of the downloaded system image. | 2013-07-18 |
20130185549 | ELECTRONIC DEVICE AND BIOS UPDATING DEVICE THEREOF - An electronic device and a basic input/output system (BIOS) updating device thereof are provided. The electronic device includes a central processing unit (CPU), a chipset, a first interface circuit and a second interface circuit. The chipset is coupled to the CPU. The first interface circuit is coupled to a first memory and a second memory. The first memory includes a first BIOS file and the second memory includes a second BIOS file. The second interface circuit is coupled to the first interface circuit and an external storage device. When the external storage device includes a third BIOS file, a target memory is selected from the first memory and second memory according to a first rule and the target memory is updated using the third BIOS file. Thus, BIOS firmware of the electronic device can be safely updated. | 2013-07-18 |
20130185550 | METHOD AND SYSTEM FOR NAND FLASH SUPPORT IN AN AUTONOMOUSLY LOADED SECURE REPROGRAMMABLE SYSTEM - A system and method that enables secure system boot up with a restricted central processing unit (CPU). The system includes a memory, a segmenting device, and a security sub-system. The memory is a NAND flash memory with a block structure that comprises a guaranteed block and non-guaranteed blocks. The guaranteed block is guaranteed to be useable. A boot code is segmented into boot code segments and the boot code segments are stored separately in the guaranteed and non-guaranteed blocks. The security sub-system is configured to locate the boot code segments stored in the non-guaranteed blocks and validate them independently based on data in the guaranteed block. The security sub-system is further configured to assemble the boot code segments into the boot code and execute the boot code. | 2013-07-18 |
20130185551 | REVOCATION LIST UPDATE FOR DEVICES - In one embodiment, a method includes receiving a revocation request for revoking a model type of a device. A first computing device determines a list of device unit identifiers (UIDs) that are associated with the model type from a database. The device UIDs are for devices of the model type manufactured by a first entity. The method adds the list of device UIDs to a device revocation list and outputs the device revocation list to revoke a validity of secure information associated with devices associated with the list of device UIDs. | 2013-07-18 |
20130185552 | Device Verification for Dynamic Re-Certificating - A method for authenticating a device is provided. The method comprises receiving, by a network component, from the device, an access request and an encryption key; sending, by the network component, to the device, a request for at least one of current information associated with the device and an identification number associated with the device; receiving, by the network component, a response from the device; comparing, by the network component, the response with a known version of the at least one of current information associated with the device and identification number associated with the device; and determining, by the network component, that the device has passed an authenticity test when at least one of: current information included in the response matches the known version of the current information, and the identification number included in the response matches the known version of the identification number. | 2013-07-18 |
20130185553 | SYSTEM AND METHOD FOR ADMINISTERING DIGITAL CERTIFICATE CHECKING - Systems and methods for handling electronic messages. An electronic message that is associated with a digital certificate is to be processed. A decision whether to check the validity of the digital certificate is based upon digital certificate checking criterion. An IT administrator may provide to one or more devices configuration data that establishes the digital certificate checking criterion. | 2013-07-18 |
20130185554 | METHOD FOR ANALYZING CODED DATA STREAMS SIMULTANEOUSLY TRANSMITTED IN IP NETWORKS - One network protocol (RTP) each, having data packets (dp) comprising an expandable header (KE) is provided for a data stream (ds | 2013-07-18 |
20130185555 | SYSTEM AND METHOD FOR SECURE ERASE IN COPY-ON-WRITE FILE SYSTEMS - Disclosed herein are systems, methods, and non-transitory computer-readable storage media for a delayed secure deletion of files from a copy-on-write file system. A system configured to practice the method receives a change to a file, writes a copy of the file in a first block of a storage device, the copy including the change, determines whether the change meets a predetermined condition, adds an entry into a delayed secure deletion list when the change triggers the predetermined condition, the entry storing an address associated with the first block, and deletes the first block when another change to the file is received, wherein the another change triggers another predetermined event. | 2013-07-18 |
20130185556 | SYSTEM AND METHOD FOR SECURE COMMUNICATION - A system and methods for secure communication are disclosed. A network packet comprising encrypted network address comprising an unencrypted network address encrypted by a first GPS time and a first pseudo random number is received. The encrypted network address is decrypted using the first GPS time and the first pseudo random number to provide the unencrypted network address. The network packet is transmitted based on the unencrypted network address. | 2013-07-18 |
20130185557 | Detection of Invalid Escrow Keys - A secure hash, such as a Hash-based Message Authentication Code (“HMAC”), is generated using a piece of secret information (e.g., a secret key) and a piece of public information specific to each escrow key (e.g., a certificate hash or public key). Using the secret key ensures that escrow key validation data can only be generated by knowing the secret key, which prevents an attacker from generating the appropriate escrow key validation data. Using the certificate hash as the public data ties each escrow key validation data to a particular certificate, thereby preventing the attacker from simply copying the validation data from another escrow key. Any escrow key that is found to be invalid may be removed from the file container and a system audit log may be generated so that a company, individual, or other entity can be aware of the possible attempt at a security breach. | 2013-07-18 |
20130185558 | System and Method for Enabling Seamless Transfer of a Secure Session - An information handling system includes a memory and a processor to execute instructions stored in the memory, which causes the processor to at least: send identification information to a second information handling system in response to an identification request broadcast from the second information handling system via a short-range communication; receive first authentication information for a local application and a remote service from the second information handling system; receive a copy of the local application; authenticate a user for the copy of the local application and for the remote service prior to the user logging on to the information handling system; receive second authentication information from the user to access the information handling system; authenticate the user to the information handling system; and automatically initiate a secure session between the copy of the local application and the remote service when the user is authenticated to the information handling system. | 2013-07-18 |
20130185559 | SECURE COMMUNICATIONS BETWEEN DEVICES - A method of establishing secure communication between a first mobile computing device and a second mobile computing device includes generating a first self-signed key at the first mobile computing device, pairing the first device with a second device, the pairing including receiving user input of a passcode and after receiving the user input sending the first public key to the second mobile computing device and receiving a second public key from the second mobile computing device, storing the second public key in a database of trusted devices, the database of trusted devices being stored in the first mobile computing device, receiving in the first mobile computing device a list of mobile computing devices connected to a mobile network, matching the list of mobile computing device against the database of trusted devices, and establishing secure communication between the first mobile computing device and the second mobile computing device. | 2013-07-18 |
20130185560 | METHOD AND ARRANGEMENT FOR PROVISIONING AND MANAGING A DEVICE - A method, arrangement, and provisioning server in a Selected Home Operator (SHO) network for downloading a new Downloadable Universal Subscriber Identity Module (DLUSIM) to a communication device when the communication device changes from a first operator network to the SHO network. A manager of the communication device registers with the SHO network and transfers K | 2013-07-18 |
20130185561 | MANAGEMENT OF PUBLIC KEYS FOR VERIFICATION OF PUBLIC WARNING MESSAGES - Techniques are disclosed for managing one or more public keys used for verification of one or more messages transferred over a communication network associated with a public warning system. In one example, a method comprises the following steps. A computing device of a communication network obtains key material for at least one source of a message generated for a public warning system. The computing device also obtains an identity of the source. A public key is computed by the computing device from the key material and the identity of the source. The public key is thus useable by the computing device to verify a message received from the source that is digitally signed using a corresponding private key of the source. In one example, the computing device comprises user equipment. | 2013-07-18 |
20130185562 | HOST DEVICE, SEMICONDUCTOR MEMORY DEVICE, AND AUTHENTICATION METHOD - According to one embodiment, encrypted secret identification information (E-SecretID) and the key management information (FKB) are read from a memory device. Encrypted management key (E-FKey) is obtained using the key management information (FKB) and index information (k). The index information (k) and the encrypted management key (E-FKey) are transmitted to the semiconductor memory device. An index key (INK) is generated using the first key information (NKey) and the received index information (k). The encrypted management key (E-FKey) is decrypted using the index key (INK) to obtain management key (FKey), which is transmitted to the host device. | 2013-07-18 |
20130185563 | Multiple System Images for Over-The-Air Updates - In one embodiment, a mobile device performs an over-the-air firmware update by writing the updated firmware to a inactive system image partition, and rebooting the device. The security of the OTA update is maintained through checking a plurality of security signatures in an OTA manifest, and the integrity of the data is maintained by checking a hash value of the downloaded system image. | 2013-07-18 |
20130185564 | SYSTEMS AND METHODS FOR MULTI-LAYERED AUTHENTICATION/VERIFICATION OF TRUSTED PLATFORM UPDATES - In accordance with the present disclosure, a system and method for multilayered authentication of trusted platform updates is described. The method may include storing first cryptographic data in a personality module of an information handling system, with the first cryptographic data corresponding to a verified firmware component. A second cryptographic data may also be determined, with the second cryptographic data corresponding to an unverified firmware component. The unverified firmware component may be stored in a memory element of the information handling system, and the second cryptographic data may be determined using a processor of the information handling system. The method may further include determining if the first cryptographic data matches the second cryptographic data and updating firmware in the information handling system with the unverified firmware component if the first cryptographic data matches the second cryptographic data, and the unverified firmware component includes a digital signature of a manufacturer. | 2013-07-18 |
20130185565 | Efficient, High Volume Digital Signature System for Medical and Business Applications - The system relates to a method for collecting signatures from pre-validated signers. In one aspect of the method, a pre-validated signer's signature is affixed to an electronic document in an appropriate location after the pre-validated signer authorizes the use of his or her signature. | 2013-07-18 |
20130185566 | SYSTEM AND METHOD FOR SECURING DATA WHILE MINIMIZING BANDWIDTH - Systems and methods for securing data are disclosed. A method for securing data can comprise processing a data block to generate a signature, processing the signature to generate a reduced signature, transmitting the data block to a recipient, and transmitting the reduced signature to the recipient. | 2013-07-18 |
20130185567 | Method or process for securing computers or mobile computer devices with a contact or dual-interface smart card - A method or system providing for the persistence of a computer session upon removal of a contact or dual-interface smart card from a smart card reader and locking, logging off, or disconnecting from the session when the contact or dual-interface smart card is re-presented to the smart card reader. | 2013-07-18 |
20130185568 | INFORMATION PROCESSING SYSTEM - An information processing system includes an information processing device and a portable terminal. The information processing device includes a card processing section that communicates with an IC chip of an IC card (card IC chip), and when security is satisfied between the information processing device and the card IC chip, performs information processing function of the card IC chip. Authentication processing between an IC chip (terminal IC chip) of the portable terminal and the card IC chip is performed through the card processing section, and secure communication is provided between the terminal IC chip and the card IC chip through the card processing section when the authentication processing is successful. Information input on the portable terminal is transmitted to the card IC chip through the secure communication. In this way, high user convenience can be achieved and increased security can also be achieved for the entire system. | 2013-07-18 |
20130185569 | DATA PROTECTION SYSTEM AND METHOD BASED ON CLOUD STORAGE - A data protection system implemented by a data protection device divides original data of a user into a plurality of data packets, and allots a sequential number to each second data. The system encrypts each of the data packets in sequence according to the allotted number of each of the data packets. After each of the data packets has been encrypted, the system moves each encrypted data packet from the data protection device to a cloud storage device in communication with the data protection device through a network. | 2013-07-18 |
20130185570 | Providing Per Core Voltage And Frequency Control - In one embodiment, the present invention includes a processor having a plurality of cores and a control logic to control provision of a voltage/frequency to a first core of the plurality of cores independently of provision of a voltage/frequency to at least a second core of the plurality of cores. In some embodiments, the voltages may be provided from one or more internal voltage regulators of the processor. Other embodiments are described and claimed. | 2013-07-18 |
20130185571 | System and Method for Providing Power-Save Operation in an In-Home Communication Network - A first device of a multimedia over coax alliance (MoCA) network may grant a second device of the MoCA network permission to enter a power-saving state. While the second device is in the power-saving mode, the first device may grant bandwidth to the second device during one or more predetermined timeslots. The bandwidth may be granted without a corresponding reservation request from the second device. While the second device is in the power-saving state, it may track time utilizing a clock that is synchronized to the system time of the MoCA network, and transmit during one or more of the predetermined timeslots without first transmitting a corresponding reservation request. The second device may utilize a first modulation profile when not operating in the power-saving state, and utilize a second modulation profile when operating in the power-saving state. | 2013-07-18 |
20130185572 | METHOD AND APPARATUS FOR ACHIEVING ENERGY SAVING OF DATA SWITCHING DEVICE - Embodiments of the present disclosure provide a method and an apparatus for achieving energy saving of a data switching device. The apparatus acquires a working model, where the working model includes correspondence between a working mode and time within a working cycle of the data switching device, the working mode can identify a bandwidth capacity in the working mode, and controls a data processing module in the data switching device to work according to the working model, so that the data processing module works under a bandwidth capacity identified by a corresponding working mode at the time. In the technical solutions of the embodiments of the present disclosure, the power consumption of the data processing module in the data switching device can be reduced in the idle time period, thereby effectively achieving energy saving. | 2013-07-18 |
20130185573 | IMAGE FORMING APPARATUS AND CONTROL METHOD FOR EXECUTING A PROXY IN RESPONSE TO A HEARTBEAT - An image forming apparatus automatically recognizes and responds to an encrypted heartbeat packet only with a small amount of calculation, without causing a sub control unit to execute an SSL/TLS decryption process. As a result, the image forming apparatus can execute a proxy response with less power consumption. | 2013-07-18 |
20130185574 | SEMICONDUCTOR DEVICE, RADIO COMMUNICATION TERMINAL USING THE SAME, AND INTER-CIRCUIT COMMUNICATION SYSTEM - Disclosed as one aspect is a semiconductor device including a transmission/reception interface that is used for transmission and reception of data, a processing unit that processes the data, a monitoring unit that monitors received data and detects a specific frame allowed to be transmitted regardless of a state of a circuit to transmit/receive the data, and a power management unit that controls power consumption of a circuit including the processing unit. | 2013-07-18 |
20130185575 | SEMICONDUCTOR DEVICE FOR SUPPLYING POWER SUPPLY VOLTAGE TO SEMICONDUCTOR DEVICE - A semiconductor device includes first, second and third power supply terminals respectively supplied with first, second and third power supply voltages. The semiconductor device also includes a first terminal connectable to a host device and a second terminal connectable to a peripheral device. The semiconductor device also includes a first circuit block connected to the first terminal and the first power supply terminal and receiving data output from the host device based on the first power supply voltage, a second circuit block connected to the second terminal and the third power supply terminal and receiving data output from the peripheral device based on the third power supply voltage, and a third circuit block connected to the second power supply terminal and controlling operation of the first circuit block and the second circuit block based on the second power supply voltage. | 2013-07-18 |
20130185576 | POWER PROFILING APPLICATION FOR MANAGING POWER ALLOCATION IN AN INFORMATION HANDLING SYSTEM - A method, system, and software instructions for allocating power in a information handling system are operable to respond to a power profiling request by transitioning a processing resource to a first power consumption state and obtaining and storing a first power consumption value. The first power consumption value is then retrieved and used to allocate power to the first processing resource in response to a power on request. The first power consumption state may be a state in which power consumption approximates a maximum power consumption. The processing resource may be further transitioned to a second power consumption state and a second power consumption value obtained. The second power consumption state may be a reduced performance state. Thereafter, responsive to determining that the system lacks sufficient power budget to fulfill a pending request for power, the processing resource is throttled and power is allocated using the second power consumption value. | 2013-07-18 |
20130185577 | METHOD, APPARATUS, AND SYSTEM FOR OPTIMIZING FREQUENCY AND PERFORMANCE IN A MULTIDIE MICROPROCESSOR - With the progress toward multi-core processors, each core is can not readily ascertain the status of the other dies with respect to an idle or active status. A proposal for utilizing an interface to transmit core status among multiple cores in a multi-die microprocessor is discussed. Consequently, this facilitates thermal management by allowing an optimal setting for setting performance and frequency based on utilizing each core status. | 2013-07-18 |
20130185578 | SEMICONDUCTOR DEVICE AND CONTROL METHOD - A semiconductor device includes a detector that receives an input signal whose characteristics fluctuate depend on the standby mode state, compares the input signal amplitude with a specific threshold amplitude, and outputs a detector output signal that shows whether or not the amplitude of the applicable input signal is above the specified threshold amplitude; and an intermittent operation control circuit that along with receiving the detector output, also receives a first signal showing which mode among the multiple standby mode states is in, and sets the detector to the continuously on (enable) mode state when the input signal is above the specified threshold amplitude, and in all other cases intermittently operates the detector depend on the characteristics of the input signal in the mode shown by the first signal. | 2013-07-18 |
20130185579 | Microarchitecture Controller For Thin-Film Thermoelectric Cooling - A device having multiple cores executes an algorithm to control Thin-Film Thermoelectric Coolers (TFTEC) that employ the Peltier effect to remove heat from the various cores of the multi-core processor. The algorithms may combine Thread Migration (TM) and Dynamic Voltage/Frequency Scaling (DVFS) to provide Dynamic Thermal Management (DTM) and TFTEC control. | 2013-07-18 |
20130185580 | INSTRUCTION FOR ENABLING A PROCESOR WAIT STATE - In one embodiment, the present invention includes a processor having a core with decode logic to decode an instruction prescribing an identification of a location to be monitored and a timer value, and a timer coupled to the decode logic to perform a count with respect to the timer value. The processor may further include a power management unit coupled to the core to determine a type of a low power state based at least in part on the timer value and cause the processor to enter the low power state responsive to the determination. Other embodiments are described and claimed. | 2013-07-18 |
20130185581 | Efficient Code Dispatch Based on Performance and Energy Consumption - A multiplexer selects one of a plurality of sense outputs from sensing circuits. Each of the sensing circuits is located in a corresponding one of voltage regulators supplying power to processors in a subsystem. The corresponding one of voltage regulators is associated with one of processors. An analog-to-digital converter converts the selected one of the plurality of sense outputs to a digital parameter representing energy consumption of the one of the processors associated with the corresponding one of the voltage regulators. The energy consumption is used for dispatching dynamically generated code. | 2013-07-18 |
20130185582 | STORAGE APPARATUS, CONTROLLER MODULE, AND STORAGE APPARATUS CONTROL METHOD - A storage apparatus includes first and second controller modules. The first controller module monitors power states of the first and second controller modules. When the monitoring results indicate that the power state of the first controller module is an ON state and the power state of the second controller module is an ON processing state in which an ON process of switching from OFF to ON is being executed, the first controller module maintains the power state of the first controller module upon detection of a power control signal for controlling the power state of the first controller module. | 2013-07-18 |
20130185583 | DISTRIBUTING INFORMATION - Example embodiments disclosed herein relate to distributing information. A set of information about components of a computing device is retrieved from a low-level system of the computing device. Programs are determined to be sent data based on the set of information. | 2013-07-18 |
20130185584 | INFORMATION PROCESSOR AND CONTROL METHOD OF THE SAME - Disclosed herein is an information processor including: a processing section adapted to perform a predetermined process on a data signal output in synchronism with one of positive and negative edges of a clock signal and output an execution result thereof; a holding section adapted to hold the execution result in synchronism with the other of the positive and negative edges; a timing determination section adapted to determine whether a grace period lasting until the execution result is held by the holding section meets a setup time of the holding section; a clock control section adapted, if it is determined that the grace period does not meet the setup time, to control at least the timing of either the positive or negative edge in such a manner that the grace period meets the setup time; and a clock generation section adapted to generate the clock signal according to the controlled timing. | 2013-07-18 |
20130185585 | USB BASED SYNCHRONIZATION AND TIMING SYSTEM - A synchronization apparatus, comprising: a USB device having a USB microcontroller, circuitry for observing USB traffic, and circuitry for decoding from a USB data stream a periodic data structure (such as a clock carrier signal) containing information about a distributed clock frequency and phase and outputting a decoded carrier signal; and circuitry for receiving the decoded carrier signal, for generating a software interrupt upon receipt of a predefined data packet (such as a SOF packet) and for passing the software interrupt to the USB microcontroller; wherein the USB microcontroller is configured to respond to the software interrupt (such as with an interrupt service routine provided therein) by generating an output signal adapted to be used as a synchronization reference signal. | 2013-07-18 |
20130185586 | SELF-HEALING OF NETWORK SERVICE MODULES - Methods, systems, and devices are described for managing virtual network services provided to a network. A number of processors in a self-contained network services module may execute a number of separate network service application instances associated with providing network services to the network. State information for each network service application instance may be stored within a shared memory, and a fault in one of the network service application instances may be identified based on the stored state information. The identified fault may be dynamically remedied in the one of the network service application instances. | 2013-07-18 |
20130185587 | Controlling a Solid State Disk (SSD) Device - A mechanism is provided for controlling a solid state disk. A failure detector detects a failure in the solid state disk. Responsive to failure detector detecting a failure, a status degrader sets a degraded status indicator for the solid state disk. Responsive to the degraded status indicator, a degraded status controller maintains the solid state disk in operation in a degraded operation mode. | 2013-07-18 |
20130185588 | QUERY EXECUTION AND OPTIMIZATION WITH AUTONOMIC ERROR RECOVERY FROM NETWORK FAILURES IN A PARALLEL COMPUTER SYSTEM WITH MULTIPLE NETWORKS - A database query execution monitor determines if a network error or low performance condition exists and then where possible modifies the query. The query execution monitor then determines an alternate query execution plan to continue execution of the query. The query optimizer can re-optimize the query to use a different network or node. Thus, the query execution monitor allows autonomic error recovery for network failures using an alternate query execution. The alternate query execution could also be determined at the initial optimization time and then this alternate plan used to execute a query in the case of a particular network failure. | 2013-07-18 |
20130185589 | MIRRORING DISK DRIVE SECTORS - A recoverable error associated with a first disk drive sector is determined. Data of the first disk drive sector is duplicated to a mirrored sector in response to the recoverable error. The first disk drive sector continues to be used to store the data after the recoverable error is determined. | 2013-07-18 |
20130185590 | Method in a Gaming Machine for Providing Data Recovery - Disclosed is a gaming machine capable of data restoration. | 2013-07-18 |
20130185591 | METHODS, APPARATUS AND ARTICLES OF MANUFACTURE TO PERFORM ROOT CAUSE ANALYSIS FOR NETWORK EVENTS - Example methods, apparatus and articles of manufacture to perform root cause analysis for network events are disclosed. An example method includes retrieving a symptom event instance from a normalized set of data sources based on a symptom event definition; generating a set of diagnostic events from the normalized set of data sources which potentially cause the symptom event instance, the diagnostic events being determined based on dependency rules; and analyzing the set of diagnostic events to select a root cause event based on root cause rules. | 2013-07-18 |
20130185592 | AUTOMATIC PROBLEM DIAGNOSIS - For automatic problem diagnosis, a data collector module collects log data comprising code sets from a plurality of components in a data processing system. An analysis module translates the log data into at least one predefined symptom. Each symptom is associated with at least one code set of the log data. The analysis module selects from a knowledge base at least one problem that includes each symptom. The analysis module further calculates an influence factor for each problem, and ranks each problem from most likely to least likely based on the influence factor of the problem. | 2013-07-18 |
20130185593 | ADAPTIVE DEVICE-INITIATED POLLING - A method includes periodically sending a polling call to an enterprise system outside the firewall at a first polling rate during normal operating conditions, monitoring for a fault condition, periodically sending polling calls to the device outside the firewall at a second polling rate when a fault condition is detected, the second polling rate being higher than the first polling rate. The second polling rate is used as result of a fault condition. The method also includes sending a problem report with the polling calls when the fault condition is detected. | 2013-07-18 |
20130185594 | AUTOMATED TESTING OF MECHATRONIC SYSTEMS - An arrangement for providing integrated, model-based testing of industrial systems in the form of a model-based test design module, a test execution engine and an automated test infrastructure (ATI) component. The ATI component includes a keyword processor that interfaces with test commands created by the design module to implement the testing of a specific industrial system. Configuration and deployment information is also automatically created by the design module and used by the ATI component to set up and control the specific industrial system being tested. | 2013-07-18 |
20130185595 | Analysis of Tests of Software Programs Based on Classification of Failed Test Cases - A solution is proposed for analyzing a test of a software program comprising a plurality of software components, the test comprising a plurality of test cases each one for exercising a set of corresponding exercised software components. A corresponding method comprises the steps of receiving an indication of each failed test case whose current execution has failed, retrieving a suspicion attribute of each failed test case indicative of a change to the corresponding exercised software components since a previous execution of the failed test case, retrieving a change attribute of each failed test case indicative of a change to the failed test case since the previous execution thereof, retrieving a regression attribute of each failed test case indicative of a regression of the failed test case since the previous execution thereof, and classifying each failed test case into a plurality of disjoint classes according to the corresponding suspicion attribute, change attribute and regression attribute. | 2013-07-18 |
20130185596 | Serialized Error Injection Into a Function Under Test - System, and computer program product embodiments for triggering error injection into a function under test using a serialization resource are provided. A test process invokes the function under test immediately after relinquishing exclusive control of the serialization resource. An error-injection process injects the error into the running function after gaining exclusive control of the serialization resource from the test process. The error-injection process may add a delay to inject the error. If the processes are repeated, the error-injection process may vary the delay, perhaps randomly, over a specified time window to thoroughly exercise the function's error recovery routine. | 2013-07-18 |
20130185597 | SERVER THROTTLED CLIENT DEBUGGING - Systems and methods of debugging client applications may provide for detecting a runtime error in a first version of a client application, and obtaining a second version of the client application server in response to the runtime error. The second version of the client application may be used to conduct a diagnosis of the runtime error. | 2013-07-18 |
20130185598 | MULTI-TIER DETECTION AND DECODING IN FLASH MEMORIES - Methods and apparatus are provided for multi-tier detection and decoding in flash memory devices. Data from a flash memory device is processed by obtaining one or more read values for at least one bit in a given page of the flash memory device; converting the one or more read values for the at least one bit to a reliability value; performing an initial decoding of the at least one bit in a given page using the reliability value; and performing an additional decoding of the at least one bit in the given page if the initial decoding is not successful, wherein the additional decoding uses one or more of additional information for the given page and at least one value for at least one bit from at least one additional page. | 2013-07-18 |
20130185599 | DETECTION AND DECODING IN FLASH MEMORIES USING CORRELATION OF NEIGHBORING BITS - Methods and apparatus are provided for detection and decoding in flash memories using a correlation of neighboring bits or errors in neighboring bits. Data from a flash memory device is processed by obtaining one or more read values for a plurality of bits in a given page of the flash memory device; converting the one or more read values for the plurality of bits to a reliability value for a bit among said plurality of bits based on a probability that a data pattern was written to the plurality of bits given that a particular pattern was read from the plurality of bits; and decoding the bit in the page using the reliability value. The probability that the data pattern was written to the plurality of bits given that the particular pattern was read from the plurality of bits is obtained from one or more tables. | 2013-07-18 |
20130185600 | THREAD BASED DYNAMIC DATA COLLECTION - Dynamically collecting data pertaining to a program execution. A method can include monitoring execution of the program in a plurality of threads and, responsive to identifying an exception triggered by the program execution in a first of the plurality of threads, initiating at least one data collector to collect data exclusively relevant to the program execution in the first thread. | 2013-07-18 |
20130185601 | Compact Function Trace - In accordance with one aspect of the invention, a system for generating compact function trace data for leaf functions includes a central processing unit (CPU), configured to output program flow information needed for generating a program flow trace, and a trace unit, coupled to the CPU. The trace unit is configured to receive the program flow information from the CPU for generating compact function trace data. The trace unit further comprises a first output mode and a second output mode and is further configured to select either the first output mode or the second output mode for generating compact function trace data. | 2013-07-18 |
20130185602 | HEAP DUMP OCCURRENCE DETECTION - Detection of heap dump occurrence is facilitated through maintenance of a heap dump location registry. The heap dump location registry indicates tools for which heap dump occurrence is to be detected. Based on periodically referencing the heap dump location registry, it is determined whether heap dump of a tool of the one or more tools has occurred. In one embodiment, startup and shutdown events of the tool are tracked to update execution status and process identifiers in the heap dump location registry, and the periodically references determines based on the indicators whether heap dump has occurred for the tool. In another embodiment, a heap dump location for heap dumps of the tool is obtained from the registry and the heap dump location is checked for the presence of heap dump files, which presence indicates occurrence of a heap dump for the tool. | 2013-07-18 |
20130185603 | FAULT TOLERANCE FOR COMPLEX DISTRIBUTED COMPUTING OPERATIONS - A method for enabling a distributed computing system to tolerate system faults during the execution of a client process. The method includes instantiating an execution environment relating to the client process; executing instructions within the execution environment, the instructions causing the execution environment to issue further instructions to the distributing computing system, the further instructions relating to actions to be performed with respect to data stored on the distributed computing system. An object interface proxy receives the further instructions and monitors the received to determine if the execution environment is in a desired save-state condition; and, if so, save a current state of the execution environment in a data store. | 2013-07-18 |
20130185604 | FAULT TOLERANT STABILITY CRITICAL EXECUTION CHECKING USING REDUNDANT EXECUTION PIPELINES - A circuit arrangement and method utilize existing redundant execution pipelines in a processing unit to execute multiple instances of stability critical instructions in parallel so that the results of the multiple instances of the instructions can be compared for the purpose of detecting errors. For other types of instructions for which fault tolerant or stability critical execution is not required or desired, the redundant execution pipelines are utilized in a more conventional manner, enabling multiple non-stability critical instructions to be concurrently issued to and executed by the redundant execution pipelines. As such, for non-stability critical program code, the performance benefits of having multiple redundant execution units are preserved, yet in the instances where fault tolerant or stability critical execution is desired for certain program code, the redundant execution units may be repurposed to provide greater assurances as to the fault-free execution of such instructions. | 2013-07-18 |
20130185605 | IMAGE FORMING APPARATUS, TERMINAL APPARATUS, INFORMATION PROCESSING METHOD, INFORMATION PROCESSING PROGRAM AND COMPUTER READABLE RECORDING MEDIUM - An apparatus has a display for an operation operated by an application program. The apparatus includes an operation screen displayer that displays an operation screen in the display. The application program is an object to be operated in the operation screen. The apparatus also includes a rule violation displayer that displays that a rule violation has occurred in the display, the rule violation occurring when a processing request from the application program exceeds a predetermined allowable range of an operation condition. A manager switches the display, by the rule violation displayer, from the operation screen to a screen showing a rule violation notice that the rule violation has occurred, in response to the processing request, if it is determined that the processing request is the rule violation based on information as to an operation authority permitted to the application program. | 2013-07-18 |
20130185606 | SYSTEMS AND METHODS FOR PROACTIVELY REFRESHING NONVOLATILE MEMORY - System and methods for proactively refreshing portions of a nonvolatile memory are disclosed. A memory system may proactively refresh a portion of nonvolatile memory based on data associated with the portion. The data may include the time elapsed since the portion was last refreshed, the number of times the portion has been cycled, and the average operating temperature of the nonvolatile memory. A portion of nonvolatile memory meeting certain criteria determined from that data may be proactively refreshed during a downtime when the nonvolatile memory is not otherwise being accessed. | 2013-07-18 |
20130185607 | SCAN TEST CIRCUITRY CONFIGURED FOR BYPASSING SELECTED SEGMENTS OF A MULTI-SEGMENT SCAN CHAIN - An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells, wherein the scan chain is separated into a plurality of scan segments with each such segment comprising a distinct subset of two or more of the plurality of scan cells. The scan test circuitry further comprises scan segment bypass circuitry configured to selectively bypass one or more of the scan segments in a scan shift mode of operation. The scan segment bypass circuitry may comprise a plurality of multiplexers and a scan segment bypass controller. The multiplexers are arranged within the scan chain and configured to allow respective ones of the scan segments to be bypassed responsive to respective bypass control signals generated by the scan segment bypass controller. | 2013-07-18 |
20130185608 | SCAN CHAIN ACCESS IN 3D STACKED INTEGRATED CIRCUITS - Stacked integrated circuits (ICs) having a base component and secondary component are tested. The base component has a scan input pad, a scan output pad, a base scan chain, and a base chain access block including a base chain select multiplexor and a base bypass multiplexor. The secondary component has a secondary scan chain and a secondary chain access block including a secondary chain select multiplexor and a secondary bypass multiplexor. The secondary chain select multiplexor is configured to receive input directly from the base component and another component. The base and secondary chain access blocks are configured to selectively access the base scan chain and/or the secondary scan chain. | 2013-07-18 |
20130185609 | NONVOLATILE MEMORY SYSTEM - A nonvolatile memory system is provided. The nonvolatile memory device includes a multi-level memory array and a page buffer; and a memory controller configured to control first page data to be to read from the multi-level memory array and stored in the page buffer, a first error bit of the first page data to be detected, an error of the first page data stored in the page buffer to be to corrected using first corrected data having an error corrected in the first error bit, and a first refresh program operation of the error-corrected first page data to be performed on the multi-level memory array. | 2013-07-18 |
20130185610 | JOINT ENCODING AND DECODING METHODS FOR IMPROVING THE ERROR RATE PERFORMANCE - Joint encoding and decoding methods for improving the error rate performance are described. In one aspect, the systems and methods determine values and positions of L desired symbols. In encoding unit receives data symbols for encoding. The encoding unit calculates, responsive to receiving the data symbols, values and positions of H help symbols. The encoding unit inserts the help symbols into the data symbols at respective help symbols positions, thereby generating new data symbols. Encoding unit encodes the new data symbols to produce a codeword C′ that contains the L desired symbols. The codeword C′ is communicated to a decoder that is instructed to explore some or all L desired symbols in C′. | 2013-07-18 |
20130185611 | BIT ERROR CORRECTION FOR REMOVING AGE RELATED ERRORS IN A BIT PATTERN - A bit error corrector includes an aging bit pattern memory operable to store at least one aging bit pattern which conveys aging-related effects within a succession of uncorrected bit patterns, a bit pattern modifier operable to modify a current, uncorrected bit pattern using the at least one aging bit pattern and generate a modified bit pattern, and a bit pattern comparator operable to compare the current uncorrected bit pattern with a corrected bit pattern which is based on the modified bit pattern and determine a corresponding comparative bit pattern. An aging bit pattern determiner is operable to recursively determine a new aging bit pattern based on the at least one aging bit pattern and the comparative bit pattern, and store the new aging bit pattern in the aging bit pattern memory for use during modification of a subsequent uncorrected bit pattern by the bit pattern modifier. | 2013-07-18 |
20130185612 | FLASH MEMORY SYSTEM AND READ METHOD OF FLASH MEMORY SYSTEM - A read method in a flash memory system containing a flash memory and a memory controller includes updating a selected one of indexes of a selected one of blocks of the flash memory, in a wear-out table for indexing each of the blocks of the flash memory, and setting a start read level to start read retry on the selected block by referring to a read retry table corresponding to a wear-out degree included in the selected index when a current request of read retry on the selected block is received. | 2013-07-18 |
20130185613 | SYSTEMS, METHODS, APPARATUS AND COMPUTER PROGRAM PRODUCTS FOR HIGHLY RELIABLE FILE DELIVERY USING COMPOUND AND BRAIDED FEC ENCODING AND DECODING - Systems, methods, apparatus and computer program products provide highly reliable file delivery using a combination of packet-level FEC on source data packets which are arranged in matrices, where encoding is performed on both rows and columns or on rows, columns and diagonals. | 2013-07-18 |
20130185614 | Lost Real-Time Media Packet Recovery - Systems, methods and computer program products for facilitating the recovery of lost real-time media packets within a computer network real-time application implementing Forward Error Control (FEC), such that server performance is not affected from a CPU and memory perspective, are disclosed. In an embodiment, a conference server that is part of a communication network compliant with the Real Time Transport Protocol (RTP) is able to avoid regenerating FEC packets by not performing any FEC coding operation on the packets unless it is flagged to indicate regeneration via an FEC (e.g., Reed-Solomon) coding is necessary. Absent the flag, the conference server updates the received FEC packet as per the RTP and transmits the packet to its ultimate destination. Such disclosed systems, methods and computer program products are independent of the nature of the media being protected and flexible enough to support a wide variety of FEC techniques. | 2013-07-18 |
20130185615 | SOFT OUTPUT VITERBI DETECTOR WITH ERROR EVENT OUTPUT - A first sequence of states associated with a surviving path and a second sequence of states associated with a non-surviving path are determined. A possible error event is determined based at least in part on the first sequence of states and the second sequence of states. The first sequence of states is replaced with the second sequence of states by applying the possible error event to the first sequence of states. | 2013-07-18 |
20130185616 | METHOD AND DEVICE FOR IMPLEMENTING VITERBI DECODING - The disclosure provides a method and device for implementing Viterbi decoding. The method comprises the following steps: calculating branch path measurement values of received code words and reference code words; parallel accumulating the branch path measurement values and measurement values corresponding to states to obtain accumulated values according to a state transition diagram, selecting a maximum accumulated value as a new measurement value of a next state, and saving all survival path selection results until data for decoding ends; and starting traceback from a final state to obtain decoded data according to the survival path selection results. In the disclosure, by modifying the traditional serial or serial-parallel mixed mode for calculating accumulated path measurement values to a multi-path fully-parallel calculation mode, the throughput rate of the system data is improved, and the decoding delay is merely in us level. In the disclosure, the traditional mode of sliding window traceback is also changed, traceback whose depth is tow times of the encoding length is only once, but the second section traceback data in the traceback depth is only valid. The accumulated values and state measurement values needn't to be stored, the method is simple and efficient, and the performance of the system is also improved. | 2013-07-18 |
20130185617 | WIRELESS BACKHAUL COMMUNICATION - A method for wireless backhaul communication comprising receiving, by a wireless backhaul transmitter, a data stream in a bit format and generating, by the wireless backhaul transmitter using a single-carrier block transmission scheme, a radio frame to include a plurality of physical data channel (PDCH) blocks, a pilot signal (PS) block and a physical control channel (PCCH) block with each block type pre-appended with a cyclic prefix (CP). A length of the PS block in symbols, a length of the PCCH block in symbols and a length of the PDCH block in symbols is determined by a frequency band, a bandwidth, and a channel condition. The wireless backhaul transmitter then transmits the radio frame. | 2013-07-18 |
20130185618 | SYSTEMS AND METHODS FOR MOBILE IMAGE CAPTURE AND PROCESSING - In various embodiments, methods, systems, and computer program products for processing digital images captured by a mobile device are disclosed. Myriad features enable and/or facilitate processing of such digital images using a mobile device that would otherwise be technically impossible or impractical, and furthermore address unique challenges presented by images captured using a camera rather than a traditional flat-bed scanner, paper-feed scanner or multifunction peripheral. | 2013-07-18 |
20130185619 | VALUE-DRIVEN VISUALIZATION PRIMITIVES FOR TABULAR DATA OF SPREADSHEETS - A method for visually enhancing display of tabular data of an electronic spreadsheet is disclosed. The method includes obtaining at least one data value from the tabular data and computing a visual parameter responsive to the at least one data value. The visual parameter is a number within a range of numbers and is determined according to one or more of: a user-specified numerically calculated mathematical function, a user-specified visual effect, a user-specified range of visual effect variation, and a user-specified range of data value. The visual effect of at least a portion of the tabular data is controlled according to the visual parameter and rendered to visually supplement the display of the portion of the tabular data responsive to the value of the numerically calculated mathematical function. One or more variations of the visual effect are automatically calculating without requiring user input, responsive to the at least one data value. | 2013-07-18 |
20130185620 | LADDER PROGRAM CREATION APPARATUS - A ladder program creation apparatus may include a command listing table storage unit configured to store a command listing table, the command listing table registering standard command information and custom ladder command information, a custom ladder command information creation unit configured to create the custom ladder command information based on an operation by user, and a custom ladder command information storage control unit configured to register the custom ladder command information, which has been created by the custom ladder command information creation unit, and the standard command information in the command listing table. | 2013-07-18 |
20130185621 | DOCUMENT RENEWAL AND TRANSLATION - Methods, systems and program products for renewing documents relating to an agreement between two entities. Content from an existing document is extracted, the existing document having been created from component documents. A selection of one or more updated component documents is received. An updated document is then generated based on the extracted content from the received document and the received selection of one or more updated component documents, wherein the updated document defines a revised agreement between the two entities. | 2013-07-18 |
20130185622 | METHODS AND SYSTEMS FOR HANDLING ANNOTATIONS AND USING CALCULATION OF ADDRESSES IN TREE-BASED STRUCTURES - This application relates to calculating addresses of modifications to tree-based structures and storing some of the addresses in a manner that allows the modifications to be applied, sustained, modified, and removed independently from one another. In some embodiments, the tree-based structures may define documents, including web documents, and the modifications may include annotations. In some embodiments, the addresses may include locations of the annotations within the documents. Methods and systems disclosed herein also include improved methods and systems for handling annotations. Some such methods and systems operate in connection with handling addresses associated with tree-based structures, while others can function independently of tree-based structures. Related user interfaces, applications, and computer program products are disclosed. | 2013-07-18 |
20130185623 | Instructing web clients to ignore scripts in specified portions of web pages - A web client is controlled to actively ignore scripts in certain portions of a web document using control instructions in the form of a special pair of markup language “tags.” A tag pair of this type is defined by a first tag, and a second tag paired with the first tag to form the tag pair. Each of the first and second tags includes a same identifier, and the tag pair is adapted to be recognized by a browser interpreter to instruct the web client to ignore given information located with the tag pair. Thus, when a web document is received by a web client, it is parsed (by the interpreter) in the usual manner. Upon determining that the tag pair is present, the browser bypasses (ignores) given information (typically, a script) located with the tag pair. Bypassing the script reduces the possibility that the script can be used for malicious purposes, such as an XSS attack. | 2013-07-18 |
20130185624 | PROVIDING DIRECT MANIPULATION OF AN ANALYTICS DATA VISUALIZATION WITHIN AN ANALYTICS REPORT - A direct manipulation event associated with a chart of an analytics report can be detected. The event can be a user interface input and the chart can be an information graphic. The graphic can be a graphically rendered HTML compliant element and a data set. The report can conform to a JAVASCRIPT OBJECT NOTATION (JSON) format. The analytics report can be presented within a browser. An action can be run responsive to the detecting. The action can be an immediate rendering of the graphic based on the event. When the action executes a request for data not in the data set data from a different data set can be obtained. When the action executes a request for data in the data set, the data from the data set can be automatically retrieved. The analytics data can be immediately rendered as a chart within the canvas element of an HTML document. | 2013-07-18 |
20130185625 | SYSTEM AND METHOD FOR INTELLIGENTLY SIZING CONTENT FOR DISPLAY - The present design deploys nonstandard graphic content to a user. The design determines, using a computing device, mandatory content on an existing page, determines existing page attributes from code associated with the existing page, and establishes dynamically created zones on a target page for the nonstandard graphic content based on the mandatory content and existing page attributes. The design further incorporates the nonstandard graphic content with the mandatory content on the existing page to form the target page and provides an indication to transmit the target page including the nonstandard graphic content to the user. | 2013-07-18 |
20130185626 | METHOD, TERMINAL AND COMPUTER-READABLE RECORDING MEDIUM FOR COMPILING JAVASCRIPT INCLUDED IN WEB APPLICATION USING Ahead-Of-Time (AOT) - The present invention relates to a method for compiling JavaScript included in a web application ahead of time (AOT). The method includes the steps of: (a) allowing a user terminal to acquire and unpackage the web application; and (b) allowing the user terminal to compile JavaScript included in the web application by referring to a platform thereof and create a form of machine code executable thereon, before the web application runs thereon. In accordance with the present invention, JavaScript included in the web application can be compiled in the form of machine code executable on a platform of the user terminal by referring to the platform where the web application is able to run. | 2013-07-18 |