32nd week of 2009 patent applcation highlights part 55 |
Patent application number | Title | Published |
20090198967 | METHOD AND STRUCTURE FOR LOW LATENCY LOAD-TAGGED POINTER INSTRUCTION FOR COMPUTER MICROARCHITECHTURE - A methodology and implementation of a load-tagged pointer instruction for RISC based microarchitecture is presented. A first lower latency, speculative implementation reduces overall throughput latency for a microprocessor system by estimating the results of a particular instruction and confirming the integrity of the estimate a little slower than the normal instruction execution latency. A second higher latency, non-speculative implementation that always produces correct results is invoked by the first when the first guesses incorrectly. The methodologies and structures disclosed herein are intended to be combined with predictive techniques for instruction processing to ultimately improve processing throughput. | 2009-08-06 |
20090198968 | Method, Apparatus and Software for Processing Software for Use in a Multithreaded Processing Environment - A method, apparatus and software for processing software code for use in a multithreaded processing environment in which lock verification mechanisms are automatically inserted in the software code and arranged to determine whether a respective shared storage element is locked prior to the use of the respective shared storage element by a given processing thread in a multithreaded processing environment. | 2009-08-06 |
20090198969 | Microprocessor systems - A microprocessor pipeline arrangement | 2009-08-06 |
20090198970 | METHOD AND STRUCTURE FOR ASYNCHRONOUS SKIP-AHEAD IN SYNCHRONOUS PIPELINES - An electronic apparatus includes a plurality of stages serially interconnected as a pipeline to perform sequential processings on input operands. A shortening circuit associated with at least one stage of the pipeline recognizes when one or more of input operands for the stage has been predetermined as appropriate for shortening and execute the shortening when appropriate. | 2009-08-06 |
20090198971 | Heterogeneous Processing Elements - A heterogeneous processing element model is provided where I/O devices look and act like processors. In order to be treated like a processor, an I/O processing element, or other special purpose processing element, must follow some rules and have some characteristics of a processor, such as address translation, security, interrupt handling, and exception processing, for example. The heterogeneous processing element model puts special purpose processing elements on the same playing field as processors, from a programming perspective, operating system perspective, power perspective, as the processors. The operating system can get work to a security engine, for example, in the same way it does to a processor. | 2009-08-06 |
20090198972 | Microprocessor systems - A microprocessor pipeline arrangement 1 includes a plurality of functional units | 2009-08-06 |
20090198973 | PROCESSING CIRCUIT - A processing circuit according to the present invention includes a plurality of logic circuits (designated as L | 2009-08-06 |
20090198974 | METHODS FOR CONFLICT-FREE, COOPERATIVE EXECUTION OF COMPUTATIONAL PRIMITIVES ON MULTIPLE EXECUTION UNITS - A method for executing multiple computational primitives is provided in accordance with exemplary embodiments. A first computational unit and at least a second computational unit cooperate to execute multiple computational primitives. The first computational unit independently computes other computational primitives. By virtue of arbitration for shared source operand buses or shared result buses, availability of the first and second computational units needed to execute cooperatively the multiple computational primitives is assured by a process of reservation as used for a computational primitive executed on a dedicated computational unit. | 2009-08-06 |
20090198975 | TERMINATION OF IN-FLIGHT ASYNCHRONOUS MEMORY MOVE - A data processing system has a processor, a memory, and an instruction set architecture (ISA) that includes: (1) an asynchronous memory mover (AMM) store (ST) instruction initiates an asynchronous memory move operation that moves data from a first memory location having a first real address to a second memory location having a second real address by: (a) first performing a move of the data in virtual address space utilizing a source effective address a destination effective address; and (b) when the move is completed, completing a physical move of the data to the second memory location, independent of the processor. The ISA further provides (2) an AMM terminate ST instruction for stopping an ongoing AMM operation before completion of the AMM operation, and (3) a LD CMP instruction for checking a status of an AMM operation. | 2009-08-06 |
20090198976 | METHOD AND STRUCTURE FOR HIGH-PERFORMANCE MATRIX MULTIPLICATION IN THE PRESENCE OF SEVERAL ARCHITECTURAL OBSTACLES - A method (and apparatus) for processing data on a computer having a memory to store the data and a processing unit to execute the processing, the processing unit having a plurality of registers available for an internal working space for a data processing occurring in the processing unit, includes configuring the plurality of registers to include at least two sets of registers. A first set of the at least two sets interfaces with the processing unit for the data processing in a current processing cycle. A second set of the at least two sets is used for removing data from the processing unit of a previous processing cycle to be stored in the memory and preloading data into the processing unit from the memory, to be used for a next processing cycle. | 2009-08-06 |
20090198977 | Sharing Data in Internal and Memory Representations with Dynamic Data-Driven Conversion - Illustrative embodiments determine the data type of the operand being accessed as well as analyze the data value subrange of the input operand data type. If the operand's data type does not match the required format of the instruction being processed, a determination is made as to whether a subrange of data values of the data type of the input operand is supported natively. If the subrange of data values of the input operand is not supported natively, then a format conversion is performed on the data and the instruction may then operate on the data. Otherwise, the data may be operated on directly by the instruction without a format conversion operation and thus, the conversion is not performed. | 2009-08-06 |
20090198978 | Data processing apparatus and method for identifying sequences of instructions - A data processing apparatus is provided comprising a processing unit for executing instructions, a cache structure for storing instructions retrieved from memory for access by the processing unit, and profiling logic for identifying a sequence of instructions that is functionally equivalent to an accelerator instruction. When such a sequence of instructions is identified, the equivalent accelerator instruction is stored in the cache structure as a replacement for the first instruction of the sequence, with the remaining instructions in the sequence of instructions being stored unchanged. The accelerator instruction includes an indication to cause the processing unit to skip the remainder of the sequence when executing the accelerator instruction. | 2009-08-06 |
20090198979 | PROCESSOR PERFORMANCE STATE OPTIMIZATION - A processor performance state optimization includes a system to change a performance state of a processor. In an embodiment, the system to change a performance state of the processor includes a processor and a step logic sub-system operatively coupled with the processor and is operable to communicate a performance state change request to the processor. A core voltage regulator is operatively coupled with the step logic sub-system. An end performance state sub-system to determine a desired end performance state is coupled with the step logic sub-system. And, an enable sub-state transition sub-system to enable sub-state transitions is coupled with the step logic sub-system. | 2009-08-06 |
20090198980 | FACILITATING PROCESSING IN A COMPUTING ENVIRONMENT USING AN EXTENDED DRAIN INSTRUCTION - An extended DRAIN instruction is used to stall processing within a computing environment. The instruction includes an indication of the one or more processing stages at which processing is to be stalled. It also includes a control that allows processing to be stalled for additional cycles, as desired. | 2009-08-06 |
20090198981 | DATA PROCESSING SYSTEM, PROCESSOR AND METHOD OF DATA PROCESSING HAVING BRANCH TARGET ADDRESS CACHE STORING DIRECT PREDICTIONS - In at least one embodiment, a processor includes at least one execution unit and instruction sequencing logic that fetches instructions for execution by the execution unit. The instruction sequencing logic includes branch logic that outputs predicted branch target addresses for use as instruction fetch addresses. The branch logic includes a branch target address cache (BTAC) having at least one direct entry providing storage for a direct branch target address prediction associating a first instruction fetch address with a branch target address to be used as a second instruction fetch address immediately after the first instruction fetch address and at least one indirect entry providing storage for an indirect branch target address prediction associating a third instruction fetch address with a branch target address to be used as a fourth instruction fetch address subsequent to both the third instruction fetch address and an intervening fifth instruction fetch address. | 2009-08-06 |
20090198982 | DATA PROCESSING SYSTEM, PROCESSOR AND METHOD OF DATA PROCESSING HAVING BRANCH TARGET ADDRESS CACHE SELECTIVELY APPLYING A DELAYED HIT - In at least one embodiment, a processor includes at least one execution unit that executes instructions and instruction sequencing logic, coupled to the at least one execution unit, that fetches instructions from a memory system for execution by the at least one execution unit. The instruction sequencing logic including branch target address prediction circuitry that stores a branch target address prediction associating a first instruction fetch address with a branch target address to be used as a second instruction fetch address. The branch target address prediction circuitry includes delay logic that, in response to at least a tag portion of a third instruction fetch address matching the first instruction fetch address, delays access to the memory system utilizing the second instruction fetch address if no branch target address prediction was made in an immediately previous cycle of operation. | 2009-08-06 |
20090198983 | GLOBAL HISTORY FOLDING TECHNIQUE OPTIMIZED FOR TIMING - A global history vector (GHV) mechanism maintains a folded GHV with higher order entries an an unfolded GHV with lower order entries. When a new entry arrives at the GHV, the GHV mechanism performs an XOR of the oldest unfolded entry in the unfolded GHV with the new entry. The XOR result is then shifted into the folded GHV as the newest folded entry. The oldest folded entry is discarded during the shift in of the newest folded entry. The GHV mechanism thus provides a resulting folded GHV that is current and can be utilized for XORing with an IFAR by performing an XOR operation. Only a single XOR logic is required to perform a single bit XOR operation between the oldest entry and the youngest entry, resulting in reducing the cycle time required to complete the folding operation on a GHV. | 2009-08-06 |
20090198984 | Global History Branch Prediction Updating Responsive to Taken Branches - A system and method are provided for updating a global history prediction record in a microprocessor system using pipelined instruction processing. The method accepts a microprocessor instruction of consecutive operations, including a conditional branch operation with an associated branch address, at a first stage in a pipelined microprocessor execution process. A global history record (GHR) of conditional branch resolutions and predictions is accessed and hashed with the branch address, creating a first hash result. The first hash result is used to access an indexed branch history table (BHT) of branch direction counts and the BHT is used to make a branch prediction. If the branch prediction being “taken”, the current GHR value is left-shifted and hashed with the branch address, creating a second hash result which is used in creating an updated GHR. | 2009-08-06 |
20090198985 | DATA PROCESSING SYSTEM, PROCESSOR AND METHOD OF DATA PROCESSING HAVING BRANCH TARGET ADDRESS CACHE WITH HASHED INDICES - In at least one embodiment, a processor includes at least one execution unit that executes instructions and instruction sequencing logic, coupled to the at least one execution unit, that fetches instructions from a memory system for execution by the at least one execution unit. The instruction sequencing logic including a branch target address cache (BTAC) including a plurality of entries for storing branch target address predictions. The BTAC includes index logic that selects an entry to access utilizing a BTAC index based upon at least a set of higher order bits of an instruction address and a set of lower order bits of the instruction address. | 2009-08-06 |
20090198986 | Configurable Instruction Sequence Generation - A configurable instruction set architecture is provided whereby a single virtual instruction may be used to generate a sequence of instructions. Dynamic parameter substitution may be used to substitute parameters specified by a virtual instruction into instructions within a virtual instruction sequence. | 2009-08-06 |
20090198987 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND RECORDING MEDIUM STORING COMPUTER PROGRAM - An information processing apparatus includes a transceiver unit transmitting and receiving information to and from an external device is provided. The apparatus includes a setting information storage unit storing setting information related to an operating environment in association with user identification information, a judging unit judging whether the information that the transceiver unit transmits to or receives from the external device includes given information, an extraction unit extracting the given information from the information including the given information, a specifying unit specifying a user on the basis of the given information, and a setting unit reading the setting information stored in the setting information storage unit in association with the user identification information and setting the user operating environment on the basis of the setting information. | 2009-08-06 |
20090198988 | METHOD FOR VERIFYING REFRESHED BIOS CONTENT - A method for verifying refreshed BIOS content includes the following steps. A virtual machine (VM) is established in a computer waiting for a system BIOS update by the use of a paravirtualization technique. The VM is booted. A new BIOS file content is copied to an address space in a designated range of a memory of a computer host. The computer host is booted with the content of the new BIOS file, and the paravirtual operating system runs on the same hardware platform of the computer host. And, whether the virtual operating system adopting the new BIOS file content runs normally or not is verified to confirm the correctness and safety of the content of the new BIOS file. | 2009-08-06 |
20090198989 | BIOS FOR A COMPUTING DEVICE WITH HANDHELD AND EXTENDED COMPUTING UNITS - A handheld computing unit includes a processing module, a main memory interface, a baseband processing module, an RF section, input/output (I/O) interfaces, a bus structure, a handheld connection structure, and a ROM. The ROM includes a first section for storing a power on self test (POST) of basic input/output system (BIOS) and a second section for storing a boot loader of the BIOS. The boot loader includes a remote mode operating system boot loader and a docked mode operating system boot loader. The remote mode operating system boot loader is used to load a remote mode operating system when in a remote mode and the docked mode operating system boot loader is used to load a docked mode operating system when in a docked mode, which includes at least a portion of the remote mode operating system. | 2009-08-06 |
20090198990 | Accessory support system for remote inspection device - A remote inspection apparatus has an active display unit receiving image data in digital form and graphically rendering the image data on an active display. A communication medium connects devices to the active display unit, such as an imager head capturing the image data. A computer readable medium records one or more instances of software for operating the one or more devices. A computer processor located in the active display unit that operates a boot loader program to detects and sequentially interrogate the devices by different protocols in order to determine appropriate software to load and operate the devices. | 2009-08-06 |
20090198991 | TRUSTED BOOT - In one embodiment, a method for trusted booting of a cryptographic processor system is disclosed. Default image(s) is loaded into a field-programmable logic chip or circuit (FPLC). The default image(s) cannot perform cryptographic processing, but can perform a first algorithm that is unclassified. A processor, internal or external to the FPLC, can be used with the default image. A multi-layer or multi-part key has portions stored in two different places. A protected image is decrypted with the multi-layer key using the first algorithm and loaded into the FPLC. Cryptographic processing is performed using a second algorithm classified by the government. | 2009-08-06 |
20090198992 | HANDHELD COMPUTING UNIT WITH MERGED MODE - A handheld computing unit includes a hardware section, an application section, and an operating system section. The hardware section and operating system section are operable to: detect another device; determine whether to merge functionality with the other device; and when it is determined to merge functionality with the other device, initiate a reboot of the handheld computing unit and of the other device in a merged mode, wherein, in the merged mode, the hardware section and a hardware section of the other device function as a single hardware section and the operating system section and an operating system section of the other device function as a single operating system section. | 2009-08-06 |
20090198993 | METHOD FOR JOINING USER DOMAIN AND METHOD FOR EXCHANGING INFORMATION IN USER DOMAIN - A method for joining a user domain based on digital right management (DRM), a method for exchanging information between a user device and a domain enforcement agent, and a method for exchanging information between user devices belonging to the same user domain include sharing a domain session key between the user device and the domain enforcement agent or between the user devices belonging to the same user domain. Information is exchanged through a secure session set up between the user device and domain enforcement agent or between the user devices, and information exchange occurs through encryption/decryption using the domain session key. | 2009-08-06 |
20090198994 | UPDATED SECURITY SYSTEM - A method is provided for improving computer security. A computer executes instructions for protecting a processing component on itself. Software generates a second processing module attacher responsive to an execution of the processing component. The computer stores data indicative of at least one second processing module thereby to define a processing module library. The attacher is adapted to retrieve a second processing module from the processing module library and to attach the retrieved second processing module to the processing component. This enables a security restriction on data processed by the processing component. | 2009-08-06 |
20090198995 | System and method for providing security via a top level domain - A system and method is disclosed for providing end-to-end security for communications between registered clients of a top level domain without the need for further encryption/decryption protocols than those provided by said at least one of said plurality of secure communication links and said at least one secure message server. Clients registered with the top level domain are assigned at least one email and IM account and to ensure message security, are required to communicate with other registered others strictly via the assigned email and IM accounts. In this manner, non-registered users are denied secure access to the top level domain. In one embodiment, registered clients of the top-level domain may communicate with non-registered users via a gateway server in a secure or non-secure manner, as is the option of the registered client (sender). | 2009-08-06 |
20090198996 | SYSTEM AND METHOD FOR PROVIDING CELLULAR ACCESS POINTS - A system and method for providing a identity association between a subscriber in a private network and a provider over a public network is described. The system and method include a subscriber security gateway in the private network, the subscriber security gateway providing policy enforcement and signaling between the private network and the provider over the public network and at least one digital key associated with the provider and readable by the subscriber security gateway and operable to provide a identity association with the provider. A network device in the private network, the network device operable to establish a trusted media channel between the provider and the network device using the public network as a result of the signaling and policy enforcement at the subscriber security gateway using the digital keys, and a security gateway in the provider network, the security gateway including a registry for authenticating the user using the digital key and for maintaining a record of the subscriber's relationship with the provider. | 2009-08-06 |
20090198997 | System and method for secure electronic communication services - A system, method and software module for secure electronic communication services, wherein a public key ( | 2009-08-06 |
20090198998 | Method and apparatus of ensuring security of communication in home network - Provided are a method and apparatus to ensuring communication security between a control apparatus and a controlled apparatus in a home network. The control apparatus in the home network establishes a registration Secure Authenticated Channel (SAC) with the controlled apparatus by using a Transport Layer Security Pre-Shared Key ciphersuites (TLS-PSK) protocol implemented by using a Product Identification Number (PIN) of the controlled apparatus input from a user, shares a private key with the controlled apparatus via the registration SAC, and uses services of the controlled apparatus via a service SAC established by using the TLS-PSK protocol implemented by using the shared private key to easily implement a framework ensuring communication security in the home network. | 2009-08-06 |
20090198999 | SYSTEM AND METHOD FOR DISTRIBUTING KEYS IN A WIRELESS NETWORK - A technique for improving authentication speed when a client roams from a first authentication domain to a second authentication domain involves coupling authenticators associated with the first and second authentication domains to an authentication server. A system according to the technique may include, for example, a first authenticator using an encryption key to ensure secure network communication, a second authenticator using the same encryption key to ensure secure network communication, and a server coupled to the first authenticator and the second authenticator wherein the server distributes, to the first authenticator and the second authenticator, information to extract the encryption key from messages that a client sends to the first authenticator and the second authenticator. | 2009-08-06 |
20090199000 | METHOD AND APPARATUS FOR ENCRYPTED COMMUNICATIONS TO A SECURE SERVER - An embodiment of the invention includes a secure server. A user at a terminal, communicatively coupled to the secure server by a secure link, can obtain web pages from web sites in a network, in encrypted form, via the secure link. Addresses associated with the web pages are altered to make it appear as if the web pages come from the secure server rather than from the web sites. Spoofing units may be used as alternative access points to the secure server, with the secure server sending the requested web pages directly to the terminal. In general, address rewriting and other manipulation can be performed on the requested web pages, such that the true sources of the web pages are disguised and such that subsequent communications from the terminal are directed to the secure server and/or spoofing unit, rather than to the true source of the web pages. Components of the user's privacy may be sold, or advertisements may be provided, in exchange for protection of the user's identity. | 2009-08-06 |
20090199001 | Access to services in a telecommunications network - A method and arrangement is disclosed for providing a user, not previously having an individual subscription with a network operator, with credentials for secure access to network services. The arrangement includes a gateway, associated with a subscription for network services, having means for generating and exporting to a user entity personalized user security data derived from security data related to the subscription. In particular, the derivation of credentials is based on a function that is shared between network and gateway and further conveniently makes use of bootstrapping on keying material from the subscription authentication. Pre-registered user identities are assigned trusted users who, thereafter, can download credentials and authenticate for service access. The invention may be implemented at a public place for providing temporary visitors network access whereby trust may exemplary be established by presenting a credit card. | 2009-08-06 |
20090199002 | Methods and Systems for Shortened Hash Authentication and Implicit Session Key Agreement - A first hash result is generated at a client system in accordance with hash input parameters known to the client system. A second hash result is generated at a server system in accordance with hash input parameters known to the server system. Each of the first hash result and the second hash result is truncated in a same manner. The truncated first hash result is transmitted from the client system to the server system. The truncated first hash result as transmitted to the server system is compared with the truncated second hash result generated at the server system. Equality between the truncated first hash result as transmitted to the server system and the truncated second hash result generated at the server system authenticates the client system to the server system. | 2009-08-06 |
20090199003 | SMART CARD AND METHOD FOR USING A SMART CARD - The invention provides as smart card, a secured client with a smart card and a method for use in a smart card. The smart card is configured for counting ECMs associated to a particular portion of the content stream and storing loyalty points on the smart card. This enables e.g. counting of ECMs related to advertisements. Watching advertisements results in earning loyalty points that can be used to watch television programs for free. | 2009-08-06 |
20090199004 | SYSTEM AND METHOD FOR SELF-AUTHENTICATING TOKEN - A secure token, possibly in the form of a smartcard, has a smart window with smart materials such as an electrophoretic or an electrochromic layer or assembly. When authenticated, such as by using biometrics or a password, the smart window layer is electronically pulsed, thereby transforming the once opaque layer to transparent and revealing information printed under, on or over the layer, or vice versa, transforming once transparent laminate to opaque and obfuscating printed information. In another embodiment, when the smart window layer is electronically pulsed to transform the once opaque laminate to transparent, a timer is started. At the end of a certain amount of time, the smart window layer is pulsed a second time, thereby transforming the layer back from transparent to opaque. | 2009-08-06 |
20090199005 | AUTHENTICATION DEVICE, MOBILE TERMINAL, AND AUTHENTICATION METHOD - The security of an IC card is improved by managing success and failure in authentication individually for each terminal program. An IC card includes a random number generation section, a source authentication section, and a process execution section. Upon receipt of a message of type “1”, the random number generation section generates a random number n, and stores it in a random number storage section by associating the random number n with a source included in the message. Upon receipt of a message of type “2” from the source and in a case where the random number n corresponding to the source is stored, the source authentication section collates a value m calculated from an authentication key held by the IC card and the random number n with a value m included in the message of type “2”. When both values agree, upon receipt of a message of type “3” from the source, the process execution section executes a process in accordance with a type of the message. | 2009-08-06 |
20090199006 | Method and Device for Secure Mobile Electronic Signature - The present invention relates to a mobile, portable and compact signature device which is used for simple and secure signature of information by a user. In particular the device is protected from manipulation attempts by the combination of two measures: firstly the architecture ensures that information can only be shown on the display and signed when decrypted by the Smartcard in the device and thus intended for a specific user identity represented by the Smartcard. Secondly further manipulation opportunities for a potential attacker are restricted by the permanent combination in everyday use of the signature device with display and Smartcard. The area of application of the signature device disclosed and associated method includes but is not restricted to the authorisation of financial transactions. | 2009-08-06 |
20090199007 | PROVIDING CERTIFICATE MATCHING IN A SYSTEM AND METHOD FOR SEARCHING AND RETRIEVING CERTIFICATES - A system and method for searching and retrieving certificates, which may be used in the processing of encoded messages. In one broad aspect, certificate identification data that uniquely identifies a certificate associated with a message is generated. The certificate identification data can then be used to determine whether the certificate is stored on a computing device. Only the certificate identification data is needed to facilitate the determination alleviating the need for a user to download the entire message to the computing device in order to make the determination. | 2009-08-06 |
20090199008 | Watermarking digital representations that have undergone lossy compression - Techniques for watermarking digital representations such as MPEG audio frames that spread the watermark information across the entire audio frame. The techniques work in conjunction with lossy compression techniques and are compatible with the perception models that are often used with lossy compression techniques. The watermark information is spread by means of transformations between the space/time domain and the frequency domain. When a MPEG audio frame is being watermarked, the compressed audio frame as it is produced by the quantizer is transformed from the frequency domain to the time domain; the time domain transformation is then randomized using a key and the randomized time domain transformation is transformed into the frequency domain. The watermark information is added at a predetermined frequency in the frequency domain transformation and the sequence of transformations is done in reverse order, with the randomization and derandomization serving to distribute the watermark information across the frequency domain representation of the watermarked audio frame. | 2009-08-06 |
20090199009 | Systems, methods and computer program products for authorising ad-hoc access - Methods, systems and computer program products for authorizing ad-hoc access are disclosed. A method for ad-hoc authorization comprising the steps of sending a pre-token via an unsecured communication channel to a device requesting ad-hoc authorization, sending a token associated with the pre-token via a secure communications channel to a proxy for the device, receiving evidence of access by the device to the token and determining the ad-hoc authorization based on the evidence. The systems and computer program products disclosed provide means for practicing the methods disclosed. | 2009-08-06 |
20090199010 | SIGNATURE DEVICE, VERIFICATION DEVICE, PROGRAM, SIGNATURE METHOD, VERIFICATION METHOD, AND SYSTEM - An efficient signature technology is provided, which is capable of arbitrary extraction and storage from a plurality of pieces of data and which can make a signature length relatively short. In a signature device ( | 2009-08-06 |
20090199011 | INFORMATION PROCESSING APPARATUS AND METHOD - An information processing apparatus includes a classifying unit configured to classify structural elements under predetermined attributes; a storage unit configured to store data, which describes which attribute among the attributes of the structural elements is a target of electronic signature verification, in association with the output destination of a structured document; an attaching unit configured to attach electronic signatures to the structural elements; and an inserting unit configured to refer to the stored data and data of the structured document, generate tree data which corresponds to the output destination of the structured document and indicates which structural element is a target of electronic signature verification among the structural elements to which electronic signatures have been attached, and insert the tree data in the data of the structured document. | 2009-08-06 |
20090199012 | CONTENTS TRANSMISSION METHOD AND CONTENTS TRANSMISSION SYSTEM - Mobile unit | 2009-08-06 |
20090199013 | AUTHENTICATION OF CONTENT DOWNLOAD - According to the invention, a method for authenticating download of a number of digital content files ordered from a web site is disclosed. In one step, a selection of the digital content files is received with the web site. Download manager software, media information, the digital content files, and first codes for each of the digital content files are sent to the client computer. The media information indicates a location of each of the number of digital content files. A first code is calculated for each of the digital content files. If the client computer determines that the first code doesn't match a second code for a particular digital content file, it is resent. | 2009-08-06 |
20090199014 | SYSTEM AND METHOD FOR SECURING AND EXECUTING A FLASH ROUTINE - A microcontroller comprises a random access memory (RAM) device; a non-volatile memory device having a data sector, wherein operation codes are stored as data files in the data sector; and a processor configured to retrieve the operation codes from the data sector, load the retrieved operation codes into the RAM device and run the decrypted operation codes from the RAM device. | 2009-08-06 |
20090199015 | METHOD FOR PROTECTING AUDIO CONTENT - Techniques for protecting information in an audio file are provided. The techniques include obtaining an audio file, detecting information bearing one or more segments in a speech signal, wherein the information comprises information sought for protection, encrypting the information sought for protection by scrambling the one or more segments using a scrambling filter, and selectively decrypting an amount of the encrypted information, wherein the amount of the encrypted information to be decrypted depends on user access privilege, and wherein selectively decrypting the amount of the encrypted information protects said amount of the encrypted information. Techniques are also provided for protecting information in an audio file. | 2009-08-06 |
20090199016 | Storage system, and encryption key management method and encryption key management program thereof - A user no longer needs to restore key information upon restoring data. Proposed is a storage system having a storage apparatus, a tape library apparatus for backing up data stored in the storage apparatus, and a management terminal for managing the storage apparatus and the tape library apparatus. The management terminal identifies a key of a tape to be restored and restores a management Information file based an a tape management file, a tape group information file and a key information file upon restoring data stored in the tape in the tape library apparatus, and commands the restoration of the tape based on the restored management information file. | 2009-08-06 |
20090199017 | ONE TIME SETTABLE TAMPER RESISTANT SOFTWARE REPOSITORY - A one-time-settable tamper resistant software repository may be used in any computing system to store system information such as security violations and policies for responding to them. A one-time-settable tamper resistant software repository may be cryptographically signed, encrypted with a per device key and accessible by only the most privileged software executed by a computing device, e.g., hypervisor or operating system kernel. A one-time-settable tamper resistant software repository may be mirrored in RAM for performance. Recordable event fields in a software repository may be one-time-settable without the ability to reset them in a field operation mode whereas they may be resettable in a different mode such as a manufacturing mode. Memory allocated to a one-time-settable tamper resistant software repository may be reset, reclaimed, reassigned, scaled and otherwise flexibly adapted to changing conditions and priorities in the lifespan of a computing device, which may be particularly useful for service-backed consumer devices. | 2009-08-06 |
20090199018 | One time settable tamper resistant software repository - An individualized per device initialization of a computing device is unique relative to the initialization of other computing devices. A common initialization program, common to all computing devices of a particular type such as a game console, may be modified to be unique for each computing device. Modification may comprise the application of at least one individualized per device secret, e.g., key, to at least a portion of the common initialization program such as at least one initialization stage. Initialization is tied to one or more device specific identities. In this way, initialization vulnerabilities discovered on a particular device cannot be exploited en masse on other computing devices because each initialization program stored in each computing device is unique. The device specific nature of the initialization program may be extended to other information input to the computing device in order to prevent unauthorized sharing of information with other computing devices. | 2009-08-06 |
20090199019 | APPARATUS, METHOD AND COMPUTER PROGRAM PRODUCT FOR REDUCING POWER CONSUMPTION BASED ON RELATIVE IMPORTANCE - An apparatus, method and computer program product are provided for reducing power consumption of an electronic device by taking into consideration not only the load history of each run-time entity operating on the electronic device, but also the importance of those run-time entities. In particular, a run-time entity's utilization of the hardware resources of an electronic device may be controlled in association with the importance level assigned to that run-time entity. Run-time entities having a lower importance level may be allocated less than the maximum operating power of the processor necessary to implement the run-time entity at the highest performance level. | 2009-08-06 |
20090199020 | METHOD AND SYSTEM OF MULTI-CORE MICROPROCESSOR POWER MANAGEMENT AND CONTROL VIA PER-CHIPLET, PROGRAMMABLE POWER MODES - A computer-implemented method and a system for managing power in a multi-core microprocessor are provided. A power management control microarchitecture in a chiplet translates a first command comprising a power setting. A chiplet comprises a processor core and associated memory cache. The power management control microarchitecture comprises power mode registers, power mode adjusters, translators, and microarchitectural power management techniques. The power management control microarchitecture sets microarchitectural power management techniques according to the power setting. The global power management controller issues the first command. The global power management controller may reside either on or off of the microprocessor. The global power management controller issues commands either directly for a specific chiplet out of the plurality of chiplets or to the plurality of chiplets and the control slave bus translates the command into sub-commands dedicated to specific chiplets within the plurality of chiplets. Each chiplet may be set to separate power levels. | 2009-08-06 |
20090199021 | POWER MANAGEMENT MODULE FOR CENTRAL PROCESSING UNIT - A power management module for a CPU is provided. The power management module includes a basic input/output system (BIOS) chip, a power stripping module, and a DC-DC converter module. The BIOS chip is coupled to the CPU, and has a power consumption information of the CPU. The power stripping module is coupled to BIOS chip, and is adapted for outputting a power control signal according to the power consumption information of the CPU. The DC-DC converter module is coupled to the CPU and the power stripping module. The DC-DC converter module includes a plurality of DC-DC converters. The power control signal is accorded to determine a quantity of the DC-DC converters for enabling, so as to provide a suitable power to the CPU. | 2009-08-06 |
20090199022 | Image processing apparatus, serial bus control method, and storage medium - A disclosed image processing apparatus has a normal power mode and a power saving mode and includes a serial bus; a serial bus PHY configured to control a physical layer of the serial bus, the serial bus PHY being turned off in the power saving mode; a voltage detection unit configured to detect a voltage output from an external device connected to the serial bus; and a physical layer control unit configured to turn on the serial bus PHY when the voltage is detected by the voltage detection unit. | 2009-08-06 |
20090199023 | Processor and Semiconductor Device Capable of Reducing Power Consumption - A processor and a semiconductor device capable of reducing power consumption is provided. The processor includes one or more logic blocks each having a logic circuit corresponding to m bits for processing m bits of data and a logic circuit corresponding to n bits for processing n bits of data, n being an integer smaller than m. A power control unit controls the processor for operation as an m-bit processor by providing a power voltage to the logic circuit corresponding to m bits, or controls the processor for operation as an n-bit processor by providing the power voltage to the logic circuit corresponding to n bits. | 2009-08-06 |
20090199024 | METHOD, APPARATUS AND SYSTEM TO DYNAMICALLY CHOOSE AN AOPTIMUM POWER STATE - Some embodiments of the invention include an apparatus and method for dynamically choosing an optimum power state. In some embodiments, the optimum power state may be determined from historical information about the various power states that any of the embodiments of the apparatus or a system equipped with embodiments of the apparatus or operating embodiments of the method may encounter. Some embodiments may generate registers to maintain information regarding the various power states. In some embodiments, power management logic may determine the optimum power state based upon this information. Other embodiments are described. | 2009-08-06 |
20090199025 | BI-DIRECTIONAL POWER CONTROL - An electrical circuit for bi-directional power control between two devices, including a first battery-operated device, including a first battery for providing a source of power to the first battery-operated device, a first power management subsystem connected to the first battery, to power on and power off components of the first battery-operated device in response to a first wakeup event, WE | 2009-08-06 |
20090199026 | Saving energy based on storage classes with corresponding power saving policies - An example of the invention classifies disks drives based on their purpose and associating power-saving policies in multiple classes. The system implements Power On Demand, where a reduced power mode is enabled for every individual component of a storage subsystem. In addition, an embodiment of this invention extends a few power modes used in the prior art and allows almost infinite number of power modes when instructing a disk drive (via its I/O interface such as a SCSI or fibre channel interface) to enter a certain power saving mode. Furthermore, an embodiment of invention teaches a system and methods to save power in a disk system comprising a plurality of disk controllers and a plurality of disk drives, arranged in a plurality of arrays, where each array includes several (e.g., 4-16) disk drives. | 2009-08-06 |
20090199027 | METHOD AND APPARATUS TO AVOID POWER TRANSIENTS DURING A MICROPROCESSOR TEST - Exemplary embodiments provide a computer-implemented method and a system for a startup cycle for a cycle deterministic start. An initializing mechanism applies power to a microprocessor. The initializing mechanism initializes the configuration of the microprocessor. The initializing mechanism initializes a timer. The initializing mechanism then sends a clock start command to the microprocessor. The clocks on the microprocessor are started. Upon the clocks starting, the timer begins and allows temporary transients, such as voltage droop due to a large instantaneous change in demand for current due to the commencement of clock switching. Responsive to the timer reaching a target value, an interrupt unit sends a system reset interrupt. Responsive to the interrupt unit sending the system reset interrupt, an instruction fetch unit fetches a first instruction. This operation will be deterministic to the state of the rest of the microprocessor memory elements (latches, arrays, et al.). | 2009-08-06 |
20090199028 | Wake-and-Go Mechanism with Data Exclusivity - Snoop response logic on a system bus is configured to detect on the system bus requests to access data at a target address with data exclusivity from at least one of a plurality of wake-and-go engines. The snoop response logic is further configured to determine a winning wake-and-go engine from the at least one wake-and-go engine that obtains a lock on the target address and generate a combined snoop response. The combined snoop response identifies the winning wake-and-go engine. The snoop response logic sends the combined snoop response to the at least one wake-and-go engine on the system bus. Each remaining wake-and-go engine within the at least one wake-and-go engine places an entry in its respective wake-and-go storage array to spin on a lock for the target address. | 2009-08-06 |
20090199029 | Wake-and-Go Mechanism with Data Monitoring - A wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism recognizes a programming idiom, specialized instruction, operating system call, or application programming interface call that indicates that a thread is waiting for an event. The wake-and-go mechanism updates a wake-and-go array with a target address, expected data value, and comparison type associated with the event. The thread then goes to sleep until the event occurs. The wake-and-go array may be a content addressable memory (CAM). When a transaction appears on the symmetric multiprocessing (SMP) fabric that modifies the value at a target address in the CAM, logic associated with the CAM performs a comparison based on the data value being written, expected data value, and comparison type. | 2009-08-06 |
20090199030 | Hardware Wake-and-Go Mechanism for a Data Processing System - A hardware wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism recognizes a programming idiom that indicates that a thread is waiting for an event. The wake-and-go mechanism updates a wake-and-go array with a target address associated with the event. The thread then goes to sleep until the event occurs. The wake-and-go array may be a content addressable memory (CAM). When a transaction appears on the symmetric multiprocessing (SMP) fabric that modifies the value at a target address in the CAM, the CAM returns a list of storage addresses at which the target address is stored. The wake-and-go mechanism associates these storage addresses with the threads waiting for an even at the target addresses, and may wake the one or more threads waiting for the event. | 2009-08-06 |
20090199031 | USB Self-Idling Techniques - USB self-idling techniques are described. In one or more embodiments, a Universal Serial Bus (USB) device comprises one or more modules to communicate via USB and self-idle by presenting an idle mode to a USB host and entering a suspend mode while the USB host is presented with the idle mode. | 2009-08-06 |
20090199032 | METHOD FOR DETERMINING AND MAXIMIZING UNAVAILABILTY INTERVAL - The method for maximizing an unavailability interval includes the steps of initializing the starting frame number of each power saving class f | 2009-08-06 |
20090199033 | Power Delivery System - A system is disclosed. The system includes a load, a voltage regulator circuit coupled to the load a power supply, a load coupled to the power supply to receive one or more voltages from the power supply, and a digital bus, coupled between the power supply and the load. The digital bus transmits power consumption measurements from the load to the power supply and transmits power consumption measurements from the power supply to the load. | 2009-08-06 |
20090199034 | INTERACTIVE DEVICE WITH TIME SYNCHRONIZATION CAPABILITY - An interactive device having time synchronization capability is provided. In one embodiment of the present invention, the interactive device has a computer processor that stores an internal clock. The computer processor may be preprogrammed to generate announcements based on a particular time of the internal clock. A user may input and adjust the time of the internal clock. In another embodiment of the present invention a setup module is provided. A setup module is an operative device that includes a computer processor that stores a setup time. The setup module establishes a connection with an interactive device, and time synchronizes the interactive device such that the internal clock of the interactive device is running the same time as the setup module. The setup module is capable of synchronizing the internal clock of multiple interactive devices, despite the interactive devices being programmed on separate occasions. In addition, the setup module is capable of programming a number of interactive devices in a quick and efficient manner, thereby keeping the manufacturer's costs low. The computer processor of the interactive device runs a software program which enables the interactive device to be synchronized by the setup module via a hard-wired connection or wireless means such as infrared (IR) and/or radio frequency (RF) signals. | 2009-08-06 |
20090199035 | Network signal processing apparatus - A network signal processing circuit includes a first signal processing module, a first sampling rate converter, a second signal processing module, a second sampling rate converter and a timing controller. The first signal processing module is utilized for processing a network signal to output a first processed signal. The first sampling rate converter is utilized for performing signal frequency conversion on the first processed signal according to a first clock timing adjusting signal and outputting a first converted signal. The second signal processing module is utilized for processing the first converted signal to output a second processed signal. The second sampling rate converter is utilized for performing signal frequency conversion on the second processed signal according to a second clock timing adjusting signal and outputting a second converted signal. The timing controller is utilized for generating the first and second clock timing adjusting signals. | 2009-08-06 |
20090199036 | LSSD compatibility for GSD unified global clock buffers - A method, system and program are provided for generating level sensitive scan design (LSSD) clock signals from a general scan design (GSD) clock buffer using an intermediate clock signal and one or more first mode control signals to generate a plurality of LSSD clock signals from an output section of the GSD clock buffer that receives the intermediate clock signal and the first mode control signal(s), where the GSD clock buffer is also configured to generate a plurality of GSD clock signals in response to receiving a GSD mode, generating an intermediate clock signal from the input section of the GSD clock buffer in response receiving a GSD mode signal. | 2009-08-06 |
20090199037 | Wake-up timer with periodic recalibration - A power saving sleep timer has a first clock and a second clock having greater frequency and temporal stability than the first clock. The second clock has an associated second clock period value which is accumulated once for each said second clock interval during one or more first clock periods, thereby forming a calibrated period value. During an operational interval, the calibrated period value is accumulated once per first clock interval until the accumulated value is equal or greater than a sleep time value, after which a power-up output is asserted. | 2009-08-06 |
20090199038 | LOW-POWER MULTI-OUTPUT LOCAL CLOCK BUFFER - An improved circuit for reducing a capacitance load on a processor. The circuit includes a global clock circuit capable of producing a primary timing signal. The circuit further includes a local clock buffer circuit having a plurality of outputs. The local clock buffer circuit is connected to the global clock circuit. The local clock buffer circuit is capable of producing a secondary timing signal based on the primary timing signal. The circuit also includes a latch connected to the local clock buffer circuit. The latch is capable of producing a select signal that controls which outputs of the plurality of outputs are active. Only a third signal, based on the secondary timing signal, controls an operation of the latch. | 2009-08-06 |
20090199039 | FILE DATA RESTORING SYSTEM AND METHOD OF COMPUTER OPERATING SYSTEM AND SOFTWARE THEREOF - A file data restoring system and method of a computer operating system and software thereof are applied in the installation of an operating system into a client computer. Divide the file data corresponding to the operating system into data blocks according to an appointed data size. Generate a check code for each of the data blocks to form a sequence list of original check codes and a sequence list of target check codes. Compare the sequence list of original check codes with the sequence list of target check codes, after installing the operating system into the computer. If the comparison result is inconsistent, a restoring call information is sent out. The position of the inconsistent check code is acquired through the restoring call information and the comparison result. The original file data corresponding to the position of the check code is read and restored to a corresponding target file. | 2009-08-06 |
20090199040 | METHOD AND DEVICE FOR IMPLEMENTING LINK PASS THROUGH IN POINT-TO-MULTIPOINT NETWORK - Methods and devices for implementing Link Pass Through in a point-to-multipoint network in respect of the network reliability field are provided. Embodiments of the present invention are applicable to a network having an access gate, an access device, an aggregation device and a router. When a failure occurs in an active link between the access device and the aggregation device or between the aggregation device and the router, the access device breaks the connection between the access device and the access gate enables a standby link to conduct communication. Advantageously, when a failure occurs in the active link between the access device and the aggregation device or between the aggregation device and the router, the access device may break the connection between the access device and the access gate and the access gate may enable a standby link to conduct communication. Therefore, no matter what type of failure occurs, the embodiments of the present invention may enable a standby link to conduct communication, ensuring thereby communication reliability. | 2009-08-06 |
20090199041 | STORAGE CONFIGURATION RECOVERY METHOD AND STORAGE MANAGEMENT SYSTEM - When failure occurs in a virtualization apparatus in storage network circumstances in which the virtualization apparatus is operated, a storage management server judges volume position information, cache configuration information and pair configuration information which are configuration information of the virtualization apparatus and external storage collectively to decide candidates of recovery methods of volume and candidates of recovery methods of data in the volume, so that construction of a physical volume and a pair and recovery of data are performed and an access path is then changed to the recovered physical primary volume. Consequently, change to the system configuration in which operation is performed without passing through the virtualization apparatus can be made in a short time and continuous operation can be attained. | 2009-08-06 |
20090199042 | Disk Array System and Control Method Thereof - A disk array system, upon detecting a failure in any data disk from among a plurality of data disks providing one or more RAID groups, conducting a correction copy to any spare disk, using one or more other data disks belonging to the same RAID group as the data disk causing the failure. When the data disk causing the failure has been replaced with a new data disk, the disk array system alters the management so that the data disk can be managed as a spare disk, and the spare disk can be managed as a data disk. | 2009-08-06 |
20090199043 | ERROR CORRECTION IN AN INTEGRATED CIRCUIT WITH AN ARRAY OF MEMORY CELLS - An integrated circuit includes an array of memory cells, and an error correction code circuit configured to correct errors in data read from the array based at least in part on a map that identifies locations of erratic memory cells in the array. | 2009-08-06 |
20090199044 | Device self-maintenance - Software running on a processor is operable to control the cycled powering down and powering up of components of a self-service terminal (SST) in order to attempt to rectify a fault within the SST without the need to power down the SST core processor. The software can also control the resetting of universal serial bus (USB) ports associated with the components of the SST in order to try and clear faults associated with a communications link between a component and the SST core processor. | 2009-08-06 |
20090199045 | SOFTWARE FAULT MANAGEMENT APPARATUS, TEST MANAGEMENT APPARATUS, FAULT MANAGEMENT METHOD, TEST MANAGEMENT METHOD, AND RECORDING MEDIUM - A fault management system is provided with a fault data entry accepting portion for accepting entry of fault data including indicator data for assessing three fault assessment items in four assessment grades, a fault data holding portion for storing the fault data, a fault data prioritizing portion for prioritizing the fault data in the order of addressing faults, a customer profile data entry accepting portion for accepting entry of customer profile data indicative of degrees of requirement by each customer regarding the three assessment items and the importance of customers to the user, and a customer profile data holding portion for storing the customer profile data. The fault data prioritizing portion prioritizes the fault data based on assessment values regarding the three assessment items. | 2009-08-06 |
20090199046 | Mechanism to Perform Debugging of Global Shared Memory (GSM) Operations - A host fabric interface (HFI) enables debugging of global shared memory (GSM) operations received at a local node from a network fabric. The local node has a memory management unit (MMU), which provides an effective address to real address (EA-to-RA) translation table that is utilized by the HFI to evaluate when EAs of GSM operations/data from a received GSM packet is memory-mapped to RAs of the local memory. The HFI retrieves the EA associated with a GSM operation/data within a received GSM packet. The HFI forwards the EA to the MMU, which determines when the EA is mapped to RAs within the local memory for the local task. The HFI processing logic enables processing of the GSM packet only when the EA of the GSM operation/data within the GSM packet is an EA that has a local RA translation. Non-matching EAs result in an error condition that requires debugging. | 2009-08-06 |
20090199047 | EXECUTING SOFTWARE PERFORMANCE TEST JOBS IN A CLUSTERED SYSTEM - Using a testing framework, developers may create a test module to centralize resources and results for a software test plan amongst a plurality of systems. With assistance from the testing framework, the test module may facilitate the creation of test cases, the execution of a test job for each test case, the collection of performance statistics during each test job, and the aggregation of collected statistics into organized reports for easier analysis. The test module may track test results for easy comparison of performance metrics in response to various conditions and environments over the history of the development process. The testing framework may also schedule a test job for execution when the various systems and resources required by the test job are free. The testing framework may be operating system independent, so that a single test job may test software concurrently on a variety of systems. | 2009-08-06 |
20090199048 | SYSTEM AND METHOD FOR DETECTION AND PREVENTION OF FLASH CORRUPTION - A non-volatile memory device comprises an application code sector of sufficient size to store a first copy of an application code and a second copy of the application code; and a boot sector having a boot loader code embodied therein. The boot loader code is configured to cause a processor to check the integrity of both the first and second copies of the application code; if the first copy is corrupted, overwrite the first copy of the application code with the second copy; and if the second copy is corrupted, overwrite the second copy of the application code with the first copy. | 2009-08-06 |
20090199049 | PROGRAM PROCESSING DEVICE AND PROGRAM PROCESSING METHOD - A program processing device has a non-volatile storage, a volatile storage and a controller. The controller has a detector that detects a bit flip in the program, the variable data, and the constant data in the volatile storage, a constant recovery unit that, when the detector detects an error in the constant data, writes the constant data in the non-volatile storage into the volatile storage, and then continues the execution of the program from a point at which the program was being executed before the detector detected the error, and a restart that, when the detector detects an error in one of the variable data and the program, writes the program, the initial value of the variable data, and the constant data in the non-volatile storage into the volatile storage, and then executes the program written into the volatile storage from a beginning of the program. | 2009-08-06 |
20090199050 | Self-service terminal - A self-service terminal comprises a pc core and at least one module, which can be powered down independently of the pc core, the terminal has a control application and an agent arranged to monitor the fault state of the at least one module and cause a fault signal to be sent from the self-service terminal when the fault state of the at least one module is characteristic of a problem with the at least one module. The agent is arranged to determine if the module has been powered down; whereupon the fault signal is buffered until the module is powered up and a determination as to the fault state of the module is again made. The fault signal is only sent if the fault state still indicates there to be a problem with the at least one module. | 2009-08-06 |
20090199051 | METHOD AND APPARATUS FOR OPERATING SYSTEM EVENT NOTIFICATION MECHANISM USING FILE SYSTEM INTERFACE - A method and structure for notifying operating system events, includes standard filesystem interfaces provided for event consumers to use for one or more of registering for event notifications of a set of events, receiving an event notification when each event occurs, and getting details of events that have occurred. | 2009-08-06 |
20090199052 | Management system, computer system, and method of providing information - A management system includes a plurality of analyzers; and a computer system connected to the analyzers via a network, wherein each of the analyzers comprises: a data transmitter for transmitting data produced by the analyzer to the computer system via the network, and wherein the computer system includes a memory under control of a processor, the memory storing instructions enabling the processor to carry out operations, comprising: (a) receiving a plurality of data transmitted from the data transmitters of the plurality of analyzers; (b) generating an aggregate result used for determining a determination condition for making a determination as to whether or not a notification to a user of the analyzer is required based on the plurality of received data; and (c) outputting the aggregate result. A computer system and a method of providing information are also disclosed. | 2009-08-06 |
20090199053 | SELF-SERVICE TERMINAL - A self-service terminal comprises a pc core; at least one module coupled to the pc core; a control application executing on the pc core for controlling the operation of the terminal; and a management application executing on the pc core. The management application is arranged to (i) monitor state of health of the pc core, the control application, and the at least one module, (ii) detect a fault state at any of the pc core, the control application, and the at least one module, (iii) monitor the control application to ascertain if a filter criterion is satisfied, and (iv) transmit a fault signal from the terminal only if the filter criterion is not satisfied. | 2009-08-06 |
20090199054 | METHOD AND SYSTEM TO PROCESS ISSUE DATA PERTAINING TO A SYSTEM - A computer-implemented method to processes issue data in a system. A plurality of issue reports are received from respective reporting entities, each issue report being in respect of a system issue which requires a response activity. The issue reports are parsed to obtain priority criterion data relating to at least one priority criterion. The priority criterion is unrelated to the dates and/or times of the issue reports and may include visibility data, severity data, exposure data, and performance data relating to past performance of a reporting entity or a reported entity. The reported issues are then prioritized for order of response based at least partially on the associated criterion data. | 2009-08-06 |
20090199055 | Interleaver Design with Unequal Error Protection for Control Information - For transmission of a block of control information within a wireless network, the control information is interleaved to form an ordered set of control bits, wherein more important information bits of the control information are placed into a first portion of the ordered set of control bits, with less important information bits of the control information placed into a second portion of the ordered set of controls bits. The ordered set of control bits is encoded to form an encoded block of data. The encoded block of data is transmitted to a serving base station, wherein bits from the first portion of the ordered set of control bits will statistically have a lower bit error rate (BER) than bits from the second portion of the ordered set of control bits during transmission. | 2009-08-06 |
20090199056 | MEMORY DIAGNOSIS METHOD - A method of an apparatus for diagnosing a memory including a storing module for storing diagnosis information relating to memory errors in a memory to be diagnosed, the apparatus capable of detecting memory errors, the method includes: testing the memory and detecting a memory error for each of a plurality of areas of the memory; dividing at least one of the areas into a plurality of sub-areas upon detection of a memory error in the at least one of the areas; testing the sub-areas and detecting a memory error for each of the plurality of the sub-areas; counting the number of sub-areas where a memory error is detected; and storing information of the number of the sub-areas where a memory error is detected together with information of the at least one of the areas containing the sub-areas into the storing module. | 2009-08-06 |
20090199057 | March DSS: Memory Diagnostic Test - Diagnostic march tests are powerful tests that are capable of detecting, identifying and locating faults in memories. While March SS was published for detecting simple static faults, no test has been published for identifying all faults and locating their involved memory cells. In this report, we target all published simple static faults. We identify faults that can not be distinguished due to their analogous behavior, and we provide a new 46n diagnostic test for the rest named March DSS. March DSS is the first test that is capable of identifying all distinguishable march test and yet has a lower time complexity. | 2009-08-06 |
20090199058 | Programmable memory with reliability testing of the stored data - The invention relates, inter alia, to a method for testing a programmable memory cell having a particular memory state, the method involving the following steps of: applying a first read signal to the memory cell, with the result that the memory cell provides a first memory signal which represents its memory state; comparing the first memory signal with a threshold value in order to obtain a first comparison result; applying a second read signal to the memory cell, with the result that the memory cell provides a second memory signal which represents its memory state; comparing the second memory signal with the threshold value in order to obtain a second comparison result; assessing the integrity of the memory state using the two comparison results. | 2009-08-06 |
20090199059 | Semiconductor memory test device and method thereof - A semiconductor memory test device and method thereof are provided. The example semiconductor memory test device may include a fail memory configured to store at least one test result of a memory under test, a mode selecting unit configured to output a selection signal for selecting a memory address protocol of the fail memory based upon which one of a plurality of test modes is active in the memory under test and an address arranging unit configured to arrange address signals to conform with the selected memory address protocol in response to the selection signal received from the mode selecting unit. | 2009-08-06 |
20090199060 | Information processing apparatus, information processing method, and computer program product - A receiving unit wirelessly receives a packet communication signal. When receiving a packet included in the packet communication signal is failed, a requesting unit issues a retransmission request for retransmitting the packet. A storing unit stores therein packets included in packet communication signals received before and after issuing the retransmission request. A setting unit sets an order of transferring the packets stored in the storing unit to a control unit in an order of receiving the packets without a fail. A transferring unit transfers the packets stored in the storing unit to the control unit in the order set by the setting unit. | 2009-08-06 |
20090199061 | METHOD AND DEVICE FOR PROCESSING DATA IN RETRANSMISSION PROCESSES - A retransmission process control method is provided that increases the efficiency of memory usage in retransmission processes. A method for processing data in multiple retransmission processes, used in a receiving-side communication device, includes; determining whether or not a received signal can be stored in a reception buffer for retransmission processes; when the received signal cannot be stored in the reception buffer, discarding from the reception buffer at least part of existing received signals corresponding to retransmission processes in progress; and storing the received signal into the reception buffer. | 2009-08-06 |
20090199062 | Virtual limited buffer modification for rate matching - Virtual limited buffer modification for rate matching. A reduced-size memory module is employed within a communication device to assist in storage of log-likelihood ratios (LLRs) employed in accordance with turbo decoding. This architecture is also applicable to other types of error correction code (ECC) besides turbo code as well. The memory size is selected to match the number of coded bits (e.g., including information bits and redundancy/parity bits) that is included within a transmission. The received signals may be various transmissions made in accordance with hybrid automatic repeat request (HARQ) transmissions. When the LLRs calculated from a first HARQ transmission is insufficient to decode, those LLRs are selectively stored in the memory module. When LLRs corresponding to a second HARQ transmission is received, LLRs corresponding to both the first HARQ transmission and the second HARQ transmission are passed from the memory module for joint use in decoding. | 2009-08-06 |
20090199063 | METHOD OF TRANSMITTING ACK/NACK SIGNAL IN WIRELESS COMMUNICATION SYSTEM - A method of transmitting an acknowledgment (ACK)/non-acknowledgement (NACK) signal in a wireless communication system includes assigning at least one ACK channel among a plurality of ACK channels which share an ACK channel region for transmitting the ACK/NACK signal, and transmitting the ACK/NACK signal through the at least one ACK channel, wherein the ACK channel region includes at least one tile including a plurality of data subcarriers, and the ACK/NACK signal of each ACK channel is indicated by mapping different orthogonal vectors respectively to the plurality of ACK channels in the tile. | 2009-08-06 |
20090199064 | Corrupted packet toleration and correction system - A corrupted packet toleration and correction system includes a receiver adapted to employ a cross layer protocol that distinguishes between corrupted packets and error-free packets, and tolerates corrupted packets by making side information about corrupted packets available to an application layer. A decoder of the application layer provides hybrid decoding that simultaneously handles errors and erasures and takes advantage of the side information, including employing LDPC (HEEL) based codes over short packet blocks in the cross layer protocol. | 2009-08-06 |
20090199065 | GLDPC ENCODING WITH REED-MULLER COMPONENT CODES FOR OPTICAL COMMUNICATIONS - A method of encoding for optical transmission of information includes encoding information with a generalized low-density parity-check (GLDPC) code for providing coding gains, and constructing the GLDPC code with a Reed-Muller RM code as a component code, the component code being decodable using a maximum posterior probability (MAP) decoding. In a preferred embodiment, the GLDPC code includes a codeword length of substantially 4096, an information word length of substantially 3201, a lower-bound on minimum distance of substantially greater than or equal to 16, a code rate of substantially 0.78 and the RM component code includes an order of substantially 4 and an r parameter of substantially 6. | 2009-08-06 |
20090199066 | METHOD FOR DETERMINING TRANSPORT BLOCK SIZE AND SIGNAL TRANSMISSION METHOD USING THE SAME - A method for determining a transport block size and a signal transmission method using the same are disclosed. When the signal transmission method constructs a transport block size combination by predetermining the transport block size, it prevents the insertion of any dummy bits in consideration of the limitation of an input bit length of an encoder during an encoding step. If a CRC is attached to the transport block and the transport block is segmented into a plurality of code blocks, the signal transmission method can establish a length of the transport block in consideration of a length of the CRC attached to each code block. | 2009-08-06 |