| 34th week of 2009 patent applcation highlights part 14 |
| Patent application number | Title | Published |
|---|
| 20090206397 | Lateral Trench MOSFET with Conformal Depletion-Assist Layer - A lateral trench DMOS device formed in a substrate of a first conductivity type includes a vertical trench lined with a dielectric layer and containing a gate electrode. A source region of a second conductivity is adjacent the surface of the substrate and a sidewall of the trench. A drain region of the second conductivity type is adjacent the surface of the substrate and spaced apart from the source region. A field oxide region is disposed at the surface of the substrate between the source region and the drain region and a drift region of the second conductivity type extends laterally from the trench sidewall to the drain region. A body region of a first conductivity type is disposed between the source region and the drift region, the body region adjacent the trench sidewall where the body region has a profile that is conformal to the field oxide region. | 2009-08-20 |
| 20090206398 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE - A semiconductor device including an n-type semiconductor substrate, a p-type channel region and a junction layer provided between the n-type semiconductor substrate and the p-type channel region is disclosed. The junction layer has n-type drift regions and p-type partition regions alternately arranged in the direction in parallel with the principal surface of the n-type semiconductor substrate. The p-type partition region forming the junction layer is made to have a higher impurity concentration than the n-type drift region. This enables the semiconductor device to have an enhanced breakdown voltage and, at the same time, have a reduced on-resistance. | 2009-08-20 |
| 20090206399 | METHOD OF FORMING A RECESS CHANNEL TRENCH PATTERN, AND FABRICATING A RECESS CHANNEL TRANSISTOR - A method of forming a recess channel trench pattern for forming a recess channel transistor is provided. A mask layer is formed on a semiconductor substrate, which is then patterned to expose an active region and a portion of an adjacent device isolating layer with an isolated hole type pattern. Using this mask layer the semiconductor substrate and the device isolating layer portion are selectively and anisotropically etched, thereby forming a recess channel trench with an isolated hole type pattern. The mask layer may be patterned to be a curved line type. In this case, the once linear portion is curved to allow the device isolating layer portion exposed by the patterned mask layer to be spaced apart from an adjacent active region. The semiconductor substrate and the device isolating layer portion are then etched, thereby forming a recess channel trench with a curved line type pattern. | 2009-08-20 |
| 20090206400 | SYSTEMS AND DEVICES INCLUDING FIN TRANSISTORS AND METHODS OF USING, MAKING, AND OPERATING THE SAME - Disclosed are methods, systems and devices, including a system, having a memory device. In some embodiments, the memory device includes a plurality of fin field-effect transistors disposed in rows, a plurality of insulating fins each disposed between the rows, and a plurality of memory elements each coupled to a terminal of a fin field-effect transistor among the plurality of fin field-effect transistors. | 2009-08-20 |
| 20090206401 | TRENCH TRANSISTOR AND METHOD FOR FABRICATING A TRENCH TRANSISTOR - A trench transistor having a semiconductor body, in which a trench structure and an electrode structure embedded in the trench structure is disclosed. The electrode structure is electrically insulated from the semiconductor body by an insulation structure. The electrode structure has a gate electrode structure and a field electrode structure arranged below the gate electrode structure and electrically insulated from the latter. There is provided between the gate electrode structure and the field electrode structure a shielding structure for reducing the capacitive coupling between the gate electrode structure and the field electrode structure. | 2009-08-20 |
| 20090206402 | Lateral Trench MOSFET with Bi-Directional Voltage Blocking - A lateral trench DMOS device formed in a substrate of a first conductivity type includes a trench extending downward from a surface of the substrate, the trench lined with a dielectric layer and containing a gate electrode. The device includes a source region of a second conductivity type adjacent the surface of the substrate and a sidewall of the trench, a drain region of the second conductivity type adjacent the surface of the substrate and spaced apart from the source region, a body region of the first conductivity type adjacent the source region and the sidewall of the trench, a drift region of the second conductivity type adjacent the body region, the sidewall of the trench and the drain region; and a body contact region of the first conductivity type disposed in the body region and spaced apart from the source region. | 2009-08-20 |
| 20090206403 | METHOD OF TRIMMING A HARD MASK LAYER, METHOD FOR FABRICATING A GATE IN A MOS TRANSISTOR, AND A STACK FOR FABRICATING A GATE IN A MOS TRANSISTOR - A stack structure for forming a gate of a MOS transistor includes a substrate including a plurality of shallow trench isolations therein; a dielectric layer, a conductive layer and a hard mask layer formed on the substrate in sequence; and a tri-layer stack comprising a top photo resist layer, a silicon-containing photo resist layer and a bottom anti-reflective coating (BARC) on the hard mask layer, wherein the silicon-containing photo resist layer comprises 10-30% silicon and the hard mask layer has a high etching selectivity ratio to the conductive layer. | 2009-08-20 |
| 20090206404 | REDUCING EXTERNAL RESISTANCE OF A MULTI-GATE DEVICE BY SILICIDATION - Reducing external resistance of a multi-gate device by silicidation is generally described. In one example, an apparatus includes a semiconductor substrate, a multi-gate fin coupled with the semiconductor substrate, the multi-gate fin having a first surface, a second surface, and a third surface, the multi-gate fin also having a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions wherein the source and drain regions of the multi-gate fin are fully or substantially silicized with a metal silicide, and a spacer dielectric material coupled to the first surface and the second surface wherein the spacer dielectric material substantially covers the first surface and the second surface in the source and drain regions. | 2009-08-20 |
| 20090206405 | FIN FIELD EFFECT TRANSISTOR STRUCTURES HAVING TWO DIELECTRIC THICKNESSES - Fin field-effect-transistor (finFET) structures having two dielectric thicknesses are generally described. In one example, an apparatus includes a semiconductor substrate, a semiconductor fin coupled with the semiconductor substrate, the semiconductor fin having at least a first surface, a second surface, and a third surface, the third surface being substantially parallel to the first surface and substantially perpendicular to the second surface, a spacer dielectric coupled to the second surface of the semiconductor fin, a back gate dielectric having a back gate dielectric thickness coupled to the first surface of the semiconductor fin, and a front gate dielectric having a front gate dielectric thickness coupled to the third surface of the semiconductor fin wherein the back gate dielectric thickness is greater than the front gate dielectric thickness | 2009-08-20 |
| 20090206406 | MULTI-GATE DEVICE HAVING A T-SHAPED GATE STRUCTURE - A multi-gate device having a T-shaped gate structure is generally described. In one example, an apparatus includes a semiconductor substrate, at least one multi-gate fin coupled with the semiconductor substrate, the multi-gate fin having a gate region, a source region, and a drain region, the gate region being positioned between the source and drain regions, a gate dielectric coupled to the gate region of the multi-gate fin, a gate electrode coupled to the gate dielectric, the gate electrode having a first thickness and a second thickness, the second thickness being greater than the first thickness, a first spacer dielectric coupled to a portion of the gate electrode having the first thickness, and a second spacer dielectric coupled to the first spacer dielectric and coupled to the gate electrode where the second spacer dielectric is coupled to a portion of the gate electrode having the second thickness. | 2009-08-20 |
| 20090206407 | SEMICONDUCTOR DEVICES HAVING TENSILE AND/OR COMPRESSIVE STRESS AND METHODS OF MANUFACTURING - A semiconductor device and method of manufacturing is disclosed which has a tensile and/or compressive strain applied thereto. The method includes forming at least one trench in a material; and filling the at least one trench by an oxidation process thereby forming a strain concentration in a channel of a device. The structure includes a gate structure having a channel and a first oxidized trench on a first of the channel, respectively. The first oxidized trench creates a strain component in the channel to increase device performance. | 2009-08-20 |
| 20090206408 | NESTED AND ISOLATED TRANSISTORS WITH REDUCED IMPEDANCE DIFFERENCE - A processing layer, such as silicon, is formed on a metal silicide contact followed by a metal layer. The silicon and metal layers are annealed to increase the thickness of the metal silicide contact. By selectively increasing the thickness of silicide contacts, R | 2009-08-20 |
| 20090206409 | Semiconductor device and method of manufacturing the same - A method of manufacturing a semiconductor device, includes forming a first insulating film containing silicon oxide as a main ingredient, on an underlying region, adhering water to the first insulating film, forming a polymer solution layer containing a silicon-containing polymer on the water-adhered first insulating film, and forming a second insulating film containing silicon oxide as a main ingredient from the polymer solution layer, wherein forming the second insulating film includes forming silicon oxide by a reaction between the polymer and water adhered to the first insulating film. | 2009-08-20 |
| 20090206410 | Semiconductor device and method for manufacturing the same - Semiconductor devices required forming a stress control film to handle different stresses on each side when optimizing the stress on the respective P channel and N channel sections. A unique feature of the semiconductor device of this invention is that P and N channel stress are respectively optimized by making use of a stress control film jointly for the P and N channels that conveys stress in different directions by utilizing the film thickness. | 2009-08-20 |
| 20090206411 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P | 2009-08-20 |
| 20090206412 | HYBRID ORIENTATION SCHEME FOR STANDARD ORTHOGONAL CIRCUITS - Embodiments herein present device, method, etc. for a hybrid orientation scheme for standard orthogonal circuits. An integrated circuit of embodiments of the invention comprises a hybrid orientation substrate, comprising first areas having a first crystalline orientation and second areas having a second crystalline orientation. The first crystalline orientation of the first areas is not parallel or perpendicular to the second crystalline orientation of the second areas. The integrated circuit further comprises first type devices on the first areas and second type devices on the second areas, wherein the first type devices are parallel or perpendicular to the second type devices. Specifically, the first type devices comprise p-type field effect transistors (PFETs) and the second type devices comprise n-type field effect transistors (NFETs). | 2009-08-20 |
| 20090206413 | CMOS INTEGRATION SCHEME EMPLOYING A SILICIDE ELECTRODE AND A SILICIDE-GERMANIDE ALLOY ELECTRODE - A p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) are formed by patterning of a gate dielectric layer, a thin silicon layer, and a silicon-germanium alloy layer. After formation of the source/drain regions and gate spacers, silicon germanium alloy portions are removed from gate stacks. A dielectric layer is formed and patterned to cover an NFET gate electrode, while exposing a thin silicon portion for a PFET. Germanium is selectively deposited on semiconductor surfaces including the exposed silicon portion. The dielectric layer is removed and a metal layer is deposited and reacted with underlying semiconductor material to form a metal silicide for a gate electrode of the NFET, while forming a metal silicide-germanide alloy for a gate electrode of the PFET. | 2009-08-20 |
| 20090206414 | Contact Configuration and Method in Dual-Stress Liner Semiconductor Device - A method for manufacturing a semiconductor device may comprise forming a conductive layer on a substrate, removing at least one portion of the conductive layer to form a plurality of separate conductive lines, forming a first stress-inducing layer of a first stress type on the conductive lines and the substrate, and removing a portion of the first stress-inducing layer such that a remaining portion of the first stress-inducing layer is disposed on a first subset of the conductive lines but not a second subset of the conductive lines and has a boundary disposed between two of the conductive lines. This method, along with other methods and various semiconductor devices, are described. | 2009-08-20 |
| 20090206415 | SEMICONDUCTOR ELEMENT STRUCTURE AND METHOD FOR MAKING THE SAME - A semiconductor element structure includes a first MOS having a first high-K material and a first metal for use in a first gate, a second MOS having a second high-K material and a second metal for use in a second gate and a bridge channel disposed in a recess connecting the first gate and the second gate for electrically connecting the first gate and the second gate, wherein the bridge channel is embedded in at least one of the first gate and the second gate. | 2009-08-20 |
| 20090206416 | DUAL METAL GATE STRUCTURES AND METHODS - Two dummy gate structures containing disposable material portions and metal portions, source and drain regions, and metal semiconductor alloy regions are formed on a semiconductor substrate. A dielectric material layer is deposited and planarized so that top surfaces of the two remaining dummy gate structures are substantially coplanar. A disposable material portion and a metal portion are removed from one dummy gate structure, while the other dummy gate structure is protected. Subsequently, another disposable material portion is removed from the other dummy gate structure. A second metal layer comprising a second metal is deposited and planarized to form two gate electrodes. One gate electrode has a gate dielectric abutting the first metal, while the other electrode has a gate electrode abutting the second metal. Both gate electrodes have substantially the same height since the two top surfaces of the gate electrodes are formed by the same planarization process. | 2009-08-20 |
| 20090206417 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for manufacturing a dual work function semiconductor device is disclosed. In one aspect, a method starts by forming a host dielectric layer over a first and second region of a substrate. A first dielectric capping layer is formed overlying the host dielectric layer on the first and second region and later selectively removed to expose an underlying layer on the first region. A Hf-based dielectric capping layer is formed overlying the underlying layer on the first region and the first dielectric capping layer on the second region. The Hf-based dielectric capping layer is selected to have a healing effect on the exposed surface of the underlying layer on the first region. A control electrode is formed overlaying the Hf-based dielectric capping layer on the first region and on the second region. | 2009-08-20 |
| 20090206418 | Semiconductor Constructions - The invention includes methods of forming PMOS transistors and NMOS transistors. The NMOS transistors can be formed to have a thin silicon-containing material between a pair of metal nitride materials, while the PMOS transistors are formed to have the metal nitride materials directly against one another. The invention also includes constructions which contain an NMOS transistor gate stack having a thin silicon-containing material between a pair of metal nitride materials. The silicon-containing material can, for example, consist of silicon, conductively-doped silicon, or silicon oxide; and can have a thickness of less than or equal to about 30 angstroms. | 2009-08-20 |
| 20090206419 | Monolithically integrated semiconductor assembly having a power component and method for producing a monolithically intergrated semiconductor assembly - A monolithically integrated semiconductor assembly having a power component, and a method for manufacturing a semiconductor assembly, are proposed, a monolithically integrated resistor element being provided between a first terminal and the second region, and a comparatively low-impedance electrical connection through the first region being provided between the resistor element and the second region. | 2009-08-20 |
| 20090206420 | SEMICONDUCTOR DEVICE AND METHOD - A semiconductor device and method is disclosed. One embodiment provides an active region in a semiconductor substrate, including a first terminal region and a second terminal region. wherein the active region is interrupted by an inactive region, wherein an electrical power dissipation in the inactive region is zero or smaller than an electrical power dissipation in the active region; and a metallization layer arranged with respect to the active region on a surface of the semiconductor device and at least partly overlapping the active area, wherein the metallization layer is divided into a first part, in electrical contact to the first terminal region, and a second part, in electrical contact to the second terminal region, wherein the first and the second part are separated by a gap; and wherein the gap and the inactive region are mutually arranged so that an electrical power dissipation below the gap is reduced compared to an electrical power dissipation below the first part and the second part of the metallization layer. | 2009-08-20 |
| 20090206421 | ORGANIC LIGHT EMITTING DISPLAY AND MANUFACTURING METHOD THEREOF - Disclosed are an organic light emitting display and a manufacturing method thereof. The organic light emitting display includes an organic light emitting section that generates a light, a first thin film transistor that drives the organic light emitting section and includes a first polysilicon layer and a first gate electrode formed below the first polysilicon layer, and a second thin film transistor connected to the first thin film transistor and includes a second polysilicon layer and a second gate electrode formed above the second polysilicon layer. The first and second polysilicon layers are formed on the same layer. | 2009-08-20 |
| 20090206422 | Micromechanical diaphragm sensor having a double diaphragm - A method for producing a micromechanical diaphragm sensor, and a micromechanical diaphragm sensor produced with the method. The micromechanical diaphragm sensor has at least one first diaphragm as well as a second diaphragm, which is disposed essentially on top of the first diaphragm. Furthermore, the micromechanical diaphragm sensor has a first cavity and a second cavity, which is essentially disposed above the first cavity. | 2009-08-20 |
| 20090206423 | Method for manufacturing micromechanical components - The present invention relates to a method for manufacturing an acceleration sensor. In the method, thin SOI-wafer structures are used, in which grooves are etched, the walls of which are oxidized. A thick layer of electrode material, covering all other material, is grown on top of the structures, after which the surface is ground and polished chemo-mechanically, thin release holes are etched in the structure, structural patterns are formed, and finally etching using a hydrofluoric acid solution is performed to release the structures intended to move and to open a capacitive gap. | 2009-08-20 |
| 20090206424 | HALL-EFFECT DEVICE WITH MERGED AND/OR NON-MERGED COMPLEMENTARY STRUCTURE - A Hall-effect device with a merged and/or non-merged complementary structure in order to cancel stress induced offsets includes an n-type epitaxial Hall element and a p-type Hall element. The p-type Hall element can be implanted directly on top of the n-type epitaxial Hall element. The merged Hall elements can be biased in parallel to provide a zero-bias depletion layer throughout for isolation. The output of the p-type Hall element can be connected to the geometrically corresponding output of the n-type epitaxial Hall element through a suitable resistance. The output signal can be taken at the outputs of the n-type element. The Hall-effect device can be constructed utilizing standard processes. | 2009-08-20 |
| 20090206425 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided are a semiconductor device having an MTJ element capable of intentionally shifting the variation, at the time of manufacture, of a switching current of an MRAM memory element in one direction; and a manufacturing method of the device. The semiconductor device has a lower electrode having a horizontally-long rectangular planar shape; an MTJ element having a vertically-long oval planar shape formed on the right side of the lower electrode; and an MTJ's upper insulating film having a horizontally-long rectangular planar shape similar to that of the lower electrode and covering the MTJ element therewith. As the MTJ's upper insulating film, a compressive stress insulating film or a tensile stress insulating film for applying a compressive stress or a tensile stress to the MTJ element is employed. | 2009-08-20 |
| 20090206426 | MAGNETORESISTIVE EFFECT ELEMENT - A magnetoresistive element includes first, second, and third fixed layers, first, second, and third spacer layers, and a free layer. The first fixed layer is made of a ferromagnetic material and having an invariable magnetization direction. The first spacer layer is formed on the first fixed layer and made of an insulator. The free layer is formed on the first spacer layer, made of a ferromagnetic material, and having a variable magnetization direction. The second spacer layer is formed on the free layer and made of a nonmagnetic material. The second fixed layer is formed on the second spacer layer, made of a ferromagnetic material, and having an invariable magnetization direction. The third spacer layer is formed below the first fixed layer and made of a nonmagnetic material. The third fixed layer is formed below the third spacer layer, made of a ferromagnetic material, and having an invariable magnetization direction. | 2009-08-20 |
| 20090206427 | MAGNETIC MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A magnetic memory device and a method of fabricating the same. The magnetic memory device includes a free layer, a write element, and a read element. The write element changes the magnetization direction of the free layer, and the read element senses the magnetization direction of the free layer. Herein, the write element includes a current confinement layer having a width smaller than the minimum width of the free layer to locally increase the density of a current flowing through the write element. | 2009-08-20 |
| 20090206428 | Direct Electron Detector - An electron detector ( | 2009-08-20 |
| 20090206429 | ANGLED IMPLANT FOR TRENCH ISOLATION - A trench isolation having a sidewall and bottom implanted region located within a substrate of a first conductivity type is disclosed. The sidewall and bottom implanted region is formed by an angled implant, a 90 degree implant, or a combination of an angled implant and a 90 degree implant, of dopants of the first conductivity type. The sidewall and bottom implanted region located adjacent the trench isolation reduces surface leakage and dark current. | 2009-08-20 |
| 20090206430 | SOLID-STATE IMAGING DEVICE AND METHOD FOR MANUFACTURING THE SAME - A pattern ( | 2009-08-20 |
| 20090206431 | Imager wafer level module and method of fabrication and use - Imager wafer level modules, methods of assembly for imager wafer level modules, and systems containing imager wafer level modules. An imager die and an optic lens stack are combined to form a module assembly. The module assembly is combined with a molded plastic, laminated plastic, or metallic interposer to form an imager wafer level module capable of assembly using industry standard equipment sets for all processing, and capable of being used with various imaging systems. | 2009-08-20 |
| 20090206432 | IMAGE SENSOR AND METHOD OF MANUFACTURING THE SAME - An image sensor and a method of manufacturing the same are provided. The image sensor includes a substrate having a sensor array area and a peripheral circuit area a first insulating film structure formed on the peripheral circuit area and including a plurality of first multi-layer wiring lines and a second insulating film structure formed on the sensor array area and including a plurality of second multi-layer wiring lines. The uppermost-layer wiring line of the plurality of first multi-layer wiring lines is higher than that of the uppermost-layer wiring line of the plurality of second multi-layer wiring lines. The first insulating film structure includes an isotropic etch-stop layer, and the second insulating film structure does not include the isotropic etch-stop layer. | 2009-08-20 |
| 20090206433 | Image sensor and method for manufacturing the same - An image sensor and a method for manufacturing the same that includes a dielectric layer having a trench formed therein, a first micro-lens having a first structure formed in the trench, and a second micro-lens having a second structure formed over and contacting the first micro-lens such that the second structure is different than the first structure. | 2009-08-20 |
| 20090206434 | PHOTOELECTRIC CONVERSION DEVICE AND METHOD OF MANUFACTURING THE SAME - A photoelectric conversion device comprises a semiconductor substrate and a multilayer wiring structure, wherein the multilayer wiring structure includes a first wiring layer which serves as a top wiring layer in an effective region and contains aluminum as a principal component, a first insulation film arranged in the effective region and an light-shielded region so as to cover the first wiring layer, and a second wiring layer which serves as a top wiring layer arranged on the first insulation film in the light-shielded region and contains aluminum as a principal component, and wherein the first insulation film has, in the effective region, a first portion which is positioned above the photoelectric conversion unit, and the first portion functions as at least a part of an interlayer lens. | 2009-08-20 |
| 20090206435 | Solid state imaging device, manufacturing method of the same, and substrate for solid state imaging device - A method of manufacturing a solid state imaging device having photoelectric conversion devices, the method including: 1) forming a plurality of color filters differing in color from each other, 2) forming a transparent resin layer on the color filters, 3) forming an etching control layer on the transparent resin layer, the etching control layer being enabled to be etched at a different etching rate from the etching rate of the transparent resin layer, 4) forming a lens master on the etching control layer by using a heatflowable resin material, 5) transferring a pattern of the lens master to the etching control layer by dry etching to form an intermediate micro lens, and 6) transferring a pattern of the intermediate micro lens to the transparent resin layer by dry etching to form the transfer lenses. | 2009-08-20 |
| 20090206436 | SEMICONDUCTOR APPARATUS - An improved semiconductor apparatus that comprises an elongated structure that extends into the substrate. The apparatus comprises a collection contact, a resistive path, a bias connection that creates along the length of the elongated structure, an electric field component that drives signal charge carriers in a direction perpendicular to the elongated structure, and a second bias that generates a current flow that creates within the substrate a constant electric field component to drive signal charge carriers towards the collection contact on the first surface. | 2009-08-20 |
| 20090206437 | Photo-detecting apparatus and photo-detecting method - A photo-detecting apparatus includes a photodiode that coverts light into electricity, a reverse-voltage switching unit that switches a reverse voltage to be applied to the photodiode, a current-difference detecting unit that detects a change in an output current of the photodiode occurring due to switching of the reverse voltage as a current difference, a correspondence retaining unit that retains a correspondence between the current difference and a dark current, a dark-current calculating unit that calculates a dark current by referring to the correspondence based on the current difference detected by the current-difference detecting unit, and a dark-current correcting unit that corrects the output current of the photodiode based on the dark current to find a photocurrent obtained through photoelectric conversion. | 2009-08-20 |
| 20090206438 | Semiconductor component - A semiconductor component and a method for manufacturing such a semiconductor component which has a resistance behavior which depends heavily on the temperature. This resistance behavior is obtained by a special multi-layer structure of the semiconductor component, one layer being designed in such a way that, for example, multiple p-doped regions are present in an n-doped region, said regions being short-circuited on one side via a metal-plated layer. For example, the semiconductor component may be used for reducing current peaks, by being integrated into a conductor. In the cold state, the semiconductor component has a high resistance which becomes significantly lower when the semiconductor component is heated as a result of the flowing current. | 2009-08-20 |
| 20090206439 | Semiconductor device - In order to provide an ESD protection circuit having high immunity to ESD destruction without increasing a chip area of a semiconductor device, a diode-type ESD protection circuit formed of a junction between a first conductivity type diffusion layer and a second conductivity type diffusion layer is formed in an entire peripheral region or a part of the peripheral region outside of internal circuits and bonding pads of the chip, and a diffusion layer formed to fix a substrate potential of the chip and electrically connected to a power source or a ground provided in the peripheral region of the chip is used for any one of the first conductivity type diffusion layer and the second conductivity type diffusion layer, permitting enlargement of the size of the ESD protection circuit without increasing a chip area, and enhancement of immunity to ESD destruction of the semiconductor device. | 2009-08-20 |
| 20090206440 | Power Semiconductor Device - A semiconductor device has a heavily doped substrate and an upper layer with doped silicon of a first conductivity type disposed on the substrate, the upper layer having an upper surface and including an active region that comprises a well region of a second, opposite conductivity type. An edge termination zone has a junction termination extension (JTE) region of the second conductivity type, the region having portions extending away from the well region and a number of field limiting rings of the second conductivity type disposed at the upper surface in the junction termination extension region. | 2009-08-20 |
| 20090206441 | METHOD OF FORMING COPLANAR ACTIVE AND ISOLATION REGIONS AND STRUCTURES THEREOF - Methods of forming coplanar active regions and isolation regions and structures thereof are disclosed. One embodiment includes shallow-trench-isolation (STI) formation in a semiconductor-on-insulator (SOI) layer on a substrate of a semiconductor structure; and bonding a handle wafer to the STI and SOI layer to form an intermediate structure. The intermediate structure may have a single layer including at least one STI region and at least one SOI region therein disposed between the damaged substrate and the handle wafer. The method may also include cleaving the hydrogen implanted substrate and removing any residual substrate to expose a surface of the at least one STI region and a surface of the at least one SOI region. The exposed surface of the at least one STI region forms an isolation region and the exposed surface of the at least one SOI region forms an active region, which are coplanar to each other. | 2009-08-20 |
| 20090206442 | METHOD AND STRUCTURE FOR RELIEVING TRANSISTOR PERFORMANCE DEGRADATION DUE TO SHALLOW TRENCH ISOLATION INDUCED STRESS - A method of forming shallow trench isolation (STI) regions for semiconductor devices, the method including defining STI trench openings within a semiconductor substrate; filling the STI trench openings with an initial trench fill material; defining a pattern of nano-scale openings over the substrate, at locations corresponding to the STI trench openings; transferring the pattern of nano-scale openings into the trench fill material so as to define a plurality of vertically oriented nano-scale openings in the trench fill material; and plugging upper portions of the nano-scale openings with additional trench fill material, thereby defining porous STI regions in the substrate. | 2009-08-20 |
| 20090206443 | DEVICES INCLUDING FIN TRANSISTORS ROBUST TO GATE SHORTS AND METHODS OF MAKING THE SAME - Disclosed are methods, systems and devices, including a method that includes the acts of etching an inter-row trench in a substrate, substantially or entirely filling the inter-row trench with a dielectric material, and forming a fin and a insulating projection at least in part by etching a gate trench in the substrate. In some embodiments, the insulating projection includes at least some of the dielectric material in the inter-row trench. | 2009-08-20 |
| 20090206444 | INTEGRATED SEMICONDUCTOR DEVICE - An integrated semiconductor device includes a plurality of semiconductor elements having different integrated element circuits or different sizes; an insulating material arranged between the semiconductor elements; an organic insulating film arranged entirely on the semiconductor elements and the insulating material; a fine thin-layer wiring that arranged on the organic insulating film and connects the semiconductor elements; a first input/output electrode arranged on an area of the insulating material; and a first bump electrode formed on the first input/output electrode. | 2009-08-20 |
| 20090206445 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device may include, but is not limited to, first and second well regions, and a well isolation region isolating the first and second well regions. The first and second well regions each may include an active region, a device isolation groove that defines the active region, and a device isolation insulating film that fills the device isolation groove. The first and second well regions may include first and second well layers, respectively. The well isolation region may include a well isolation groove, a well isolation insulating film that fills the well isolation groove, and a diffusion stopper layer disposed under a bottom of the well isolation groove. The first and second well layers have first and second bottoms respectively, which are deeper in depth than a bottom of the device isolation groove and shallower in depth than the bottom of the well isolation groove. | 2009-08-20 |
| 20090206446 | Electrical Device and Fabrication Method - An electrical device with a fin structure, a first section of the fin structure having a first width and a first height, a second section of the fin structure having a second width and a second height, wherein the first width is smaller than the second width and the first height is lower than the second height. | 2009-08-20 |
| 20090206447 | ANTI-FUSE DEVICE STRUCTURE AND ELECTROPLATING CIRCUIT STRUCTURE AND METHOD - Disclosed are embodiments of a circuit and method for electroplating a feature (e.g., a BEOL anti-fuse device) onto a wafer. The embodiments eliminate the use of a seed layer and, thereby, minimize subsequent processing steps (e.g., etching or chemical mechanical polishing (CMP)). Specifically, the embodiments allow for selective electroplating metal or alloy materials onto an exposed portion of a metal layer in a trench on the front side of a substrate. This is accomplished by providing a unique wafer structure that allows a current path to be established from a power supply through a back side contact and in-substrate electrical connector to the metal layer. During electrodeposition, current flow through the current path can be selectively controlled. Additionally, if the electroplated feature is an anti-fuse device, current flow through this current path can also be selectively controlled in order to program the anti-fuse device. | 2009-08-20 |
| 20090206448 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device that prevents the leaning of storage node when forming a capacitor having high capacitance includes a plurality of cylinder-shaped storage nodes formed over a semiconductor substrate; and support patterns formed to fix the storage nodes in the form of an ‘L’ or a ‘+’ when viewed from the top. This semiconductor device having support patterns in the form of an ‘L’ or a ‘+’ reduces stress on the storage nodes when subsequently forming a dielectric layer and plate nodes that prevents the capacitors from leaking. | 2009-08-20 |
| 20090206449 | STRESS-MODIFIED DEVICE STRUCTURES, METHODS OF FABRICATING SUCH STRESS-MODIFIED DEVICE STRUCTURES, AND DESIGN STRUCTURES FOR AN INTEGRATED CIRCUIT - Stress-modified device structures, methods of fabricating such stress-modified device structures, and design structures for an integrated circuit. An electrical characteristic of semiconductor devices formed on a common substrate, such as the current gains of bipolar junction transistors, may be altered by modifying stresses in structures indirectly on or over, or otherwise indirectly coupled with, the semiconductor devices. The structures, which may be liners for contacts in a contact level of an interconnect, are physically spaced away from, and not in direct physical contact with, the respective semiconductor devices because at least one additional intervening material or structure is situated between the stress-imparting structures and the stress-modified devices. The intervening materials or structures, such as contacts extending through an insulating layer of a local interconnect level between the contact level and the semiconductor devices, provide paths for the transfer of stress from the stress-imparting structures to the stress-modified semiconductor devices. | 2009-08-20 |
| 20090206450 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE OBTAINED HEREWITH, AND SLURRY SUITABLE FOR USE IN SUCH A METHOD - The invention relates to a method of manufacturing a semiconductor device ( | 2009-08-20 |
| 20090206451 | Semiconductor device - A semiconductor device is provided, in which a well contact diffusion layer pattern ( | 2009-08-20 |
| 20090206452 | METHOD AND SYSTEM FOR CREATING SELF-ALIGNED TWIN WELLS WITH CO-PLANAR SURFACES IN A SEMICONDUCTOR DEVICE - A method and system for providing a twin well in a semiconductor device is described. The method and system include providing at least one interference layer and providing a first mask that covers a first portion of the semiconductor device and uncovers a second portion of the semiconductor device. The first and second portions of the semiconductor device are adjacent. The method and system also include implanting a first well in the second portion of the semiconductor device after the first mask is provided. The method and system also include providing a second mask. The interference layer(s) are configured such that energy during a blanket exposure develops the second mask that uncovers the first portion and covers the second portion of the semiconductor device. The method and system also include implanting a second well in the first portion of the semiconductor device after the second mask is provided. | 2009-08-20 |
| 20090206453 | Method for Preparing Modified Porous Silica Films, Modified Porous Silica Films Prepared According to This Method and Semiconductor Devices Fabricated Using the Modified Porous Silica Films - A hydrophobic compound having at least one each of hydrophobic group (an alkyl group having 1 to 6 carbon atoms or a —C | 2009-08-20 |
| 20090206454 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes the steps of: forming a first insulating film on a semiconductor substrate; removing part of the first insulating film; forming a second insulating film having a leakage current density higher than that of the first insulating film on a region where the part of the first insulating film has been removed on the semiconductor substrate; forming an undoped semiconductor film on the first and second insulating films; implanting an impurity into part of the undoped semiconductor film, thereby defining semiconductor regions of a first conductivity type dotted as discrete islands; forming a third insulating film on the semiconductor regions of the first conductivity type and the undoped semiconductor film; and removing part of the third insulating film by wet etching. At least the second insulating film is formed under the semiconductor regions of the first conductivity type. | 2009-08-20 |
| 20090206455 | INTEGRATED CIRCUIT STACKED PACKAGE PRECURSORS AND STACKED PACKAGED DEVICES AND SYSTEMS THEREFROM - A package-on-package (POP) package precursor and packaged devices and systems therefrom includes an electronic substrate including electrically conductive layers and a top surface. A first portion of the top surface has an IC die attached thereon. A second portion of the top surface has a plurality of first attach pads on opposing sides of the IC die for electrically coupling to a first electronic device on top of the IC die. At least a third portion of the top surface is positioned laterally with respect to the first and second portion. The third portion includes a plurality of second attach pads for electrically coupling to at least a second electronic device. At least one of the electrically conductive layers includes a coupling trace that couples at least one of the plurality of second attach pads to the IC die and/or one or more of the plurality of first attach pads. | 2009-08-20 |
| 20090206456 | MODULE INCLUDING A SINTERED JOINT BONDING A SEMICONDUCTOR CHIP TO A COPPER SURFACE - A module includes a substrate including a first copper surface and a semiconductor chip. The module includes a first sintered joint bonding the semiconductor chip directly to the first copper surface. | 2009-08-20 |
| 20090206457 | RESIN MOLDING PART AND MANUFACTURING METHOD THEREOF - A primary molding product is formed by integrally forming a first lead frame and a second lead frame with a primary molding resin portion. In addition, in order to prevent separation of the first lead frame and the second lead frame from the primary molding resin portion, a hook-and-hold portion for preventing separation of the first lead frame from the primary molding resin portion and separation of the second lead frame from the primary molding resin portion is provided on an outer surface of each of the first lead frame and the second lead frame. Thus, a resin molding part capable of achieving suppression of increase in a thickness thereof without deformation or displacement of a lead frame and a manufacturing method thereof can be provided. | 2009-08-20 |
| 20090206458 | FLAT LEADLESS PACKAGES AND STACKED LEADLESS PACKAGE ASSEMBLIES - A flat leadless package includes at least one die mounted onto a leadframe and electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, an assembly includes stacked leadless packages electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, a package module includes an assembly of stacked leadless packages mounted on a support and electrically connected to circuitry in the support using an electrically conductive polymer or an electrically conductive ink. | 2009-08-20 |
| 20090206459 | QUAD FLAT NON-LEADED PACKAGE STRUCTURE - A quad flat non-leaded package structure including a die pad, a plurality of leads, a chip, and a molding compound is provided. The die pad has a top surface and an opposite bottom surface, and the leads are disposed around the die pad. A concave portion is disposed at the end of each leads. The chip is disposed on the top surface of the die pad and is electrically connected to the leads. The molding compound encapsulates the chip, a portion of the leads and the die pad, and fills the gaps between the leads. | 2009-08-20 |
| 20090206460 | Intermediate Bond Pad for Stacked Semiconductor Chip Package - The invention provides apparatus and methods by which, in a stacked semiconductor chip package, a continuous electrical path may be provided among bond pads by way of one or more intermediate bond pad electrically isolated from its underlying surface. | 2009-08-20 |
| 20090206461 | INTEGRATED CIRCUIT AND METHOD - An integrated circuit and method of fabricating an integrated circuit. One embodiment includes a circuit chip, a contact pad, and a projecting top contact. A signal line couples the contact pad to the projecting top contact, the contact pad, the projecting top contact. The signal line is arranged on a top face of the circuit chip. A substrate and a lower contact pad, the lower contact pad is arranged on a bottom face of the substrate and the circuit chip is arranged on a top face of the substrate. A bottom face of the circuit chip is facing the top face of the substrate. A connection couples the contact pad on the circuit chip to the lower contact pad. | 2009-08-20 |
| 20090206462 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF - A semiconductor device | 2009-08-20 |
| 20090206463 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC EQUIPMENT USING THE SAME - A semiconductor device includes a substrate | 2009-08-20 |
| 20090206464 | METHOD OF FORMING SEMICONDUCTOR CHIPS, THE SEMICONDUCTOR CHIPS SO FORMED AND CHIP-STACK PACKAGE HAVING THE SAME - Provided are methods of fabricating semiconductor chips, semiconductor chips formed by the methods, and chip-stack packages having the semiconductor chips. One embodiment specifies a method that includes patterning a scribe line region of a semiconductor substrate to form a semiconductor strut spaced apart from edges of a chip region of the semiconductor substrate. | 2009-08-20 |
| 20090206465 | SEMICONDUCTOR CHIP PACKAGE STRUCTURE FOR ACHIEVING ELECTRICAL CONNECTION WITHOUT USING A WIRE-BONDING PROCESS AND METHOD FOR MAKING THE SAME - A semiconductor chip package structure for achieving electrical connection without using a wire-bonding process includes: a package unit, a semiconductor chip, a first insulative layer, first conductive layers, a second insulative layer, and second conductive layers. The package unit has a receiving groove. The semiconductor chip receives in the receiving groove and has a plurality of conductive pads disposed on its top surface. The first insulative layer is formed among the conductive pads in order to insulate the conductive pads from each other. The first conductive layers are formed on the first insulative layer, and one side of each first conductive layer is electrically connected to the corresponding conductive pad. The second insulative layer is formed among the first conductive layers in order to insulate the first conductive layers from each other. The second conductive layers are respectively formed on the other opposite sides of the first conductive layers. | 2009-08-20 |
| 20090206466 | SEMICONDUCTOR DEVICE - A semiconductor device is provided that can further reduce the thickness of an electronic device and that can reduce its own mounting area and development period. This semiconductor device has a first semiconductor chip and a second semiconductor chip, and is formed in a WLCSP type package. On the upper surface of the first semiconductor chip, an integrated circuit is formed and, in a region other than where it is formed, a recess is formed. An integrated circuit is formed on the second semiconductor chip. The second semiconductor chip is provided in the recess of the first semiconductor chip such that the upper surface of the first semiconductor chip is level with that of the second semiconductor chip. | 2009-08-20 |
| 20090206467 | INTEGRATED CIRCUIT PACKAGE | 2009-08-20 |
| 20090206468 | Board on chip package and manufacturing method thereof - A method of manufacturing a board on chip package including laminating a dry film on a carrier film, one side of which is laminated by a thin metal film; patterning the dry film in accordance with a circuit wire through light exposure and developing process, and forming a solder ball pad and a circuit wire; removing the dry film; laminating an upper photo solder resist excluding a portion where the solder ball pad is formed; etching the thin metal film formed on a portion where the upper photo solder resist is not laminated; mounting a semiconductor chip on the solder ball pad by a flip chip bonding; molding the semiconductor chip with a passivation material; removing the carrier film and the thin metal film; and laminating a lower photo solder resist under the solder ball pad. The board on chip package provides a high density circuit since a circuit pattern is formed using a seed layer. | 2009-08-20 |
| 20090206469 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device has a plurality of wafers which are laminated to each other, wherein: each wafer includes an lamination surface to which another wafer is laminated and a substrate having an element formed thereon; the lamination surface is provided with an electric signal connecting portion that electrically connects to said another wafer so as to form a semiconductor circuit; at least one of the electrical signal connecting portions facing each other is a protruding connection portion that protrudes from a region which exposes the substrate on the lamination surface; and a reinforcing protruding portion that is insulated from the semiconductor circuit, and is formed of the same material as the substrate to protrude from the lamination surface with a height equal to the length of a gap between the lamination surfaces of wafers facing each other is provided in an area where the protruding connection portion is not disposed on the lamination surface formed with the protruding connection portion. | 2009-08-20 |
| 20090206470 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SEMICONDUCTOR DEVICE, AND WIRING BOARD - In a semiconductor device manufacturing method, a semiconductor chip is mounted on a support board so as to expose a side of the semiconductor chip on which a plurality of terminal electrodes are provided. An insulating layer is formed so as to cover the side of the semiconductor chip on which the terminal electrodes are provided. Through electrodes connecting to the terminal electrodes and piercing the insulating layer are formed. Metal wirings connecting to the through electrodes are formed on the insulating layer. External terminal electrodes connecting the metal wiring are formed. Second spacing, spacing between the adjacent external terminal electrodes, is larger than first spacing, spacing between the adjacent terminal electrodes. | 2009-08-20 |
| 20090206471 | Electronic parts packaging structure and method of manufacturing the same - An electronic parts packaging structure of the present invention includes a wiring substrate having a wiring pattern, a first insulating film which is formed on the wiring substrate and which has an opening portion in a packaging area where an electronic parts is mounted, the electronic parts having a connection terminal flip-chip mounted on the wiring pattern exposed in the opening portion of the first insulating film, a second insulating film for covering the electronic parts, a via hole formed in a predetermined portion of the first and second insulating films on the wiring pattern, and an upper wiring pattern formed on the second insulating film and connected to the wiring pattern through the via hole. | 2009-08-20 |
| 20090206472 | COF PACKAGING STRUCTURE, METHOD OF MANUFACTURING THE COF PACKAGING STRUCTURE, AND METHOD FOR ASSEMBLING A DRIVER IC AND THE COF PACKAGING STRUCTURE THEREOF - A COF packaging structure includes a substrate, a first conductive foil, and a second conductive foil. The substrate has a first surface and a second surface opposite to the first surface. The first conductive foil is disposed on the first surface of the substrate and has a first designated pattern for bump bonding. The second conductive foil is disposed on the second surface of the substrate and has a second designated pattern, wherein the area of the second designated pattern is not smaller than the area of the first designated pattern. | 2009-08-20 |
| 20090206473 | System and Method for Integrated Waveguide Packaging - A millimeter wave system or package may include at least one printed wiring board (PWB), at least one integrated waveguide interface, and at least one monolithic microwave integrated circuit (MMIC). The package may be assembled in panel form incorporating parallel manufacturing techniques. | 2009-08-20 |
| 20090206474 | ELECTRICAL DEVICE AND METHOD OF MANUFACTURING ELECTRICAL DEVICES USING FILM EMBOSSING TECHNIQUES TO EMBED INTEGRATED CIRCUITS INTO FILM - An electrical device and method of making same is provided wherein a chip or other electrical component is embedded in a substrate. The substrate may be a thermoplastic material capable of deforming around the chip and at least partially encasing the chip when heat and/or pressure is applied to the substrate. Electromagnetic radiation such a near infrared radiation can be used to heat the substrate. The substrate may include a compressible layer that can be compressed and/or crushed to form a recess into which the chip can be inserted. Once embedded, the chip or electrical component is secured by the substrate and may be coupled to another electrical component. A method of making an RFID transponder is also provided wherein an RFID chip is embedded in a substrate using heat and/or pressure, an antenna structure is applied to the substrate, and the RFID chip and antenna structure are coupled together. | 2009-08-20 |
| 20090206475 | Method of manufacturing semiconductor device, and semiconductor device - A method of manufacturing a semiconductor device which includes step of forming a lower resist film over an insulating interlayer; forming a first opening having a circular geometry in a plan view, and second to fifth openings arranged respectively on four sides of the first opening, in the lower resist film; and etching the film-to-be-etched while using the lower resist film as a mask, wherein in the step of etching the film-to-be-etched, a hardened layer is formed in a region of the lower resist film fallen between the first opening and each of the second to fifth openings, and the film-to-be-etched is etched while using the hardened layers as a mask, so as to form a contact hole having a rectangular geometry in a plan view in the film-to-be-etched at a position correspondent to the first opening of the lower resist film. | 2009-08-20 |
| 20090206476 | CONDUCTIVE STRUCTURE FOR A SEMICONDUCTOR INTEGRATED CIRCUIT - A conductive structure for a semiconductor integrated circuit is provided. The semiconductor integrated circuit comprises a pad, and a passivation layer partially overlapping the pad, which jointly define an opening portion. The conductive structure is adapted to be electrically connected to the pad through the opening portion. The conductive structure comprises an under bump metal (UBM). A first conductor layer formed on the under bump metal is electrically connected to the under bump metal. A second conductor layer formed on the first conductor layer and electrically connected to the first conductor layer and a cover conductor layer. Furthermore, the under bump metal, the first conductor layer, and the second conductor jointly define a basic bump structure. The cover conductor layer is adapted to cover the basic bump structure. | 2009-08-20 |
| 20090206477 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device has a plurality of wafers which are laminated to each other, wherein: each wafer comprises an lamination surface to which another wafer is laminated; the lamination surface is provided with an electric signal connecting portion that electrically connects to said another surface so as to form a semiconductor circuit; at least one of the electrical signal connecting portions facing each other is a protruding connection portion that protrudes from the lamination surface; and a reinforcing protruding portion that is insulated from the semiconductor circuit and is provided in an area where the protruding connection portion is not disposed on the lamination surface formed with the protruding connection portion so as to protrude from the lamination surface with a height equal to or larger than that of the protruding connection portion. | 2009-08-20 |
| 20090206478 | FLIP CHIP DEVICE AND MANUFACTURING METHOD THEREOF - A flip chip device made using LCD-COG (liquid crystal display-chip on glass) technique. The flip chip device comprises a substrate, at least one chip having active area with a plurality of compliant bumps thereon. The compliant bumps are centrally disposed in the center of the chip for electrically connecting the chip and the substrate. An adhesive is daubed on a joint area of the substrate and the chips for jointing the substrate and the chips. By limiting the position of the compliant bumps so that they are centrally disposed on the chips, the thermal warpage of the substrate is reduced. | 2009-08-20 |
| 20090206479 | SOLDER INTERCONNECT PADS WITH CURRENT SPREADING LAYERS - Structure and methods of making the structures. The structures include a structure, comprising: an organic dielectric passivation layer extending over a substrate; an electrically conductive current spreading pad on a top surface of the organic dielectric passivation layer; an electrically conductive solder bump pad comprising one or more layers on a top surface of the current spreading pad; and an electrically conductive solder bump containing tin, the solder bump on a top surface of the solder bump pad, the current spreading pad comprising one or more layers, at least one of the one or more layers consisting of a material that will not form an intermetallic with tin or at least one of the one or more layers is a material that is a diffusion barrier to tin and adjacent to the solder bump pad. | 2009-08-20 |
| 20090206480 | FABRICATING LOW COST SOLDER BUMPS ON INTEGRATED CIRCUIT WAFERS - A low cost method of forming solder bumps on an integrated circuit (IC) wafer includes depositing solder directly onto stud bumps formed on bond pads of the IC wafer. In some implementations, stud bumps are formed on the IC wafer by performing wire ball-bonding onto metal bond pads of the wafer. Photodefinable solder mask material is applied to the wafer and cured. The photodefinable solder mask material is exposed to form open solder mask areas at the metal bond pad areas. Solder paste is applied into the open solder mask areas. Reflowing the solder paste on the wafer forms solder bumps that wet to the stud bumps. The solder mask is then stripped from the wafer. Other processes (e.g., a wave-soldering machine, stencil or screen printing process) can also be used to wet solder onto stud bumps to form solder bumps. | 2009-08-20 |
| 20090206481 | STACKING OF TRANSFER CARRIERS WITH APERTURE ARRAYS AS INTERCONNECTION JOINTS - An interconnection mechanism between plated through holes is disclosed, a first embodiment includes a first substrate having a first plated through hole; a second substrate having a second plated through hole; a metal core is configured in between the two plated through holes; the metal ball has a diameter larger than a diameter of the plated through holes; and melted solder binds the first plated through hole, metal core, and the second plated through hole. A second embodiment includes stacked substrate having a gold plated only on ring pads of the plated through holes; melted solder binds the two gold ring pads. | 2009-08-20 |
| 20090206482 | TOOLING METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICES FABRICATED THEREOF - A tooling method for fabricating semiconductor devices includes identifying two adjacent device lines having a device-to-device spacing width in an active region of a substrate, performing an operation to selectively define a first region as a region between the two adjacent device lines overlapping the active region, forming a first block pattern corresponding to the first region on a photomask when the device-to-device spacing width is equal to a predetermined value, and transferring the first block pattern to the substrate. | 2009-08-20 |
| 20090206483 | NANOTUBE AND METAL COMPOSITE INTERCONNECTS - Nanotube and metal composite interconnects are generally described. In one example, an apparatus includes an interlayer dielectric (ILD) and one or more interconnect structures coupled to the ILD, the one or more interconnect structures including a composite of metal and one or more nanotubes. | 2009-08-20 |
| 20090206484 | MICROSTRUCTURE MODIFICATION IN COPPER INTERCONNECT STRUCTURE - Cobalt is added to a copper seed layer, a copper plating layer, or a copper capping layer in order to modify the microstructure of copper lines and vias. The cobalt can be in the form of a copper-cobalt alloy or as a very thin cobalt layer. The grain boundaries configured in bamboo microstructure in the inventive metal interconnect structure shut down copper grain boundary diffusion. The composition of the metal interconnect structure after grain growth contains from about 1 ppm to about 10% of cobalt in atomic concentration. Grain boundaries extend from a top surface of a copper-cobalt alloy line to a bottom surface of the copper-cobalt alloy line, and are separated from any other grain boundary by a distance greater than a width of the copper-cobalt alloy line. | 2009-08-20 |
| 20090206485 | NOVEL STRUCTURE AND METHOD FOR METAL INTEGRATION - An interconnect structure including a gouging feature at the bottom of one of the via openings and a method of forming the same are provided. In accordance with the present invention, the method of forming the interconnect structure does not disrupt the coverage of the deposited diffusion barrier in the overlying line opening, nor does it introduce damages caused by Ar sputtering into the dielectric material including the via and line openings. In accordance with the present invention, such an interconnect structure contains a diffusion barrier layer only within the via opening, but not in the overlying line opening. This feature enhances both mechanical strength and diffusion property around the via opening areas without decreasing volume fraction of conductor inside the line openings. In accordance with the present invention, such an interconnect structure is achieved by providing the gouging feature in the bottom of the via opening prior to formation of the line opening and deposition of the diffusion barrier in said line opening. | 2009-08-20 |
| 20090206486 | WIREBOND OVER POST PASSIVATION THICK METAL - A chip assembly includes a semiconductor chip and a wirebonded wire. The semiconductor chip includes a passivation layer over a silicon substrate and over a thin metal structure, a first thick metal layer over the passivation layer and on a contact point of the thin metal structure exposed by an opening in the passivation layer, a polymer layer over the passivation layer and on the first thick metal layer, and a second thick metal layer on the polymer layer and on the first thick metal layer exposed by an opening in the polymer layer. The first thick metal layer includes a copper layer with a thickness between 3 and 25 micrometers. The wirebonded wire is bonded to the second thick metal layer. | 2009-08-20 |
| 20090206487 | WIRE BONDING SUBSTRATE AND FABRICATION THEREOF - A method for forming a wire bonding substrate is disclosed. A substrate comprising a first surface and a second surface is provided. A through hole is formed in the substrate. A conductive layer is formed on the first surface and the second surface of the substrate and covers a sidewall of the through hole. The conductive layer on the first surface of the substrate is patterned to form at least a first conductive pad, and the conductive layer on the second surface of the substrate is patterned to form at least a second conductive pad. An insulating layer is formed on the first surface and the second surface of the substrate and covers the first conductive pad and the second conductive pad. The insulating layer is recessed until top surfaces of the first conductive pad and the second conductive pad are exposed. A first metal layer is electroplated on the first conductive pad by applying current from the second conductive pad to the first conductive pad through the conductive layer passing the through hole. | 2009-08-20 |
| 20090206488 | THROUGH SUBSTRATE ANNULAR VIA INCLUDING PLUG FILLER - A through substrate via includes an annular conductor layer at a periphery of a through substrate aperture, and a plug layer surrounded by the annular conductor layer. A method for fabricating the through substrate via includes forming a blind aperture within a substrate and successively forming and subsequently planarizing within the blind aperture a conformal conductor layer that does not fill the aperture and plug layer that does fill the aperture. The backside of the substrate may then be planarized to expose at least the planarized conformal conductor layer. | 2009-08-20 |
| 20090206489 | DUAL DAMASCENE METAL INTERCONNECT STRUCTURE HAVING A SELF-ALIGNED VIA - A recessed region containing a line portion and a bulge portion is formed in a hard mask layer. Self-assembling block copolymers containing two or more different polymeric block components that are immiscible with one another are applied within the recessed region and annealed. A cylindrical polymeric block centered at the bulge portion is removed selective to a polymeric block matrix surrounding the cylindrical polymeric block. A via cavity is formed by transferring the cavity formed by removal of the cylindrical polymeric block into a dielectric layer. The pattern in the hard mask layer is subsequently transferred into the dielectric layer to form a line cavity. A metal via and a metal line are formed by deposition and planarization of metal. The metal via is self-aligned to the metal line. | 2009-08-20 |
| 20090206490 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAE - A semiconductor device having redistribution interconnects in the WPP technology and improved reliability, wherein the redistribution interconnects have first patterns and second patterns which are electrically separated from each other within the plane of the semiconductor substrate, the first patterns electrically coupled to the multi-layer interconnects and the floating second patterns are coexistent within the plane of the semiconductor substrate, and the occupation ratio of the total of the first patterns and the second patterns within the plane of the semiconductor substrate, that is, the occupation ratio of the redistribution interconnects is 35 to 60%. | 2009-08-20 |
| 20090206491 | SEMICONDUCTOR DEVICE - A semiconductor device according to one embodiment includes: a semiconductor substrate provided with a semiconductor element; a connecting member formed above the semiconductor substrate configured to electrically connect upper and lower conductive members; a first insulating film formed in the same layer as the connecting member; a wiring formed on the connecting member, the wiring including a first region and a second region, the first region contacting with a portion of an upper surface of the connecting member, and the second region located on the first region and having a width greater than that of the first region; and a second insulating film formed on the first insulating film so as to contact with at least a portion of the first region of the wiring and with a bottom surface of the second region. | 2009-08-20 |
| 20090206492 | Semiconductor device - A semiconductor device includes a semiconductor chip, a first substrate, and a second substrate. The first substrate includes a plurality of wires and a plurality of first electrodes, each first electrode being connected with each wire. The second substrate includes the semiconductor chip that is mounted thereon, and a plurality of second electrodes with, each second electrode being connected with the each first electrode of the first substrate. The widths of the wires of the first substrate are different depending on the lengths of the wires. By changing the widths of the wires depending on their lengths, it is possible to reduce variation in stiffness of the electrodes and vicinities of electrodes, whereby variation in ultrasonic bonding strength can be reduced. | 2009-08-20 |
| 20090206493 | Flip Chip Interconnection Pad Layout - A flip chip interconnect pad layout has the die signal pads are arranged on the die surface near the perimeter of the die, and the die power and ground pads arranged on the die surface inboard from the signal pads; and has the signal pads on the corresponding package substrate arranged in a manner complementary to the die pad layout and the signal lines routed from the signal pads beneath the die edge away from the die footprint, and has the power and ground lines routed to vias beneath the die footprint. Also, a flip chip semiconductor package in which the flip chip interconnect pad layouts have the die signal pads situated in the marginal part of the die and the die power and ground pads arranged on the die surface inboard from the signal pads, and the corresponding package substrates have signal pads arranged in a manner complementary to the die pad layout and signal lines routed from the signal pads beneath the die edge away from the die footprint. | 2009-08-20 |
| 20090206494 | WIRING OVER SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHODS FOR MANUFACTURING THEREOF - A wiring over a substrate capable of reducing particles between wirings and a method for manufacturing the wiring is disclosed. A wiring over a substrate capable of preventing short-circuiting between wirings due to big difference in projection and depression between wirings and a method for manufacturing the wiring is also disclosed. Further, a wiring over a substrate capable of preventing cracks in the insulating layer due to stress at the edge of a wiring or particles and a method for manufacturing the wiring is also disclosed. According to the present invention, a method for manufacturing a wiring over a substrate is provided that comprises the steps of: forming a first conductive layer over an insulating surface; forming a first mask pattern over the first conductive layer; forming a second mask pattern by etching the first mask pattern under a first condition, simultaneously, forming a second conductive layer having a side having an angle of inclination cross-sectionally by etching the first conductive layer; and forming a third conductive layer and a third mask pattern by etching the second conductive layer and the second mask pattern under a second condition; wherein a selective ratio under the first condition of the first conductive layer to the first mask pattern is in a range of 0.25 to 4, and a selective ratio under the second condition of the second conductive layer to the second mask pattern is larger than that under the first condition. | 2009-08-20 |
| 20090206495 | Semiconductor Device and Method for Manufacturing Same - A semiconductor device wherein a force of peeling a chip from a substrate does not operate even the semiconductor device is exposed under a high temperature condition after bonding and a bonding state of the substrate and the chip can be maintained, and a method for manufacturing such semiconductor device are provided. Specifically, in the semiconductor manufacture, a recessed alignment mark is formed on a front plane of a high distortion point glass substrate as a target for alignment for bonding, and the recessed alignment mark is permitted to have a shape which extends to an external side of the semiconductor device. Thus, excellent bonding between the high distortion point glass substrate and the semiconductor device can be provided, and at the same time, since the recessed alignment mark is not sealed, the bonding state can be maintained even when the high distortion point glass substrate is exposed under the high temperature condition after bonding the semiconductor device. | 2009-08-20 |
| 20090206496 | WATER-COOLING FAN WITH HUMIDIFYING EFFECT - A water-cooling fan with humidifying effect includes a main body, a cloth curtain and a filter. The main body has a fan, an air outlet formed at its front, an air inlet formed at its rear, a plugging groove positioned respectively at two sides of the air inlet, a water tank, a pump and a sink. The circumference of the air inlet is attached with a Velcro band corresponding to a Velcro band fixed around the circumference of the cloth curtain. The water tank has an opening for the cloth curtain to extend into it, a water-exiting tube connected with the pump, and at least one heater fixed in its bottom. The sink has a plurality of water-dropping holes in its bottom and a water-entering tube for being connected with the pump. Such a fan can be used as a water-cooling fan or used to increase indoor humidity if necessary. | 2009-08-20 |
