43rd week of 2017 patent applcation highlights part 59 |
Patent application number | Title | Published |
20170309277 | Voice Enabled Screen Reader - In some embodiments, a system may process a user interface to identify textual or graphical items in the interface, and may prepare a plurality of audio files containing spoken representations of the items. As the user navigates through the interface, different ones of the audio files may be selected and played, to announce text associated with items selected by the user. A computing device may periodically determine whether a cache offering the interface to users stores audio files for all of the interface's textual items, and if the cache is missing any audio files for any of the textual items, the computing device may take steps to have a corresponding audio file created. | 2017-10-26 |
20170309278 | CODING DEVICE AND METHOD, DECODING DEVICE AND METHOD, AND PROGRAM - The present technology relates to a coding device and method, and a decoding device and method, and a program capable of reducing the amount of calculations for decoding. | 2017-10-26 |
20170309279 | Audio Encoder and Decoder - The present disclosure provides methods, devices and computer program products for encoding and decoding of a vector of parameters in an audio coding system. The disclosure further relates to a method and apparatus for reconstructing an audio object in an audio decoding system. According to the disclosure, a modulo differential approach for coding and encoding a vector of a non-periodic quantity may improve the coding efficiency and provide encoders and decoders with less memory requirements. Moreover, an efficient method for encoding and decoding a sparse matrix is provided. | 2017-10-26 |
20170309280 | METHODS FOR PARAMETRIC MULTI-CHANNEL ENCODING - The present document relates to audio coding systems. In particular, the present document relates to efficient methods and systems for parametric multi-channel audio coding. An audio encoding system configured to generate a bitstream indicative of a downmix signal and spatial metadata for generating a multi-channel upmix signal from the downmix signal is described. The system comprises a downmix processing unit configured to generate the downmix signal from a multi-channel input signal; wherein the downmix signal comprises m channels and wherein the multi-channel input signal comprises n channels; n, m being integers with m2017-10-26 | |
20170309281 | METHODS AND DEVICES FOR JOINT MULTICHANNEL CODING - Encoding and decoding devices for encoding the channels of an audio system having at least four channels are disclosed. The decoding device has a first stereo decoding component which subjects a first pair of input channels to a first stereo decoding, and a second stereo decoding component which subjects a second pair of input channels to a second stereo decoding. The results of the first and second stereo decoding components are crosswise coupled to a third and a fourth stereo decoding component which each performs stereo decoding on one channel resulting from the first stereo decoding component, and one channel resulting from the second stereo decoding component. | 2017-10-26 |
20170309282 | Comfort Noise Generation - A system for generating comfort noise for a stream of frames carrying an audio signal includes frame characterizing logic configured to generate a set of filter parameters characterising the frequency content of a frame; an analysis filter adapted using the filter parameters and configured to filter the frame so as to generate residual samples; an analysis controller configured to cause the residual samples to be stored in a store responsive to receiving an indication that the frame does not comprise speech; and a synthesis controller operable to select stored residual samples from the store and cause a synthesis filter, inverse to the analysis filter and adapted using filter parameters generated by the frame characterizing logic for one or more frames not comprising speech, to filter the selected residual samples so as to generate a frame of comfort noise. | 2017-10-26 |
20170309283 | AUDIO ENCODER, AUDIO DECODER, METHODS FOR ENCODING AND DECODING AN AUDIO SIGNAL, AND A COMPUTER PROGRAM - An encoder for providing an audio stream on the basis of a transform-domain representation of an input audio signal includes a quantization error calculator configured to determine a multi-band quantization error over a plurality of frequency bands of the input audio signal for which separate band gain information is available. The encoder also includes an audio stream provider for providing the audio stream such that the audio stream includes information describing an audio content of the frequency bands and information describing the multi-band quantization error. | 2017-10-26 |
20170309284 | ENCODER FOR ENCODING AN AUDIO SIGNAL, AUDIO TRANSMISSION SYSTEM AND METHOD FOR DETERMINING CORRECTION VALUES - An encoder for encoding an audio signal includes an analyzer for analyzing the audio signal and for determining analysis prediction coefficients from the audio signal. The encoder includes a converter for deriving converted prediction coefficients from the analysis prediction coefficients, a memory for storing a multitude of correction values and a calculator. The calculator includes a processor for processing the converted prediction coefficients to obtain spectral weighting factors. The calculator includes a combiner for combining the spectral weighting factors and the multitude of correction values to obtain corrected weighting factors. A quantizer of the calculator is configured for quantizing the converted prediction coefficients using the corrected weighting factors to obtain a quantized representation of the converted prediction coefficients. The encoder includes a bitstream former for forming an output signal based on the quantized representation of the converted prediction coefficients and based on the audio signal. | 2017-10-26 |
20170309285 | APPARATUS AND METHOD FOR SELECTING ONE OF A FIRST ENCODING ALGORITHM AND A SECOND ENCODING ALGORITHM USING HARMONICS REDUCTION - An apparatus for selecting one of a first encoding algorithm and a second encoding algorithm includes a filter configured to receive the audio signal, to reduce the amplitude of harmonics in the audio signal and to output a filtered version of the audio signal. First and second estimators are provided for estimating first and second quality measures in the form of SNRs of segmented SNRs associated with the first and second encoding algorithms without actually encoding and decoding the portion of the audio signal using the first and second encoding algorithms. A controller is provided for selecting the first encoding algorithm or the second encoding algorithm based on a comparison between the first quality measure and the second quality measure. | 2017-10-26 |
20170309286 | SYSTEM FOR MAINTAINING REVERSIBLE DYNAMIC RANGE CONTROL INFORMATION ASSOCIATED WITH PARAMETRIC AUDIO CODERS - On the basis of a bitstream (P), an n-channel audio signal (X) is reconstructed by deriving an m-channel core signal (Y) and multichannel coding parameters (α) from the bitstream, where 1≦m2017-10-26 | |
20170309287 | SIGNAL CODEC DEVICE AND METHOD IN COMMUNICATION SYSTEM - The present invention relates to a codec device and method for encoding/decoding voice and audio signals in a communication system, wherein: a fixed codebook excited signal is generated by using a pulse index for a voice signal; a first adaptive codebook excited signal is generated by using a pitch index for the voice signal; a fixed codebook signal is generated by multiplying the fixed codebook excited signal by a fixed codebook gain; a first adaptive codebook signal is generated by multiplying the first adaptive codebook excited signal by a first adaptive codebook gain; and a synthesized filter excited signal is generated by adding the fixed codebook signal and the first adaptive codebook signal. | 2017-10-26 |
20170309288 | DECODING METHOD AND DECODER FOR DIALOG ENHANCEMENT - There is provided a method for enhancing dialog in a decoder of an audio system. The method comprises receiving a plurality of downmix signals being a downmix of a larger plurality of channels; receiving parameters for dialog enhancement being defined with respect to a subset of the plurality of channels that is downmixed into a subset of the plurality of downmix signals; upmixing the subset of downmix signals parametrically in order to reconstruct the subset of the plurality of channels with respect to which the parameters for dialog enhancement are defined; applying dialog enhancement to the subset of the plurality of channels with respect to which the parameters for dialog enhancement are defined using the parameters for dialog enhancement to provide at least one dialog enhanced signal; and subjecting the at least one dialog enhanced signal to mixing to provide dialog enhanced versions of the subset of downmix signals. | 2017-10-26 |
20170309289 | METHODS, APPARATUSES AND COMPUTER PROGRAMS RELATING TO MODIFICATION OF A CHARACTERISTIC ASSOCIATED WITH A SEPARATED AUDIO SIGNAL - This specification describes a method comprising determining, based on a determined measure of success of a separation of an audio signal representing a sound source from a composite audio signal comprising components derived from at least two sound sources, a value of a separated signal modification parameter, the value of the separated signal modification parameter indicating a range of modification of a characteristic associated with the separated audio signal. | 2017-10-26 |
20170309290 | LISTENING TO THE FRONTEND - In some embodiments, apparatuses, and methods are provided herein pertaining to sound analysis in a shopping facility. In some embodiments, a system comprises one or more sound sensors distributed throughout at least a portion of a shopping facility and configured to receive at least sounds resulting from activity in the shopping facility and a control circuit, the control circuit configured to receive, from at least one of the one or more sound sensors, audio data, receive an indication of an employee, correlate the audio data and in the indication of the employee, and determine, based at least in part on the audio data and the indication of the employee, a performance metric for the employee. | 2017-10-26 |
20170309291 | METHOD AND APPARATUS FOR SEPARATING SPEECH DATA FROM BACKGROUND DATA IN AUDIO COMMUNICATION - A method and an apparatus for separating speech data from background data in an audio communication are suggested. The method comprises: applying a speech model to the audio communication for separating the speech data from the background data of the audio communication; and updating the speech model as a function of the speech data and the background data during the audio communication. | 2017-10-26 |
20170309292 | INTEGRATED SENSOR-ARRAY PROCESSOR - An integrated sensor-array processor and method includes sensor array time-domain input ports to receive sensor signals from time-domain sensors. A sensor transform engine (STE) creates sensor transform data from the sensor signals and applies sensor calibration adjustments. Transducer time-domain input ports receive time-domain transducer signals, and a transducer output transform engine (TTE) generates transducer output transform data from the transducer signals. A spatial filter engine (SFE) applies suppression coefficients to the sensor transform data, to suppress target signals received from noise locations and/or amplification locations. A blocking filter engine (BFE) applies subtraction coefficients to the sensor transform data, to subtract the target signals from the sensor transform data. A noise reduction filter engine (NRE) subtracts noise signals from the BFE output. An inverse transform engine (ITE) generates time-domain data from the NRE output. | 2017-10-26 |
20170309293 | METHOD AND APPARATUS FOR PROCESSING AUDIO SIGNAL INCLUDING NOISE - A method of processing an audio signal is provided. The method includes: acquiring an audio signal of a frequency domain for a plurality of frames; dividing a frequency band into a plurality of sections; acquiring energies of the plurality of sections; detecting an audio signal including noise based on an energy difference between the plurality of sections; and applying a suppression gain to the detected audio signal. | 2017-10-26 |
20170309294 | ELECTRONIC DEVICE AND REVERBERATION REMOVAL METHOD THEREFOR - Provided are an electronic device and a reverberation removal method therefor. The reverberation removal method for an electronic device comprises: a plurality of microphone units for receiving a user's voice; a reverberation removal unit removing a reverberation component of the user's voice received from the plurality of microphone units so as to acquire an original component of the user's voice; a reverberation information acquisition unit for acquiring information on the intensity of the reverberation component of the user's voice; and a post-processing unit for additionally removing a reverberation component from the original component acquired from the reverberation removal unit on the basis of the information on the intensity of the reverberation component. | 2017-10-26 |
20170309295 | Subband Block Based Harmonic Transposition - The present document relates to audio source coding systems which make use of a harmonic transposition method for high frequency reconstruction (HFR), as well as to digital effect processors, e.g. exciters, where generation of harmonic distortion add brightness to the processed signal, and to time stretchers where a signal duration is prolonged with maintained spectral content. A system and method configured to generate a time stretched and/or frequency transposed signal from an input signal is described. The system comprises an analysis filterbank configured to provide an analysis subband signal from the input signal; wherein the analysis subband signal comprises a plurality of complex valued analysis samples, each having a phase and a magnitude. Furthermore, the system comprises a subband processing unit configured to determine a synthesis subband signal from the analysis subband signal using a subband transposition factor Q and a subband stretch factor S. The subband processing unit performs a block based nonlinear processing wherein the magnitude of samples of the synthesis subband signal are determined from the magnitude of corresponding samples of the analysis subband signal and a predetermined sample of the analysis subband signal. In addition, the system comprises a synthesis filterbank configured to generate the time stretched and/or frequency transposed signal from the synthesis subband signal. | 2017-10-26 |
20170309296 | AUDIO DRIVEN ACCELERATED BINGE WATCH - Example embodiments provide systems and methods for accelerating digital content playback based on speech. A content acceleration system electronically accesses digital content. The system analyzes the digital content to detect at least one audio portion within the digital content, each of the at least one audio portion comprising speech. The system creates at least one digital content segment from the digital content based on the at least one audio portion, whereby a beginning of each digital content segment of the at least one digital content segment coincides with a beginning of a corresponding audio portion of the at least one audio portion. The system then accelerates playback of the digital content by fast forwarding through parts of the at least one digital content segment where speech is absent. | 2017-10-26 |
20170309297 | METHODS AND SYSTEMS FOR CLASSIFYING AUDIO SEGMENTS OF AN AUDIO SIGNAL - The disclosed embodiments illustrate a method for classifying one or more audio segments of an audio signal. The method includes determining one or more first features of a first audio segment of the one or more audio segments. The method further includes determining one or more second features based on the one or more first features. The method includes determining one or more third features of the first audio segment, wherein each of the one or more third features is determined based on a second feature of the one or more second features of the first audio segment and at least one second feature associated with a second audio segment. Additionally, the method includes classifying the first audio segment either in an interrogative category or a non-interrogative category based on one or more of the one or more second features and the one or more third features. | 2017-10-26 |
20170309298 | DIGITAL FINGERPRINT INDEXING - A machine accesses audio data that may be included in a media item, and the audio data includes multiple segments. The machine detects a silent segment among non-silent segments of the audio data. The machine generates sub-fingerprints of the non-silent segments by hashing the non-silent segments with a same fingerprinting algorithm, but the machine generates a sub-fingerprint of the silent segment based on a predetermined non-zero value that represents fingerprinted silence. With these sub-fingerprints generated, the machine generates a fingerprint of the audio data, of the media item, or of both, by storing the generated sub-fingerprints mapped to locations of their corresponding segments in the audio data. The machine then indexes the fingerprint by indexing the sub-fingerprints of the non-silent segments, without indexing the sub-fingerprint of the silent segment. | 2017-10-26 |
20170309299 | MICROWAVE ASSISTED MAGNETIC RECORDING HEAD WITH SPIN TORQUE OSCILLATOR CORNER ANGLE RELATIONSHIP, HEAD GIMBAL ASSEMBLY, AND MAGNETIC RECORDING DEVICE - A microwave assisted magnetic head includes a main magnetic pole; a trailing shield; and a spin torque oscillator provided between the main magnetic pole and the trailing shield. The spin torque oscillator has a first end surface configuring a part of an air bearing surface, a second end surface facing the main magnetic pole, and a third end surface facing the first end surface, the first angle θ | 2017-10-26 |
20170309300 | STRIPE HEIGHT LAPPING CONTROL STRUCTURES FOR A MULTIPLE SENSOR ARRAY - A method and system provide a storage device. A plurality of read sensor stacks for each reader of the storage device are provided. The read sensor stacks are distributed along a down track direction and offset in a cross-track direction. A plurality of electronic lapping guides (ELGs) are provided for the read sensor stacks. The read sensor stacks are lapped. Lapping is terminated based on signal(s) from the ELG(s). | 2017-10-26 |
20170309301 | MULTILAYER ELEMENT INCLUDING BASE MULTILAYER BODY, MAGNETIC SENSOR AND MICROWAVE ASSISTED MAGNETIC HEAD - A base multilayer body is made by laminating a seed layer and a buffer layer in respective order. The seed layer is an alloy layer containing tantalum (Ta) and at least one type of other metal, and having an amorphous structure or a microcrystal structure. The buffer layer is an alloy layer having a [001] plane orientation hexagonal close-packed structure and containing at least one type of a group VI metal and at least one type of a group IX metal in the periodic table. With this configuration, a magnetic layer providing a desired magnetic characteristic(s) can be laminated on the thinned base multilayer body. | 2017-10-26 |
20170309302 | CURRENT PERPENDICULAR-TO-PLANE SENSORS HAVING HARD SPACERS - An apparatus according to one embodiment includes a transducer structure having a lower shield and/or an upper shield. A current-perpendicular-to-plane sensor is positioned adjacent the shield(s). An electrical lead layer is positioned between the sensor and the upper or lower shield. The electrical lead layer is in electrical communication with the sensor. A spacer layer is positioned between the electrical lead layer and the upper or lower shield. A conductivity of the electrical lead layer is higher than a conductivity of the spacer layer. | 2017-10-26 |
20170309303 | SUSPENSION ASSEMBLY WITH LIFT TAB, DISK DRIVE WITH THE SAME, AND METHOD OF MANUFACTURING LIFT TAB OF SUSPENSION ASSEMBLY - According to one embodiment, a suspension assembly includes a support plate and a lift tab extending in a first direction. The lift tab has an arc-shaped cross section, and includes an arc-shaped outer circumferential surface, an arc-shaped inner circumferential surface, a first upper end surface located between one arc ends of the outer and inner circumferential surfaces, and a second upper end surface located between other arc ends of the outer and inner circumferential surfaces of the inner circumferential surface, and a first angle made between the outer circumferential surface and the first upper end surface is less than a second angle made between the inner circumferential surface and the first upper end surface. | 2017-10-26 |
20170309304 | HARDWARE BASED CROSSTALK REDUCTION FOR HARD DISK DRIVES - An actuator assembly for crosstalk reduction in hard disk drives (HDDs) is provided. The actuator assembly comprises a base plate; a pivot; a voice coil motor (VCM) with an upper yoke and a lower yoke; and a cut-out insert having a predetermined stiffness and predetermined magnetic properties, wherein the cut-out insert corresponds to a cut-out recess of the base plate, and wherein the lower yoke of the VCM and the pivot are coupled to the cut-out insert. | 2017-10-26 |
20170309305 | SKIVING BLOCK FOR MITIGATING PROTRUDING DEFECTS FROM MAGNETIC TAPE RECORDING MEDIA - An apparatus according to one embodiment includes a block having multiple skiving edges along a tape bearing surface thereof, and a guide mechanism configured to set a wrap angle of a tape approaching the skiving edge. A drive mechanism is configured to cause the tape to move over the block. The block has no transducer coupled directly thereto. A computer-implemented method according to one embodiment includes causing a magnetic recording tape to pass over a block having a skiving edge at a wrap angle of at least one degree for burnishing the tape, wherein the block has an average hardness of at least about 9 Mohs. | 2017-10-26 |
20170309306 | DEVICE FOR AND METHOD OF ENABLING THE PROCESSING OF A VIDEO STREAM - A method of enabling processing of a video stream is described. The method comprises establishing a slice width for frames of the video stream; receiving the video stream; dividing, for each frame of the video stream, the frame into vertical slices having the slice width; storing a frame of the video stream in a re-ordered slice based format. Computer-readable storage medium and a device for enabling processing of a video stream are also described | 2017-10-26 |
20170309307 | VIDEO RECORDING APPARATUS WITH PRE-EVENT CIRCULATION RECORDING FUNCTION - A video recording apparatus with a pre-event circulation recording function is provided. A limitation on memory capacity may be removed by recording a pre-event video directly on a nonvolatile storage medium, such as a hard disk drive (HDD), without using a buffer according to a circulation recording method during pre-event recording performed to record videos before and after an event occurs. | 2017-10-26 |
20170309308 | DISPLAY APPARATUS AND CONTROL METHOD THEREOF - A display apparatus including a display unit, adapted to playback a sequence of images, comprises: a detection configured to detect an attitude of the display apparatus or the display unit; a control unit configured to control the display unit to pause playback of the sequence of images, if the detected attitude of the display apparatus is not substantially aligned with the orientation of an image to be displayed. | 2017-10-26 |
20170309309 | SYSTEM, APPARATUS AND METHOD FOR FORMATTING A MANUSCRIPT AUTOMATICALLY - System, method and apparatuses of the present invention directed to a paradigm of manuscript generation and manipulation from a source textual document, involving a first format, into another document in a second format. A converter converts scenes, dialogue, milieus, movements, actions and other instructions input or stored in a first format into a second, different format, and vice versa. | 2017-10-26 |
20170309310 | METHOD AND DEVICE FOR COMPRESSED-DOMAIN VIDEO EDITING - A method and device for editing a media file comprising input video frames. The editing device comprises a frame analyzer to determine whether the input video frames have the frame characteristics suitable for compressed domain editing or spatial domain editing. For those frames suitable for compressed domain editing, the frame analyzer provides frame data to a compressed domain processor so that video frame data can be modified in the compressed domain. For those frames only suitable for spatial domain editing, the frame analyzer provides frame data to a decoder and then to a spatial domain processor for frame data modification. The modified data at different domains are combined and converted to file format by a file format composer. Moreover, a file format parser is used to separate audio data from video data so that audio data can also be modified, if so desired. | 2017-10-26 |
20170309311 | GENERATING VIDEOS OF MEDIA ITEMS ASSOCIATED WITH A USER - A method includes grouping media items associated with a user into segments based on a timestamp associated with each media item and a total number of media items. The method also includes selecting target media from the media items for each of the segments based on media attributes associated with the media item. The method also includes generating a video that includes the target media for each of the segments by generating a first animation that illustrates a first transition from a first item from the target media to a second item from the target media with movement of the first item from an onscreen location to an offscreen location, wherein the first item is adjacent to the second item in the first animation and determining whether the target media includes one or more additional items. The method also includes adding a song to the video. | 2017-10-26 |
20170309312 | METHODS AND DEVICES FOR DETECTING SHOCK EVENTS - An apparatus includes an actuator assembly, a dampening assembly coupled to the actuator assembly, and a vibration sensor assembly coupled to the dampening assembly and coupled to the actuator assembly by way of the dampening assembly. A method includes attaching a dampening assembly to an actuator assembly and attaching a vibration sensor assembly to the dampening assembly. The dampening assembly is positioned between the vibration sensor assembly and the actuator assembly. | 2017-10-26 |
20170309313 | SEMICONDUCTOR DEVICE - According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate. | 2017-10-26 |
20170309314 | APPARATUSES AND METHODS FOR PERFORMING CORNER TURN OPERATIONS USING SENSING CIRCUITRY - The present disclosure includes apparatuses and methods related to performing corner turn operations using sensing circuitry. An example apparatus comprises a first group of memory cells coupled to an access line and a plurality of sense lines and a second group of memory cells coupled to a plurality of access lines and one of the plurality of sense lines. The access line can be a same access line as one of the plurality of access lines. The example apparatus comprises a controller configured to cause a corner turn operation on an element stored in the first group of memory cells resulting in the element being stored in the second group of memory cells to be performed using sensing circuitry. | 2017-10-26 |
20170309315 | SIMULATING ACCESS LINES - Examples of the present disclosure provide apparatuses and methods for simulating access lines in a memory. An example method can include receiving a first bit-vector and a second bit-vector in a format associated with storing the first bit-vector in memory cells coupled to a first access line and a first number of sense lines and storing the second bit-vector in memory cells coupled to a second access line and the first number of sense lines. The method can include storing the first bit-vector in a number of memory cells coupled to the first access line and a second number of sense lines and storing the second bit-vector in a number of memory cells coupled to the first access line and a third number of sense lines, wherein a quantity of the first number of sense lines is less than a quantity of the second and third number of sense lines. | 2017-10-26 |
20170309316 | APPARATUSES AND METHODS FOR PERFORMING CORNER TURN OPERATIONS USING SENSING CIRCUITRY - The present disclosure includes apparatuses and methods related to performing corner turn operations using sensing circuitry. An example apparatus comprises a first group of memory cells coupled to an access line and a plurality of sense lines and a second group of memory cells coupled to a plurality of access lines and a sense line. The example apparatus comprises a controller configured to cause a corner turn operation using sensing circuitry on an element stored in the first group of memory cells resulting in the element being stored in the second group of memory cells. | 2017-10-26 |
20170309317 | RECEPTION CIRCUIT AND ELECTRONIC APPARATUS INCLUDING THE SAME - Provided is a reception circuit provided in a chip, the reception circuit including a controller that generates a reception control signal which is activated for a preset time on a basis of a first control signal individually provided to a plurality of chips, a buffer that receives a second control signal commonly provided to the plurality of chips, and a delay circuit that receives the second control signal from the buffer in response to the reception control signal and provides the second control signal to other elements in the chip. | 2017-10-26 |
20170309318 | APPARATUSES AND METHODS FOR MEMORY OPERATIONS HAVING VARIABLE LATENCIES - Apparatuses and methods for performing memory operations are described. In an example apparatus, a memory is configured to receive a memory instruction and perform a memory operation responsive to the memory instruction. The memory is further configured to provide an acknowledgement indicative of an end of the variable latency period wherein the acknowledgement includes information related to an acceptance of a memory instruction. Data associated with the memory instruction is exchanged with the memory following the acknowledgement. In an example method a read instruction and an address from which read data is to be read is received. A write operation is suspended responsive to the read instruction and an acknowledgement indicative of an end of the variable latency period is provided. Read data for the read instruction is provided and the write operation is continued to be suspended for a hold-off period following completion of the read operation. | 2017-10-26 |
20170309319 | APPARATUSES AND METHODS FOR DETECTING FREQUENCY RANGES CORRESPONDING TO SIGNAL DELAYS OF CONDUCTIVE VIAS - Apparatuses for monitoring a signal on a conductive via are described. An example apparatus includes: a controller, a first conductive via, a second conductive via and an evaluation circuit. The controller provides a clock signal as a first signal. The first conductive via provides a second signal responsive to the first signal. The second conductive via provides a third signal responsive to the second signal. Responsive to the third signal, the evaluation circuit provides an evaluation result signal. The evaluation result signal is indicative of a frequency of the clock signal, based on a delay of the third signal relative to the clock signal. The first conductive via, the second conductive via and the evaluation circuit may be included in an interface die. The evaluation circuit may detect whether a frequency of the first signal is below a first threshold frequency and may further provide the evaluation result signal. | 2017-10-26 |
20170309320 | METHODS AND APPARATUSES INCLUDING COMMAND DELAY ADJUSTMENT CIRCUIT - Apparatuses for controlling latencies on input signal paths in semiconductor devices are disclosed. An example apparatus includes: a clock input buffer that provides a reference clock signal and a system clock signal based on an external clock signal; a command decoder that latches command signals with the system clock signal and further provides a signal based on the command signals; and a command delay adjustment circuit including: a clock synchronizing circuit that receives the signal, latches the signal with the system clock signal and provides a clock-synchronized read signal responsive to a shift cycle parameter. | 2017-10-26 |
20170309321 | Peak Current Bypass Protection Control Device Applicable in MRAM - A peak current bypass protection control device applicable in MRAM is provided. In a memory unit array formed of a plurality of magnetic memory bit cells, each column of magnetic memory bit cells is connected in parallel with a bypass unit. When the magnetic memory bit cells of the memory unit array are being read/written, at the moment of switching on a switch, the bypass unit connected in parallel to the magnetic memory bit cells allows an instantaneous peak current to be guided out and prevents it from flowing through the magnetic memory bit cells. | 2017-10-26 |
20170309322 | Memory Arrays, Ferroelectric Transistors, and Methods of Reading and Writing Relative to Memory Cells of Memory Arrays - Some embodiments include a ferroelectric transistor. The transistor has gate dielectric material configured as a first container, with the first container having a first inner surface. Metal-containing material is configured as a second container nested within said first container. The second container has a second inner surface with an area less than the first inner surface. Ferroelectric material is configured as a third container nested within the second container. The third container has a third inner surface with an area less than the second inner surface. Gate material is within the third container. Some embodiments include memory arrays having ferroelectric transistors as memory cells. Some embodiments include methods of writing/reading relative to memory cells of memory arrays when the memory cells are metal-ferroelectric-metal-insulator-semiconductor (MFMIS) transistors. | 2017-10-26 |
20170309323 | METHODS AND APPARATUSES INCLUDING COMMAND DELAY ADJUSTMENT CIRCUIT - Apparatuses for controlling latencies on input signal paths in semiconductor devices are disclosed. An example apparatus includes: a clock input buffer that provides a reference clock signal and a system clock signal based on an external clock signal; a command decoder that latches command signals with the system clock signal and further provides a signal based on the command signals; and a command delay adjustment circuit including: a clock synchronizing circuit that receives the signal, latches the signal with the system clock signal and provides a clock-synchronized read signal responsive to a shift cycle parameter. | 2017-10-26 |
20170309324 | VOLATILE MEMORY DEVICE EMPLOYING A RESISTIVE MEMORY ELEMENT - A volatile resistive memory device includes a resistive memory element including a barrier material portion and a charge-modulated resistive memory material portion. The barrier material portion includes a material selected from germanium and a silicon-germanium alloy, and the charge-modulated resistive memory material portion includes a non-filamentary, electrically conductive metal oxide. The resistive memory device may be a volatile eDRAM device. In operation, reading a resistance state of the resistive memory element does not disturb the resistance state of the charge-modulated resistive memory material portion. | 2017-10-26 |
20170309325 | SEMICONDUCTOR DEVICE, CIRCUIT BOARD, AND ELECTRONIC DEVICE - A semiconductor device with low power consumption or a semiconductor device with a reduced area is provided. The semiconductor device includes a cell array including a first memory cell and a second memory cell; and a sense amplifier circuit including a first sense amplifier and a second sense amplifier. The cell array is over the sense amplifier circuit. The first sense amplifier is electrically connected to the first memory cell through a first wiring BL. The second sense amplifier is electrically connected to the second memory cell through a second wiring BL. The first sense amplifier and the second sense amplifier are electrically connected to a wiring GBL. The sense amplifier circuit is configured to select one of a potential of the first wiring BL and a potential of the second wiring BL and output the selected potential to the wiring GBL. | 2017-10-26 |
20170309326 | SEMICONDUCTOR DEVICE - A semiconductor device includes a SRAM circuit. The SRAM circuit includes: a memory array having a plurality of memory cells arranged in a matrix; a ground interconnection commonly connected to each of the memory cells; and a first potential control circuit for controlling a potential of the ground interconnection depending on an operation mode. The first potential control circuit includes a first NMOS transistor and a first PMOS transistor connected in parallel to each other between a around node providing a ground potential and the ground interconnection. | 2017-10-26 |
20170309327 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND SYSTEM - A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line. | 2017-10-26 |
20170309328 | LOCAL BIT LINE-SHARING MEMORY DEVICE AND METHOD OF DRIVING THE SAME - Disclosed is a local bit line-sharing memory device, including a plurality of memory cells that share a local bit line pair; a pre-charging unit that is connected to a write bit line pair and pre-charges the local bit line pair; and a data reading unit that reads data when bit line voltage pre-charged in a memory cell selected from the memory cells is discharged. | 2017-10-26 |
20170309329 | Non-Volatile Semiconductor Memory Device Adapted to Store a Multi-Valued Data in a Single Memory Cell - A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell. | 2017-10-26 |
20170309330 | RESISTIVE MEMORY DEVICE AND A MEMORY SYSTEM INCLUDING THE SAME - A memory device includes a memory cell array, a read circuit, and a control logic. The memory cell array includes a memory cell having a resistance level that varies depending on data stored therein. The memory cell is connected to a first signal line and a second signal line. The read circuit is configured to read the data. The control logic is configured to precharge a sensing node, connected to the first signal line through a first switching device, and a first node, connected to the second signal line through a second switching device, to different voltage levels during a first period, and develop a voltage of the sensing node based on the resistance level of the memory cell during a second period. | 2017-10-26 |
20170309331 | APPARATUSES AND METHODS OF READING MEMORY CELLS BASED ON RESPONSE TO A TEST PULSE - The disclosed technology generally relates to memory apparatuses and methods of operating the same, and more particularly to memory arrays and methods of reading memory cells in a memory array, such as a cross point memory array. In one aspect, the method comprises providing a memory array comprising a memory cell in one of a plurality of states. The method additionally comprises determining whether a threshold voltage (Vth) of the memory cell has a value within a predetermined read voltage window. A test pulse is applied to the memory cell if it is determined that the threshold voltage has a value within the predetermined read voltage window. The state of the memory cell may be determined based on a response of the memory cell to the test pulse, wherein the state corresponds to the one of the pluralities of states of the memory cell prior to receiving the test pulse. | 2017-10-26 |
20170309332 | PLANAR MEMORY CELL ARCHITECTURES IN RESISTIVE MEMORY DEVICES - To provide enhanced data storage devices and systems, various systems, architectures, apparatuses, and methods, are provided herein. In a first example, a resistive random access memory (ReRAM) array is provided. The ReRAM array includes a plurality of memory cells each comprising resistive memory material formed into a layer of a substrate, with resistance properties of the resistive memory material corresponding to data bits stored by the memory cells. The ReRAM array also includes a plurality of interconnect features each comprising conductive material between adjacent memory cells formed into the layer of the substrate, and gate portions coupled onto the memory cells and configured to individually alter the resistance properties of the resistive memory material of associated memory cells responsive to at least voltages applied to the gate portions. | 2017-10-26 |
20170309333 | OPERATIONAL SIGNALS GENERATED FROM CAPACITIVE STORED CHARGE - Methods, a memory device, and a system. are disclosed. One such method includes applying a select pulse to a snapback device of a memory cell. This causes the memory cell to enter a conductive state. Once in the conductive state, the memory cell can be set or reset by a pulse formed from parasitic capacitive discharge from various paths coupled to the memory cell. | 2017-10-26 |
20170309334 | METHODS FOR ENHANCED STATE RETENTION WITHIN A RESISTIVE CHANGE CELL - A method for improving the stability of a resistive change cell is disclosed. The stability of a resistive change memory cell-that is, the tendency of the resistive change memory cell to retain its programmed resistive state-may, in certain applications, be compromised if the cell is programmed into an unstable or metastable state. In such applications, a programming method using bursts of sub-pulses within a pulse train is used to drive the resistive change cell material into a stable state during the programming operation, reducing resistance drift over time within the cell. | 2017-10-26 |
20170309335 | NON-VOLATILE MEMORY DEVICE AND METHOD OF CONTROLLING NON-VOLATILE MEMORY DEVICE - A non-volatile memory device of the disclosure includes a memory cell, a writing circuit, and a current controller. The memory cell is disposed at an intersection of a first wiring and a second wiring, and includes a variable resistance element having a resistance state that is variable between a first resistance state and a second resistance state. The writing circuit varies the variable resistance element from the first resistance state to the second resistance state, and thereby performs writing of data on the memory cell. The current controller controls a current and thereby limits the current to a predetermined limit current value. The current is caused to flow through the first wiring or the second wiring by the writing circuit upon performing of the writing of the data. The current controller causes the predetermined limit current value to be a first limit current value in a period before a time at which the variable resistance element is varied to the second resistance state, and varies the predetermined limit current value from the first limit current value to a second limit current value after the time at which the variable resistance element is varied to the second resistance state. | 2017-10-26 |
20170309336 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device including a plurality of memory cells, each including a variable resistance element, and control circuitry that executes a first writing process of applying a first writing pulse to a memory cell to turn the memory cell state into a first resistance state and a second writing process of applying a second writing pulse of opposite polarity to the first writing pulse to turn the memory cell into a second resistance state, the memory cell from among the plurality of memory cells. The control circuitry, when the memory cell is placed in the second resistance state, after applying the first writing pulse to the memory cell, applies a reading pulse for a verify process of reading whether the variable resistance element is placed in the first resistance state or the second resistance state. | 2017-10-26 |
20170309337 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block. | 2017-10-26 |
20170309338 | INDEPENDENT MULTI-PLANE READ AND LOW LATENCY HYBRID READ - Read operations are performed in a multi-plane memory device. A state machine interfaces an external controller to each plane of memory cells to allow reading from selected word lines in the planes. In one approach, different types of read operations are performed in different planes, such as a multi-level cell read, e.g., a lower, middle or upper page read and a single-level cell (SLC) read. When the read operation in one plane uses fewer read voltages than another plane, the read data can be output early from the one plane while read operations continue on the other plane. The external controller can also command a cache release for one plane after outputting data from the caches of another plane. Read voltages can be set for each plane in a respective set of registers. | 2017-10-26 |
20170309339 | ARCHITECTURE FOR CMOS UNDER ARRAY - Systems and methods for reducing the area and improving the performance of a non-volatile memory array are described. The non-volatile memory array may comprise a 3D NAND memory array that includes vertical NAND strings that are arranged orthogonal to a substrate. A vertical NAND string may include floating gate memory cell transistors or charge trap memory cell transistors. Sensing circuitry for sensing the programmed data states of memory cell transistors within the vertical NAND strings may be positioned underneath the 3D NAND memory array and connections from bit lines positioned above the 3D NAND memory array may be made using vertical connections extending though the 3D NAND memory array or through memory breaks within the 3D NAND memory array. | 2017-10-26 |
20170309341 | METHODS OF OPERATING A MEMORY DEVICE COMPARING INPUT DATA TO DATA STORED IN MEMORY CELLS COUPLED TO A DATA LINE - Methods of operating a memory device include comparing input data to data stored in memory cells coupled to a data line, comparing a representation of a level of current in the data line to a reference, and determining that the input data potentially matches the data stored in the memory cells when the representation of the level of current in the data line is less than the reference. Methods of operating a memory device further include comparing input data to first data and to second data stored in memory cells coupled to a first data line or to a second data line, respectively, comparing representations of the levels of current in the first data line and in the second data line to a first reference and to a different second reference, and deeming one to be a closer match to the input data in response to results of the comparisons. | 2017-10-26 |
20170309343 | DATA STORAGE DEVICE AND OPERATING METHOD THEREOF - A data storage device includes a nonvolatile memory device and a controller configured to control an operation of the nonvolatile memory device. The controller includes an RAM in which a category table that categories with respect to LBAs are defined and a read voltage table that read voltages with respect to the categories are set are stored and a controller configured to, when a read request and an LBA to be read are received from a host apparatus, determine a category corresponding to the LBA with reference to the category table and perform a read operation on a read-requested memory cell of the nonvolatile memory device by applying a read voltage corresponding to the determined category to the memory cell with reference to the read voltage table. | 2017-10-26 |
20170309344 | MULTI-DIE PROGRAMMING WITH DIE-JUMPING INDUCED PERIODIC DELAYS - Systems and methods for improving the reliability of data stored in memory cells are described. To mitigate the effects of trapped electrons after one or more programming pulses have been applied to memory cells, a delay between the one or more programming pulses and subsequent program verify pulses may be set based on a chip temperature, the number of the one or more programming pulses that were applied to the memory cells, and/or the programming voltage that was applied to the memory cells during the one or more programming pulses. To mitigate the effects of residual electrons after one or more program verify pulses have been applied to memory cells, a delay between the one or more program verify pulses and subsequent programming pulses may be set based on a chip temperature and/or the programming voltage to be applied to the memory cells during the subsequent programming pulses. | 2017-10-26 |
20170309345 | SHIFT REGISTER, SEMICONDUCTOR DEVICE, DISPLAY DEVICE, AND ELECTRONIC DEVICE - The invention provides a semiconductor device and a shift register, in which low noise is caused in a non-selection period and a transistor is not always on. First to fourth transistors are provided. One of a source and a drain of the first transistor is connected to a first wire, the other of the source and the drain thereof is connected to a gate electrode of the second transistor, and a gate electrode thereof is connected to a fifth wire. One of a source and a drain of the second transistor is connected to a third wire and the other of the source and the drain thereof is connected to a sixth wire. One of a source and a drain of the third transistor is connected to a second wire, the other of the source and the drain thereof is connected to the gate electrode of the second transistor, and a gate electrode thereof is connected to a fourth wire. One of a source and a drain of the fourth transistor is connected to the second wire, the other of the source and the drain thereof is connected to the sixth wire, and a gate electrode thereof is connected to the fourth wire. | 2017-10-26 |
20170309346 | CALIBRATION APPARATUS AND METHOD FOR SAMPLER WITH ADJUSTABLE HIGH FREQUENCY GAIN - Methods and systems are described for receiving a sampling signal, pre-charging a pair of output nodes prior to a sampling interval, initiating the sampling interval by enabling a current source according to a first transition of the received sampling signal, generating a differential output voltage at the pair of output nodes by discharging the pair of output nodes according to a differential input signal, the pair of output nodes discharged according to current drawn by the current source during the sampling interval, terminating the sampling interval by disabling the current source in response to a second transition of the received sampling signal, and inhibiting a recharge of the pair of output nodes for a hold time after termination of the sampling interval and prior to initiation of a subsequent sampling interval. | 2017-10-26 |
20170309347 | STATE MACHINE CONTROLLED MOS LINEAR RESISTOR - A sample-and-hold circuit includes a sampling capacitor, a first transistor, a first switch between a gate electrode and a source electrode of the first transistor, a current source connected to the source electrode of the first transistor, and a resistive element and a second switch connected in parallel between a drain electrode of the first transistor and a predetermined voltage. The resistive element may include a second transistor biased to operate in a linear region according to a gate control signal at a gate electrode of the second transistor, or may include multiple transistor banks connected in parallel, each including a second transistor biased to operate in a linear region according to a gate control signal at a gate electrode of the second transistor. The gate control signal may originate from a circuit including a state machine. | 2017-10-26 |
20170309348 | CONTINUOUS WRITE AND READ OPERATIONS FOR MEMORIES WITH LATENCIES - A method and apparatus for continuous write and read operations during memory testing. The method comprises: controlling a signal generator; triggering a write address and a data field operation each memory cycle; triggering a write signal to write to a memory each memory clock cycle; and reading a read address and a read data operation to the memory. An additional embodiment provides an apparatus for advanced memory latency testing. The apparatus includes a data generator trigger in communication with a signal generator and an address generator trigger also in communication with the signal generator. | 2017-10-26 |
20170309349 | FAILURE ANALYSIS AND REPAIR REGISTER SHARING FOR MEMORY BIST - A built-in self-test (BIST) system comprising repair logic structured to share state logic of failed memories across local registers located in a shared registry which services multiple memories, wherein each of the local registers is associated with a different memory. | 2017-10-26 |
20170309350 | Data Storage Device and Data Maintenance Method Thereof - An exemplary embodiment provides a data storage device including a flash memory and a controller. The flash memory includes a plurality of chips, each of the chips includes a plurality of pages, the pages are arranged to assemble into a super block, the pages of the super block are numbered 0˜X from top to bottom of the super block, the pages with number 0˜Y−1 constitute a data area, and the pages with numbers Y˜X constitute a RAID parity area. The controller corrects data of the data area according to data of the RAID parity area when the data in the data area cannot be successfully read. | 2017-10-26 |
20170309351 | METHOD AND APPARATUS FOR PERIODIC ION COLLISIONS - Systems and methods are disclosed herein relating to fusion reactors for fusing particles via multiple periodic collisions. A fusion reactor may include a first evacuated region, such as a chamber, with a plurality of charged particles therein. A uniform magnetic field may be applied to the region to radially confine moving charged particles within the region by inducing circular trajectories. Upper and lower electrodes may be positioned on ends of the region to axially confine charged particles within the region. An energizing beam may be pulsed at a cyclotron frequency corresponding to the mass and charge of the particles to cause oscillating periodic collisions of the particles along the beam path as the particles travel in the circular trajectories with increased velocity after each pulse of the energizing beam. | 2017-10-26 |
20170309352 | FUEL ASSEMBLY FOR BOILING WATER REACTOR - A fuel assembly for a boiling water reactor, having fuel rods, a tie plate, a handle device, and at least two water rods attached to the tie plate and to the handle device. A plurality of spacers, define first passages for some of the fuel rods, and second passages for the water rods. Each water rod comprises a tube part attached to the tie plate, and a solid part attached to the handle device. The tube part permits a flow of coolant. The spacers include primary spacers and a secondary spacer. The primary spacers are attached to the tube parts. The tie plate, the water rods, the primary spacers and the handle device form a support structure carrying the weight of the fuel rods. The secondary spacer is positioned at the solid part of the respective water rod. | 2017-10-26 |
20170309353 | Method and Control System for Gas Injection into Coolant and Nuclear Reactor Plant - The patent discloses method and control system for gas injection into the coolant of a nuclear reactor plant. The method includes the following steps: gas to be injected into the coolant is supplied from the gas system to the above-coolant space; gas is injected into the gas system from the above-coolant space. Technical result: prevention of reuse of contaminated gas. | 2017-10-26 |
20170309354 | HEAT EXCHANGER AND NUCLEAR POWER PLANT COMPRISING SAME - The present invention relates to a plate heat exchanger and provides a heat exchanger and a nuclear power plant comprising same, the heat exchanger comprising: a plate unit having multiple plates overlapping one another; a flow path unit, which forms flow paths having fluids flowing therein by processing at least parts of the respective plates; and a detection flow path formed between the multiple plates so as to allow the fluids leaking from the flow paths to flow thereinto and formed so as to detect the leakage of the fluids from the flow paths. | 2017-10-26 |
20170309355 | RADIATION SHIELDING SYSTEM - A radiation shielding system for an x-ray digital detector array includes a first radiation shield having a plurality of shielding pads and a plurality of interstices between the plurality of shielding pads, the plurality of shielding pads having a greater thickness than the thickness of the plurality of interstices. The plurality of shielding pads is configured to be positioned over active components of the x-ray digital detector array and the interstices are configured to be positioned over passive components of the x-ray digital detector array. | 2017-10-26 |
20170309356 | RADIATION PROTECTION EQUIPMENT AND RADIATION PROTECTION SYSTEM PROVIDED WITH RADIATION PROTECTION EQUIPMENT - An amount of radiation exposure of a medical staff is significantly reduced, and a large working area is ensured during an operation. A size of each component of a radiation protection equipment is reduced so as to decrease a weight thereof. The radiation protection equipment is provided, which can be installed within a short time period before an operation and easily put away after the operation. The radiation protection equipment, includes: a first protection sheet arranged on a periphery of a radiation source device and configured to shield radiation; a second protection sheet formed separately from the first protection sheet, arranged on a side of an operation table, and configured to shield radiation; and a third protection sheet formed separately from the first and second protection sheets, arranged on a periphery of a surgical field so as to expose the surgical field, and configured to shield the radiation. | 2017-10-26 |
20170309357 | SHIELDING DEVICE AND METHOD - Some embodiments of a shielding device can include a base and a shield coupled to the base. The shielding device can be used to provide protection for a healthcare worker (e.g., physician, nurse, technician) during a medical procedure. | 2017-10-26 |
20170309358 | SOLID-STATE NUCLEAR ENERGY CONVERSION SYSTEM - A solid-state nuclear energy conversion system includes a crystalline insulator bombarded with radiation to create electron-hole pairs. A voltage source provides a potential bias across the crystalline insulator, causing electrons and holes to collect at opposing ends. A diode is incorporated in a circuit including the crystalline insulator, voltage source, and a load, inhibiting current flow from the voltage source to the load. Thus, a radiation-driven current flows to the load. | 2017-10-26 |
20170309360 | SINGLE CELL APPARATUS AND METHOD FOR SINGLE ION ADDRESSING - A single cell apparatus and method for single ion addressing are described herein. One apparatus includes a single cell configured to set a frequency, intensity, and a polarization of a laser, shutter the laser, align the shuttered laser to an ion in an ion trap such that the ion fluoresces light and/or performs a quantum operation, and detect the light fluoresced from the ion. | 2017-10-26 |
20170309361 | DYNAMIC BEAM SHAPER - The present invention presents a beam shaper for radiation imaging comprising a hollow beam shaper body filled with radiation attenuating gas. Radiation attenuation can be changed by adding or removing pressure to the gas or the housing containing the gas, making it suitable for use as a dynamic beam shaper in 3D radiation imaging. | 2017-10-26 |
20170309362 | MULTI-LAYERED GRAPHENE MATERIAL HAVING A PLURALITY OF YOLK/SHELL STRUCTURES - Multi-layered graphene materials and methods of making and use are described herein. A multi-layered graphene material can include a plurality of graphene layers having a plurality of intercalated nano- or microstructures that form a plurality of yolk/shell type structures. Each yolk/shell type structure can include at least two graphene layers that form a shell-like structure that encompasses a void space having at least one of the plurality of nano- or microstructures. The void space has a volume sufficient to allow for volume expansion of the at least one of the plurality of nano- or microstructures without deforming the shell-like structure. | 2017-10-26 |
20170309363 | ELECTROCONDUCTIVE FILM AND METHOD FOR MANUFACTURING ELECTROCONDUCTIVE PATTERN - A method for manufacturing an electroconductive pattern | 2017-10-26 |
20170309364 | TRANSPARENT CONDUCTOR, METHOD FOR PRODUCING TRANSPARENT CONDUCTOR, AND TOUCH PANEL - The present invention provides a transparent conductor that is excellent in conductivity, transparency, and low-reflection property and does not cause defects such as a moire pattern; and a touch panel including the transparent conductor. The transparent conductor of the present invention includes an anti-reflection film provided on a surface with projections formed at a pitch equal to or shorter than the wavelength of visible light; and metal fine particles each having a particle size equal to or smaller than the pitch of the projections and being placed in bottom portions of gaps between the projections, the metal fine particles placed in the gaps between the projections constituting mesh conductive portions. The touch panel of the present invention includes the above transparent conductor. | 2017-10-26 |
20170309366 | Electrical Device Comprising a Cross-linked Layer - The present invention relates to an electrical device ( | 2017-10-26 |
20170309367 | Radiation Crosslinked Fluoropolymer Compositions Containing Low Level of Extractable Fluorides - A composition for manufacturing a crosslinked ethylene tetrafluoroethylene (ETFE) copolymer with enhanced abrasion resistance and heat resistance is provided, the composition including ETFE, about 0.1-10% w/w of a metal oxide that effectively scavenges high levels of fluoride ions; and a crosslinking agent. Methods of using and making the composition are also provided. | 2017-10-26 |
20170309368 | TRANSPARENT CONDUCTIVE FILM AND ELECTRONIC DEVICE INCLUDING THE SAME - A transparent conductive film includes a metal oxide, a metal, and an epoxy, wherein a refractive index of the metal may be lower than that of the epoxy. | 2017-10-26 |
20170309369 | HIGHLY BENDABLE INSULATED ELECTRIC WIRE AND WIRE HARNESS - A highly bendable insulated electric wire includes a conductor part that has a plurality of non-compressed strands made of a copper alloy, each of the non-compressed strands having a cross-sectional area of 0.13 sq. mm, and a covering part that is provided on the conductor part, wherein the conductor part has an elongation of 7% or more and a tensile strength of 500 MPa or more, and the covering part is made of 100 degree Celsius heat-resistant polyvinyl chloride and has an elongation of 100% or more at a temperature of −40 degree Celsius. | 2017-10-26 |
20170309370 | CORE ELECTRIC WIRE FOR MULTI-CORE CABLE AND MULTI-CORE CABLE - Provided are a core electric wire for a multi-core cable superior in flex resistance at low temperature, and a multi-core cable employing the same. The core electric wire for a multi-core cable according to an aspect of the present invention comprises a conductor obtained by twisting element wires, and an insulating layer covering the conductor, a principal component of the insulating layer being a copolymer of ethylene and an α-olefin having a carbonyl group; the α-olefin content in the copolymer being 14% to 46% by mass; and a mathematical product C*E being 0.01 to 0.9, wherein C is a linear expansion coefficient of the insulating layer at from 25° C. to −35° C., and E is a modulus of elasticity thereof at −35° C. Average area of the conductor in the transverse cross section is 1.0 to 3.0 mm | 2017-10-26 |
20170309371 | MULTIFUNCTIONAL CABLE - A multifunctional cable is particularly suitable for the automotive industry. The multifunctional cable has a plurality of functional elements. A core in the form of a sheathed line contains at least one inner functional element. At least one outer functional element is wound around the sheathed line core. | 2017-10-26 |
20170309372 | RINGED TUBULAR SHEATH HAVING A DETACHABLE LONGITUDINAL STRIP - The invention relates to a ringed tubular sheath which comprises a longitudinal strip which can be easily detached by a user, in particular manually. More specifically, the invention relates to a ringed tubular sheath comprising a sheath body ( | 2017-10-26 |
20170309373 | CORE ELECTRIC WIRE FOR MULTI-CORE CABLE AND MULTI-CORE CABLE - Provided are a core electric wire for multi-core cable that is superior in flex resistance at low temperature, and a multi-core cable employing the same. A core electric wire for multi-core cable according to an aspect of the present invention comprises a conductor obtained by twisting element wires, and an insulating layer that covers an outer periphery of the conductor, in which, in a transverse cross section of the conductor, a percentage of an area occupied by void regions among the element wires is from 5% to 20%. An average area of the conductor in the transverse cross section is preferably from 1.0 mm | 2017-10-26 |
20170309374 | SUPERCONDUCTING CABLE - A superconducting cable includes a core part, in which the core part includes a former including a plurality of copper wires, a superconducting conductor layer including a plurality of superconducting wires connected in parallel to each other, an insulating layer, and a superconducting shield layer including a plurality of superconducting wires are sequentially arranged. A conducting layer formed of a metal having a current-carrying property at room temperature is provided on opposite surfaces of each of the superconducting wires of the superconducting conductor layer to reinforce mechanical rigidity of each of superconducting wires of the superconducting conductor layer, and the former has a cross-sectional area which is smaller than that of a former of a superconducting cable in which the conducting layer is not added to superconducting wires and which is designed on an assumption that all fault current flows to the former. | 2017-10-26 |
20170309375 | FABRICATION OF REINFORCED SUPERCONDUCTING WIRES - In various embodiments, superconducting wires feature assemblies of clad composite filaments and/or stabilized composite filaments embedded within a wire matrix. The wires may include one or more stabilizing elements for improved mechanical properties. | 2017-10-26 |
20170309376 | MULTIPLE STRESS CONTROL DEVICE FOR CABLE ACCESSORIES AND METHODS AND SYSTEMS INCLUDING SAME - Provided are devices, methods and systems. A cover system may include a unitary cold shrinkable, tubular, elastomeric cover sleeve defining a cover sleeve through passage that is configured to receive the electrical cable. The cover sleeve may include a first type of stress control element and a second type of stress control element that is different from the first type of stress control element. A holdout maintains the cover sleeve in an expanded state in which the cover sleeve is elastically expanded and when removed, permits the cover sleeve to radially contract to a contracted state about the electrical cable. The first type of stress control element includes a geometric stress cone that includes an electrically conductive and/or semiconductive portion that is configured to conductively engage a semiconductor layer of the electrical cable. The second type of stress control element includes a high-K stress relief element. | 2017-10-26 |
20170309377 | APPARATUS FOR PROVIDING AN ARC DIVERTER FOR COVERED OVERHEAD CONDUCTORS AND RELATED ASSEMBLIES AND METHODS - Described herein is a protective cover assembly for an electrical cable mounted on an insulator. The assembly includes an insulator cover including a cover body covering the electrical cable and the insulator and an electrically conductive arc diverter. The arc diverter is elongated in an axial direction that is parallel to a center axis of the electrical cable and is attached to an outer surface of the electrical cable at a portion of the electrical cable that is covered by the insulator cover such that a portion of the arc diverter is positioned below and covered by the insulator cover and another portion of the arc diverter extends past a terminal end of the insulator cover with an end of the arc diverter being spaced apart from the terminal end of the insulator cover in the axial direction. | 2017-10-26 |
20170309378 | Chip Resistor and Method for Producing Same - The invention is to provide a chip resistor suitable for lowering an initial resistance value. A chip resistor | 2017-10-26 |
20170309379 | PPTC OVER-CURRENT PROTECTION DEVICE - A PPTC over-current protection device includes: a first PPTC component that has a first metal foil layer and a first PTC element including a first polymer matrix, the first metal foil layer being bonded to the first polymer matrix; and a second PPTC component that has a second metal foil layer and a second PTC element including a second polymer matrix. The second metal foil layer is bonded to the second polymer matrix. The first and second PPTC components are stacked one above the other and are bonded to each other to form a stack with the first and second polymer matrices being bonded to each other by interfusion-bonding. | 2017-10-26 |
20170309380 | Method for Forming a Bed of Stabilized Magneto-Caloric Material - A method for forming a stabilized bed of magneto-caloric material is provided. The method includes aligning magneto-caloric particles within the casing while a magnetic field is applied to the magneto-caloric particles and then fixing positions of the magneto-caloric particles within the casing. A related stabilized bed of magneto-caloric material is also provided. | 2017-10-26 |