43rd week of 2021 patent applcation highlights part 60 |
Patent application number | Title | Published |
20210335731 | ACTIVE ATTACK PREVENTION FOR SECURE INTEGRATED CIRCUITS USING LATCHUP SENSITIVE DIODE CIRCUIT - The present disclosure relates to an active x-ray attack prevention structure for secure integrated circuits. In particular, the present disclosure relates to a structure including a functional circuit, and at least one latchup sensitive diode circuit configured to induce a latchup condition in the functional circuit, placed in proximity of the functional circuit. | 2021-10-28 |
20210335732 | ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF - An array substrate and a manufacturing method thereof are provided. A plurality of groups of bonding terminals are formed on a substrate, a first electrostatic protection wire is formed on a marginal region of the substrate, and a second electrostatic protection wire is formed to connect the bonding terminals and the first electrostatic protection wire. | 2021-10-28 |
20210335733 | ELECTRONIC DEVICE MODULE AND METHOD OF MANUFACTURING ELECTRONIC DEVICE MODULE - An electronic device module includes: a substrate; at least one electronic device mounted on a first surface of the substrate; a shielding wall mounted on the first surface of the substrate; a sealing portion disposed on the first surface of the substrate such that the at least one electronic device and the shielding wall are embedded in the sealing portion; and a shielding layer disposed on one surface of the sealing portion. At least a portion of the sealing portion is disposed externally of the shielding wall. The shielding wall and the shielding layer are formed of different materials. | 2021-10-28 |
20210335734 | SEMICONDUCTOR DEVICE - A semiconductor device may include a substrate, a first semiconductor chip buried in the substrate, a first antenna pattern, a second antenna pattern, and outer terminals. A bottom surface of the substrate may include first and second regions spaced apart from each other. The first semiconductor chip may have a first active surface that is directed to the top surface of a core portion of the substrate. The first antenna pattern may be provided on the top surface of the substrate and electrically connected to the first semiconductor chip. The outer terminals may be provided on the first region of the bottom surface of the substrate, and the second antenna pattern may be provided on the second region of the bottom surface of the substrate. | 2021-10-28 |
20210335735 | INTEGRATED CIRCUITS - One of integrated circuits includes a substrate, a through via, a conductive pad and at least one via. The through via is disposed in the substrate. The conductive pad is disposed over and electrically connected to the through via, and the conductive pad includes at least one dielectric pattern therein. The via is disposed between and electrically connected to the through via and the conductive pad. | 2021-10-28 |
20210335736 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a redistribution structure including an insulating layer having an upper surface and a lower surface, a redistribution pad and a redistribution pattern on the lower surface of the insulating layer and electrically connected to each other, and a passivation layer on the lower surface of the insulating layer and having an opening exposing at least a portion of the redistribution pad; a semiconductor chip on the redistribution structure and including a connection pad electrically connected to the redistribution pad; an encapsulant on the redistribution structure and encapsulating the semiconductor chip; and a connection bump and a dummy bump on the passivation layer, wherein the redistribution pattern has a width narrower than a width of the redistribution pad, the connection bump vertically overlaps the redistribution pad, and the dummy bump vertically overlaps the redistribution pattern. | 2021-10-28 |
20210335737 | MULTI-METAL CONTACT STRUCTURE - A first conductive material having a first hardness is disposed within a recess or opening of a microelectronic component, in a first preselected pattern, and forms a first portion of an interconnect structure. A second conductive material having a second hardness different from the first hardness is disposed within the recess or opening in a second preselected pattern and forms a second portion of the interconnect structure. | 2021-10-28 |
20210335738 | CAPACITOR INTERPOSER LAYER (CIL) IN A DIE-TO-WAFER THREE-DIMENSIONAL (3D) INTEGRATED CIRCUIT (IC) (3DIC) - A capacitor interposer layer (CIL) in a die-to-wafer three dimensional integrated circuit (3DIC) and methods of forming the same are disclosed. A CIL is formed in a wafer under a powder distribution network (PDN) die area of a chip. Electrical connections between the wafer and the chip are formed using a copper-to-copper bond. This placement allows the capacitor to be close to the PDN die area within the chip to reduce equivalent series resistance (ESR) and equivalent series inductance (ESL), while permitting a relatively low profile device with reduced PDN voltage droop. | 2021-10-28 |
20210335739 | SEMICONDUCTOR PACKAGE AND METHODS OF MANUFACTURING A SEMICONDUCTOR PACKAGE - In an embodiment, a semiconductor package includes a first transistor device having first and second opposing surfaces, a first power electrode and a control electrode arranged on the first surface and a second power electrode arranged on the second surface. A first metallization structure arranged on the first surface includes a plurality of outer contact pads which includes a protective layer of solder, Ag or Sn. A second metallization structure is arranged on the second surface. A conductive connection extending from the first surface to the second surface electrically connects the second power electrode to an outer contact pad of the first metallization structure. A first epoxy layer arranged on side faces and on the first surface of the transistor device includes openings which define a lateral size of the plurality of outer contact pads and a package footprint. | 2021-10-28 |
20210335740 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes a pad formed on a surface of a substrate, a bonding wire for connecting the pad to an external circuit, and a resin layer covering at least a connection portion between the pad and the bonding wire and exposing at least a part of the substrate outside the pad. | 2021-10-28 |
20210335741 | SYSTEMS FOR THERMALLY TREATING CONDUCTIVE ELEMENTS ON SEMICONDUCTOR AND WAFER STRUCTURES - Methods of reflowing electrically conductive elements on a wafer may involve directing a laser beam toward a region of a surface of a wafer supported on a film of a film frame to reflow at least one electrically conductive element on the surface of the wafer. In some embodiments, the wafer may be detached from a carrier substrate and be secured to the film frame before laser reflow. Apparatus for performing the methods, and methods of repairing previously reflowed conductive elements on a wafer are also disclosed. | 2021-10-28 |
20210335742 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate and a metal holder. The substrate includes at least one bonding pad disposed adjacent to its surface and the metal holder is disposed adjacent to the bonding pad. | 2021-10-28 |
20210335743 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - A semiconductor device includes a semiconductor substrate and a connection terminal, including a base pillar, on the semiconductor substrate. An insulation layer is formed on the semiconductor substrate, the insulation layer including an opening in the insulation layer through which the base pillar extends, wherein a side wall of the insulation layer defining the opening includes a horizontal step at a level that is lower than an uppermost portion of the base pillar. | 2021-10-28 |
20210335744 | STACKABLE FULLY MOLDED SEMICONDUCTOR STRUCTURE WITH VERTICAL INTERCONNECTS - A method of making a semiconductor device may include providing a carrier and forming a first photoresist over the carrier with first openings through the first photoresist. A non-planar conductive seed layer may be formed over the first photoresist and conformally extend into the first openings through the first photoresist. A second photoresist may be formed over the first photoresist and over the non-planar conductive seed layer. The second photoresist layer may be patterned to form second openings through the second photoresist that extend to the non-planar conductive seed layer. Conductive posts may be plated over the non-planar conductive seed layer and within the second openings. The second photoresist may be removed while leaving in place the first photoresist. A semiconductor die may be coupled to the carrier. The semiconductor die, the conductive posts, and the first photoresist may be encapsulated with mold compound. | 2021-10-28 |
20210335745 | SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME - The present invention relates to a semiconductor structure and method of forming the same. The semiconductor structure includes a first substrate, a first adhesive/bonding stack on the surface of first substrate, wherein the first adhesive/bonding stack includes at least one first adhesive layer and at least one first bonding layer. The material of first bonding layer includes dielectrics such as silicon, nitrogen and carbon, the material of first adhesive layer includes dielectrics such as silicon and nitrogen, and the first adhesive/bonding stack of semiconductor structure is provided with higher bonding force in bonding process. | 2021-10-28 |
20210335746 | VACUUM DEPOSITION SYSTEM AND METHOD THEREOF - A system and method are provided for depositing a substance onto a substrate, the system comprising: a chamber adapted to operate under high vacuum; an apparatus for receiving and cleaning the substrate to produce a clean substrate and for delivering the clean substrate to a coating position in the chamber under high vacuum; a carrier assembly for receiving the clean substrate from the apparatus and for retaining the substrate at the coating position; an evaporator adapted to hold a supply of the substance in the chamber and to evaporate and produce a discharge of the substance; and a collimator disposed within the chamber between the supply of the substance and the carrier assembly, the collimator being configured to define an aperture proximal to the substrate and to capture the discharge but for that which is directed through the aperture. | 2021-10-28 |
20210335747 | APPARATUS FOR MANUFACTURING ELECTRONIC DEVICE USING DEVICE CHIP - An apparatus includes a first substrate including a first adhesive layer, a second substrate including a second adhesive layer, a first drum that is rotatable, and a third adhesive layer located on the first drum. The first drum moves to a first location to separate device chips from the first adhesive layer of the first substrate and adheres the device chips to the third adhesive layer by rotating the first drum, and moves to a second location to separate the device chips from the third adhesive layer by rotating the first drum. The adhesive force of the first adhesive layer is less than the adhesive force of the third adhesive layer, and the adhesive force of the third adhesive layer is less than the adhesive force of the second adhesive layer. | 2021-10-28 |
20210335748 | FLIP-CHIP BONDING APPARATUS USING VCSEL DEVICE - Provided is a flip-chip bonding apparatus using VCSEL device, and more particularly, to a flip-chip bonding apparatus using VCSEL device for bonding a flip-chip type semiconductor chip to a substrate using infrared laser light generated from the VCSEL device. The flip-chip bonding apparatus using VCSEL device may quickly control laser light to bond a semiconductor chip to a substrate, with high productivity and high quality. | 2021-10-28 |
20210335749 | FLIP CHIP LASER BONDING SYSTEM - Provided is a flip-chip laser bonding system for bonding a semiconductor chip in the form of a flip chip to a substrate using a laser beam. In the flip-chip laser bonding system, the semiconductor chip is laser-bonded to the substrate while pressure is applied to the semiconductor chip. Accordingly, even a semiconductor chip that is bent or is capable of being bent can be bonded to a semiconductor chip without contact failure. | 2021-10-28 |
20210335750 | CHIP PACKAGE STRUCTURE WITH REDISTRIBUTION LAYER HAVING BONDING PORTION - A chip package structure is provided. The chip package structure includes a first redistribution layer having a bonding portion. The bonding portion includes a dielectric layer. The chip package structure includes a chip structure bonded to the bonding portion. A first width of the dielectric layer of the bonding portion is substantially equal to a second width of the chip structure. The chip package structure includes a protective layer over the first redistribution layer and surrounding the chip structure. A portion of the protective layer extends into the first redistribution layer and surrounds the bonding portion. | 2021-10-28 |
20210335751 | METHOD TO CONSTRUCT 3D DEVICES AND SYSTEMS - A method to construct a 3D system, the method including: providing a base wafer; transferring a first memory wafer on top of the base wafer; thinning the first memory wafer, thus forming a thin first memory wafer; transferring a second memory wafer on top of the thin first memory wafer; thinning the second memory wafer, thus forming a thin second memory wafer; and transferring a memory control wafer on top of the thin second memory wafer; where the transferring a memory control wafer includes bonding of the memory control wafer to the thin second memory wafer, and where the bonding includes oxide to oxide and conductor to conductor bonding. | 2021-10-28 |
20210335752 | METHOD OF TRANSFERRING A PLURALITY OF MICRO LIGHT EMITTING DIODES TO A TARGET SUBSTRATE, ARRAY SUBSTRATE AND DISPLAY APPARATUS THEREOF - The present application discloses a method for transferring a plurality of micro light emitting diodes (micro LEDs) to a target substrate. The method includes providing a first substrate having an array of the plurality of micro LEDs; providing a target substrate having a bonding layer having a plurality of bonding contacts; applying the plurality of bonding contacts with an electrical potential; aligning the plurality of micro LEDs with the plurality of bonding contacts having the electrical potential; and transferring the plurality of micro LEDs in the first substrate onto the target substrate. | 2021-10-28 |
20210335753 | Semiconductor Device and Method - An embodiment is package structure including a first integrated circuit die, a redistribution structure bonded to the first integrated circuit die, the redistribution structure including a first metallization pattern in a first dielectric layer, the first metallization pattern including a plurality of first conductive features, each of the first conductive features including a first conductive via in the first dielectric layer and first conductive line over the first dielectric layer and electrically coupled to the respective first conductive via, each of the first conductive lines comprising a curve in a plan view, a second dielectric layer over the first dielectric layer and the first metallization pattern, and a second metallization pattern in the second dielectric layer, the second metallization pattern including a plurality of second conductive via in the second dielectric layer, each of the second conductive vias being over and electrically coupled to a respective first conductive line. | 2021-10-28 |
20210335754 | DISPLAY PANEL AND DISPLAY DEVICE - A display panel is provided. The display panel includes a frame area, and the frame area includes an array substrate and a color filter substrate. The array substrate includes a fanout area configured to dispose a fanout trace. The color filter substrate is disposed opposite to the array substrate. The color filter substrate includes a gate driver on array (GOA) circuit and a signal trace disposed at a side of the GOA circuit. The GOA circuit is electrically connected to the signal trace. The GOA circuit and the signal trace both overlap the fanout area. | 2021-10-28 |
20210335755 | PROCESS FOR PRODUCING A HIGH-FREQUENCY-COMPATIBLE ELECTRONIC MODULE - The field of the invention is that of producing 3D electronic modules, compatible with components operating beyond 1 GHz. The invention relates to a 3D electronic module featuring an interconnection between a horizontal conductor and a vertical conductor to which it is connected exhibits, in a vertical plane, a non-zero curvature. It also relates to the associated production process. | 2021-10-28 |
20210335756 | SEMICONDUCTOR PACKAGE - A semiconductor package including a substrate; a semiconductor stack on the substrate; an underfill between the substrate and the semiconductor stack; an insulating layer conformally covering surfaces of the semiconductor stack and the underfill; a chimney on the semiconductor stack; and a molding member surrounding side surfaces of the chimney, wherein the semiconductor stack has a first upper surface that is a first distance from the substrate and a second upper surface that is a second distance from the substrate, the first distance being greater than the second distance, wherein the chimney includes a thermally conductive filler on the first and second upper surfaces of the semiconductor stack, the thermally conductive filler having a flat upper surface; a thermally conductive spacer on the thermally conductive filler; and a protective layer on the thermally conductive spacer, and wherein an upper surface of the thermally conductive spacer is exposed. | 2021-10-28 |
20210335757 | METHOD FOR PACKAGING SEMICONDUCTOR, SEMICONDUCTOR PACKAGE STRUCTURE, AND PACKAGE - Embodiments provide a method for packaging a semiconductor, a semiconductor package structure, and a package. The packaging method includes: providing a substrate wafer having a first surface and a second surface arranged opposite to each other, the first surface having a plurality of grooves, a plurality of electrically conductive pillars being provided at a bottom of the groove, and the electrically conductive pillar penetrating through the bottom of the groove to the second surface; providing a plurality of semiconductor die stacks; placing the semiconductor die stack in the groove; and filling an insulating dielectric in a gap between a sidewall of the groove and the semiconductor die stack to form an insulating dielectric layer covering an upper surface of the semiconductor die stack to seal up the semiconductor die stack so as to form the semiconductor package structure. | 2021-10-28 |
20210335758 | METHOD FOR PACKAGING SEMICONDUCTOR, SEMICONDUCTOR PACKAGE STRUCTURE, AND PACKAGE - Embodiments provide a method for packaging a semiconductor, a semiconductor package structure, and a package. The packaging method includes: providing a substrate wafer having a first surface and a second surface arranged opposite to each other, the first surface having a plurality of grooves, a plurality of electrically conductive pillars being provided at a bottom of the groove, and the electrically conductive pillar penetrating through the bottom of the groove to the second surface; providing a plurality of semiconductor die stacks; placing the semiconductor die stack in the groove, an upper surface of the semiconductor die stack being lower than or flush with an upper edge of the groove, and a bottom of the semiconductor die stack being electrically connected to the electrically conductive pillar; and providing an insulating material on the semiconductor die stack to form a semiconductor package structure. | 2021-10-28 |
20210335759 | AREA LIGHT SOURCE, METHOD FOR MANUFACTURING THE SAME AND DISPLAY DEVICE - An area light source, a method for manufacturing the same and a display device are provided. The area light source includes: a first conductive structure and a second conductive structure arranged opposite to each other; and a light-emitting layer arranged between the first conductive structure and the second conductive structure and including a plurality of light-emitting chips insulated from each other. A first electrode of each light-emitting chip is electrically connected to the first conductive structure, and a second electrode of each light-emitting chip is electrically connected to the second conductive structure. | 2021-10-28 |
20210335760 | LED BRACKET, LED DEVICE, AND EDGE-LIT BACKLIGHT MODULE - The present invention provides a light emitting diode (LED) bracket, an LED device, and an edge-lit backlight module. The LED bracket includes an insulating stand, and a conductive anode lead and a conductive cathode lead which are embedded in the insulating stand. The conductive anode lead and the conductive cathode lead comprise an anode pad and a cathode pad exposed from an upper surface of the insulating stand. The anode pad and the cathode pad are arranged symmetrical to each other on the insulating stand. The present invention utilizes symmetrically arranged metal pads to effectively solve a color difference problem of the LED device, improve luminous efficiency and stability of the LED device, and realize large-sized chip packaging, high-efficiency flip-chip packaging, and high-voltage LED packaging. | 2021-10-28 |
20210335761 | ELECTRONIC DEVICE - An electronic device is provided in this disclosure. In some embodiments, the electronic device includes two display panels, a first filling element, and a second filling element. The two display panels adjoin each other. The first filling element and the second filling element are disposed between the two display panels, and a material of the first filling element is different from a material of the second filling element. In some embodiments, the electronic device includes a protection substrate, two light emitting plates, and a filling element. The two light emitting plates adjoin each other. The protection substrate is disposed corresponding to the two light emitting plates, and the two light emitting plates emit light towards the protection substrate. The filling element is disposed between the two light emitting plates. | 2021-10-28 |
20210335762 | DISPLAY PANEL, DISPLAY MODULE, AND DISPLAY DEVICE - The present invention provides a display panel, a display module, and a display device. The display panel includes a substrate and micro-LEDs. The display module achieves an extremely-narrow-bezel design by attaching a support plate to one side of a flexible drive circuit board of the display panel, bending a bending region, and attaching a bonding region to another side of the support plate. Multiple display modules are arranged in a accommodating chamber defined by a back plate of the display device and are fixed and joined to each other. Accordingly, a narrow-gap joining technology for micro-LED is realized, thus solving a problem that the micro-LED is too small in size, and realizing large-sized micro-LED displays. | 2021-10-28 |
20210335763 | METHOD FOR MANUFACTURING ELECTRONIC DEVICE - A method for manufacturing an electronic device includes transferring a plurality of light emitting units from a carrier substrate to an object substrate through steps of: picking the plurality of light emitting units from the carrier substrate by a pick-and-place tool, and placing the plurality of light emitting units onto the object substrate. The steps are both performed under a protection by at least one electrostatic discharge protective unit. | 2021-10-28 |
20210335764 | ELECTRONIC DEVICE AND FABRICATION METHOD THEREOF - An electronic device and a fabrication method thereof are provided. The electronic device includes a circuit structure layer, a package structure, an electronic element, and a plurality of function elements. The circuit structure layer has a first side and a second side opposite to the first side. The package structure is disposed on the first side of the circuit structure layer. The electronic element is embedded or encapsulated in the package structure. The function elements are disposed on the second side of the circuit structure layer. The function elements are electrically connected to the electronic element through the circuit structure layer. The electronic device provided by the disclosure exhibits borderless design or has a large function region. | 2021-10-28 |
20210335765 | DISPLAY DEVICE - A display device comprises a plurality of first banks disposed on a substrate to extend in a first direction and spaced apart from one another, a plurality of first patterns disposed between the plurality of first banks and spaced apart from one another in the first direction, a first electrode and a second electrode extending in the first direction and disposed on different first banks of the plurality of first banks and spaced apart from each other, a first insulating layer overlapping the plurality of first patterns, disposed on the first substrate, and to partially overlapping the first and second electrodes, and a plurality of light-emitting elements disposed on the first insulating layer so that first and second ends of each of the plurality of light-emitting elements are disposed on the first and second electrodes, respectively. | 2021-10-28 |
20210335766 | DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed are a display device and a method of manufacturing the same. The display device includes a plurality of pixels on a base layer and a plurality of light emitting devices provided on a first pixel, which is one of the pixels. The light emitting devices include at least one active light emitting device and at least one dummy light emitting device. Each of the active and dummy light emitting devices includes a first surface and a second surface, which are opposite to each other, and a metal oxide pattern on the second surface. The first surface of the active light emitting device faces the base layer, and the second surface of the dummy light emitting device faces the base layer. | 2021-10-28 |
20210335767 | INTEGRATED DISPLAY DEVICES - An IC chip includes I/O bumps on a back side, a first die, a second die, a first circuit, and a second circuit. The first die has driver circuits for LED devices, the LED devices being located on a front-facing surface of the first die. The first circuit extends from the front side toward the back side and across a thickness of the first die. The first circuit provides electrical connections between the LED devices and at least some of the I/O bumps. The first die and the second die can be stacked vertically or arranged laterally adjacent. The second circuit extends between the first die and the second die to electrically connect the first die and the second die. A circuit board can be electrically connected to the IC chip through the I/O bumps to, among other things, provide power to the various components of the IC chip. | 2021-10-28 |
20210335768 | DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a display device includes forming a circuit layer on a base layer, forming a first preliminary electrode and a second preliminary electrode on the circuit layer, forming a photoresist layer on the first preliminary electrode and the second preliminary electrode, patterning the photoresist layer to form a photoresist pattern, treating a region of each of the first preliminary electrode and the second preliminary electrode to form a first electrode and a second electrode having regions of lower and higher electrical resistance, and disposing a light-emitting element on the first electrode and the second electrode at regions having lower electrical resistance. | 2021-10-28 |
20210335769 | DISPLAY APPARATUS, MANUFACTURING METHOD AND OPERATING METHOD THEREOF - A display apparatus includes a display panel having an image acquisition region within a display area, and an image acquisition device over a side of the display panel opposing to its display surface. The image acquisition device is at a position corresponding to the image acquisition region, and is configured to capture an image based on lights from an outside pattern over a side of the display panel proximal to the display surface. The display panel includes a substrate and a plurality of light-emitting elements over the substrate. The plurality of light-emitting elements comprises one or more first light-emitting elements positionally within the image acquisition region. At least one first light-emitting element includes a non-transparent electrode provided with at least one through-hole configured to allow the lights from the outside pattern to pass through the display panel. | 2021-10-28 |
20210335770 | DISPLAY DEVICE - Provided is a display device capable of preventing or reducing short-circuiting in an alternating high and low temperature environment. The display device is configured to display an image in a display region and includes: an insulating substrate; conductive lines provided on the insulating substrate and extending from the display region to a frame region exterior to the display region; a driver provided in the frame region and connected to the conductive lines; an organic protective film overlapping the conductive lines and extending from the display region to a region between the display region and the driver; an anisotropic conductive film provided under the driver and covering an end of the organic protective film between the display region and the driver; and a moisture-proof resin film overlapping the anisotropic conductive film and covering the end of the organic protective film between the display region and the driver. | 2021-10-28 |
20210335771 | CONTROL CIRCUIT AND HIGH ELECTRON MOBILITY ELEMENT - A control circuit applied in a specific element and including a first transistor and an electrostatic discharge (ESD) protection circuit is provided. The specific element has a III-V semiconductor material and includes a control electrode, a first electrode and a second electrode. The first transistor is coupled between the first electrode and the second electrode and has the III-V semiconductor material. The ESD protection circuit is coupled to the control electrode, the first transistor and the second electrode. In response to an ESD event, the ESD protection circuit provides a discharge path to release the ESD current from the control electrode to the second electrode. | 2021-10-28 |
20210335772 | CASCODE CELL - The present disclosure relates to semiconductor structures and, more particularly, to unitary Cascode cells with resistance and capacitance optimization, and methods of manufacture. The structure includes a common source FET (CS-FET) in a first portion of a single common semiconductor region, the CS-FET comprising a source region and a drain region, a common gate FET (CG-FET) in a second portion of the single common semiconductor region, the CG-FET comprising a source region and a drain region, and a doped connecting region of the single common semiconductor region, connecting the drain of the CS-FET and the source of the CG-FET. | 2021-10-28 |
20210335773 | Symmetric FET for RF Nonlinearity Improvement - A physical layout of a symmetric FET is described which provides symmetry in voltages coupled to structures of the FET so to reduce OFF state asymmetry in capacitances generated by the structures when the FET is used as a switch. According to one aspect, the symmetric FET is divided into two halves that are electrically coupled in parallel. Gate structures of the two half FETs are arranged in the middle region of the layout, each gate structure having gate fingers that project towards opposite directions. Interdigitated source and drain structures run along the gate fingers and include crossover structures that cross source and drain structures in the middle region of the layout. The gate structures share a body contact region that is arranged in the middle of the layout between the two gate structures. | 2021-10-28 |
20210335774 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - Between strap power supply lines that supply a power supply potential VDD, standard cell columns and standard cell columns are arranged alternately in a Y-direction. Out of capacitor cells and correction cells, only the capacitor cells are arranged in the standard cell columns, and only the correction cells are arranged in the standard cell columns. | 2021-10-28 |
20210335775 | Silicon Controlled Rectifier and Method for Making the Same - The application provides a SCR and a manufacturing method thereof. The SCR comprises: a P-type heavily doped region | 2021-10-28 |
20210335776 | Silicon Controlled Rectifier and Method for Making the Same - The application provides a SCR and a manufacturing method thereof. The SCR comprises: a P-type heavily doped region | 2021-10-28 |
20210335777 | SILICON CONTROLLED RECTIFIER AND METHOD FOR MAKING THE SAME - The present disclosure provides a silicon controlled rectifier and a manufacturing method thereof. The silicon controlled rectifier comprises: a P-type substrate; an N-type well | 2021-10-28 |
20210335778 | TRANSISTOR DEVICES AND METHODS OF FORMING A TRANSISTOR DEVICE - According to various embodiments, a transistor device may include a semiconductor structure having a trench formed therein. The semiconductor structure may include a buffer layer and a barrier layer arranged over the buffer layer. The trench may extend at least to the buffer layer. The transistor device may include a source terminal, a drain terminal, and a gate terminal arranged between the source terminal and the drain terminal. The gate terminal may extend into the trench. The transistor device may include an electrode component. The electrode component may include an electrode. The electrode component may extend into the trench where the electrode component is separated from the gate terminal. The electrode component may contact a side wall of the trench. | 2021-10-28 |
20210335779 | RESISTOR WITH DOPED REGIONS AND SEMICONDUCTOR DEVICES HAVING THE SAME - A resistor including a device isolation layer is described that includes a first active region and a second active region, a buried insulating layer, and an N well region. The N well region surrounds the first active region, the second active region, the device isolation layer and the buried insulating layer. A first doped region and a second doped region are disposed on the first active region and the second active region. The first doped region and the second doped region are in contact with the N well region and include n type impurities. | 2021-10-28 |
20210335780 | COMPUTATION-IN-MEMORY IN THREE-DIMENSIONAL MEMORY DEVICE - Three-dimensional (3D) memory devices are provided. An exemplary 3D memory device includes a first semiconductor structure including a peripheral circuit, a data processing circuit, and a first bonding layer including a plurality of first bonding contacts. The peripheral circuit and the data processing circuit are stacked over one another vertically on different planes. The 3D memory device also includes a second semiconductor structure including an array of 3D NAND memory strings and a second bonding layer including a plurality of second bonding contacts. In addition, the 3D memory device includes a bonding interface between the first bonding layer and the second bonding layer. The first bonding contacts are in contact with the second bonding contacts at the bonding interface. | 2021-10-28 |
20210335781 | POWER SEMICONDUCTOR DEVICE WITH AN AUXILIARY GATE STRUCTURE - Power semiconductor devices in GaN technology include an integrated auxiliary (double) gate terminal and a pulldown network to achieve a normally-off (E-Mode) GaN transistor with threshold voltage higher than 2V, low gate leakage current and enhanced switching performance. The high threshold voltage GaN transistor has a high-voltage active GaN device and a low-voltage auxiliary GaN device wherein the high-voltage GaN device has the gate connected to the source of the integrated auxiliary low-voltage GaN transistor and the drain being the external high-voltage drain terminal and the source being the external source terminal, while the low-voltage auxiliary GaN transistor has the gate (first auxiliary electrode) connected to the drain (second auxiliary electrode) functioning as an external gate terminal. A pull-down network for the switching-off of the high threshold voltage GaN transistor may be formed by additional auxiliary low-voltage GaN transistors and resistive elements connected with the low-voltage auxiliary GaN transistor. | 2021-10-28 |
20210335782 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided is a semiconductor device including a substrate, an isolation structure, a gate dielectric layer, a high-k dielectric layer, and a protection cap. The substrate includes a first region, a second region, and a transition region located between the first region and the second region. The isolation structure, located in the transition region. The gate dielectric layer is located on the isolation structure. The high-k dielectric layer is located on the isolation structure and extended to cover a sidewall and a surface of the gate dielectric layer. The protection cap is located on a surface and sidewalls of the high-k dielectric layer. | 2021-10-28 |
20210335783 | Self-Aligned Etch in Semiconductor Devices - Methods of performing backside etching processes on source/drain regions and gate structures of semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a first interconnect structure on a front-side of the first transistor structure; and a second interconnect structure on a backside of the first transistor structure, the second interconnect structure including a first dielectric layer on the backside of the first transistor structure; a contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and first spacers along sidewalls of the contact between the contact and the first dielectric layer, sidewalls of the first spacers facing the first dielectric layer being aligned with sidewalls of the source/drain region of the first transistor structure. | 2021-10-28 |
20210335784 | INPUT/OUTPUT DEVICES - Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a first transistor in a first area and a second transistor in a second area. The first transistor includes a first gate structure extending lengthwise along a first direction, and a first gate spacer, a second gate spacer, and a third gate spacer over sidewalls of the first gate structure. The second transistor includes a second gate structure extending lengthwise along the first direction, and the first gate spacer and the third gate spacer over sidewalls of the second gate structure. The first gate spacer, the second gate spacer and the third gate spacer are of different compositions and the third gate spacer is directly on the first gate spacer in the second area. | 2021-10-28 |
20210335785 | INTEGRATED CIRCUIT STRUCTURE - An IC fabrication method includes forming a first fin on a semiconductor substrate, forming an isolation dielectric material over the first fin, and planarizing the isolation dielectric material. A top surface of the first fin is covered by the isolation dielectric material after planarizing the isolation dielectric material. The method further includes etching back the isolation dielectric material until the first fin protrudes from the isolation dielectric material. | 2021-10-28 |
20210335786 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a patterned mask on the second region; and performing a process to enlarge the first fin-shaped structure so that the top surfaces of the first fin-shaped structure and the second fin-shaped structure are different. | 2021-10-28 |
20210335787 | SEMICONDUCTOR DEVICE AND METHOD - A method includes forming fins extending over a semiconductor substrate; forming a photoresist structure over the fins; patterning a serpentine cut pattern in the photoresist structure to form a cut mask, wherein the serpentine cut pattern extends over the fins, wherein the serpentine cut pattern includes alternating bridge regions and cut regions, wherein each cut region extends in a first direction, wherein each bridge region extends between adjacent cut regions in a second direction, wherein the second direction is within 30° of being orthogonal to the first direction; and performing an etching process using the cut mask as an etching mask. | 2021-10-28 |
20210335788 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device with a large storage capacity per unit area is provided. The disclosed semiconductor device includes a plurality of gain-cell memory cells each stacked over a substrate. Axes of channel length directions of write transistors of memory cells correspond to each other, and are substantially perpendicular to the top surface of the substrate. The semiconductor device can retain multi-level data. The channel of read transistors is columnar silicon (embedded in a hole penetrating gates of the read transistors). The channel of write transistors is columnar metal oxide (embedded in a hole penetrating the gates of the read transistors and gates, or write word lines, of the write transistors). The columnar silicon faces the gate of the read transistor with an insulating film therebetween. The columnar metal oxide faces the write word line with an insulating film, which is obtained by oxidizing the write word line, therebetween, and is electrically connected to the gate of the read transistor. | 2021-10-28 |
20210335789 | SEMICONDUCTOR MEMORY DEVICE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC DEVICE INCLUDING THE SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device, a method of manufacturing the same, and an electronic device including the semiconductor memory device are disclosed. According to an embodiment, the semiconductor memory device may include a substrate; an array of memory cells provided on the substrate, wherein the memory cells are arranged in rows and columns, each of the memory cells comprises a pillar-shaped active region extending vertically, wherein the pillar-shaped active region comprises source/drain regions at upper and lower ends respectively and a channel region between the source/drain regions; and a plurality of bit lines formed on the substrate, wherein each of the bit lines is located below a corresponding one of the columns of memory cells and is electrically connected to the source/drain regions at lower ends of the respective memory cells in the corresponding column, wherein each of the memory cells further comprises a gate stack formed around a periphery of a corresponding channel region, and a respective one of the rows of memory cells has gate conductor layers included in the gate stacks of the respective memory cells in the row extending continuously in a direction of the row to form a corresponding one of word lines. | 2021-10-28 |
20210335790 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor memory device and a method of fabricating the same. The semiconductor memory device may include: a first impurity doped region and a second impurity doped region spaced apart from each other in a semiconductor substrate, a bit line electrically connected to the first impurity doped region and crossing over the semiconductor substrate, a storage node contact electrically connected to the second impurity doped region, a first spacer and a second spacer disposed between the bit line and the storage node contact, and an air gap region disposed between the first spacer and the second spacer. The first spacer may cover a sidewall of the bit line, and the second spacer may be adjacent to the storage node contact. A top end of the first spacer may have a height higher than a height of a top end of the second spacer. | 2021-10-28 |
20210335791 | THREE-DIMENSIONAL MEMORY ARRAYS WITH LAYER SELECTOR TRANSISTORS - A three-dimensional memory array may include a first memory array and a second memory array, stacked above the first. Some memory cells of the first array may be coupled to a first layer selector transistor, while some memory cells of the second array may be coupled to a second layer selector transistor. The first and second layer selector transistor may be coupled to one another and to a peripheral circuit that controls operation of the first and/or second memory arrays. A different layer selector transistor may be used for each row of memory cells of a given memory array and/or for each column of memory cells of a given memory array. Such designs may allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density. | 2021-10-28 |
20210335792 | SEMICONDUCTOR MEMORY DEVICE WITH AIR GAPS FOR REDUCING CAPACITIVE COUPLING AND METHOD FOR PREPARING THE SAME - The present disclosure provides a semiconductor memory device with air gaps for reducing capacitive coupling between a bit line and an adjacent conductive feature and a method for preparing the semiconductor memory device. The semiconductor memory device includes a substrate; an isolation member defining an active region having a first P-type ion concentration in the substrate; a gate structure disposed in the substrate; a first doped region positioned at a first side of the gate structure in the active region; a second doped region positioned at a second side of the gate structure in the active region; a bit line positioned on the first doped region; an air gap positioned adjacent to the bit line; a capacitor plug disposed on the second doped region and a barrier layer on a sidewall of the capacitor plug; and a landing pad on a top portion of the capacitor plug, wherein the landing pad comprises a first silicide layer disposed over a protruding portion of the capacitor plug, and a second silicide layer disposed on a sidewall of the barrier layer. | 2021-10-28 |
20210335793 | Transistors, Memory Arrays, And Methods Used In Forming An Array Of Memory Cells Individually Comprising A Transistor - A method used in forming an array of memory cells comprises forming lines of top-source/drain-region material, bottom-source/drain-region material, and channel-region material vertically there-between in rows in a first direction. The lines are spaced from one another in a second direction. The top-source/drain-region material, bottom-source/drain-region material, and channel-region material have respective opposing sides. The channel-region material on its opposing sides is laterally recessed in the second direction relative to the top-source/drain-region material and the bottom-source/drain-region material on their opposing sides to form a pair of lateral recesses in the opposing sides of the channel-region material in individual of the rows. After the pair of lateral recesses are formed, the lines of the top-source/drain-region material, the channel-region material, and the bottom-source/drain-region material are patterned in the second direction to comprise pillars of individual transistors. Rows of wordlines are formed in the first direction that individually are operatively aside the channel-region material of individual of the pillars in the pairs of lateral recesses and that interconnect the transistors in that individual row. Other embodiments, including structure independent of method, are disclosed. | 2021-10-28 |
20210335794 | METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE - A method of manufacturing a semiconductor structure includes: receiving a substrate having an active region and a non-active region adjacent to the active region; forming an etch stop layer over the non-active region of the substrate, in which the etch stop layer is oxide-free; forming an isolation over the etch stop layer; removing a portion of the active region and a portion of the isolation to form a first trench in the active region and a second trench over the etch stop layer, respectively, in which a thickness of the etch stop layer beneath the second trench is greater than a depth difference between the first trench and the second trench; forming a dielectric layer in the first trench; and filling a conductive material on the dielectric layer in the first trench and in the second trench. A semiconductor structure is also provided. | 2021-10-28 |
20210335795 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. The method includes: providing a semiconductor substrate; determining a position of a bit line contact opening on a top surface of the semiconductor substrate and a top surface of a first dielectric layer; etching an active region, the first dielectric layer and an isolation structure exposed by the bit line contact opening according to the position of the bit line contact opening until the active region is etched to a preset depth to form a bit line contact window; and forming a second dielectric layer on a surface of the isolation structure and a surface of the first dielectric layer that have a depth greater than a depth of a surface of the active region in the bit line contact window. | 2021-10-28 |
20210335796 | SRAM DEVICE AND MANUFACTURING METHOD THEREOF - An SRAM memory device includes a substrate, a first transistor, a second transistor, a metal interconnect structure, and a capacitor. The metal interconnect structure is formed on the first and second transistors. The capacitor is disposed in the metal interconnect structure and coupled between the first transistor and the second transistor. The capacitor includes a lower metal layer, a first electrode layer, a dielectric layer, a second electrode layer, and an upper metal layer from bottom to top. The lower metal layer is coupled to a source node of the first transistor and a source node of the second transistor. The lower metal layer and an n-th metal layer in the metal interconnect structure are formed of a same material, wherein n≥1; the upper metal layer and an m-th metal layer in the metal interconnect structure are formed of a same material, wherein m≥n+1. | 2021-10-28 |
20210335797 | STATIC RANDOM ACCESS MEMORY WITH MAGNETIC TUNNEL JUNCTION CELLS - Disclosed herein are related to a memory cell including magnetic tunneling junction (MTJ) devices. In one aspect, the memory cell includes a first layer including a first transistor and a second transistor. In one aspect, the first transistor and the second transistor are connected to each other in a cross-coupled configuration. A first drain structure of the first transistor may be electrically coupled to a first gate structure of the second transistor, and a second drain structure of the second transistor may be electrically coupled to a second gate structure of the first transistor. In one aspect, the memory cell includes a second layer including a first MTJ device electrically coupled to the first drain structure of the first transistor and a second MTJ device electrically coupled to the second drain structure of the second transistor. In one aspect, the second layer is above the first layer. | 2021-10-28 |
20210335798 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THEREOF - Provided is a semiconductor memory device. The semiconductor memory device comprises a first semiconductor pattern including a first impurity region, a second impurity region, and a channel region, the first impurity region spaced apart from a substrate in a first direction and having a first conductivity type, the second impurity region having a second conductivity type different from the first conductivity type, and the channel region between the first impurity region and the second impurity region, a first conductive connection line connected to the first impurity region and extending in a second direction different from the first direction and a first gate structure extending in the first direction and including a first gate electrode and a first gate insulating film, wherein the first gate electrode penetrates the channel region and the first gate insulating film is between the first gate electrode and the semiconductor pattern. | 2021-10-28 |
20210335799 | FERROELECTRIC RANDOM ACCESS MEMORY DEVICE WITH SEED LAYER - In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a bottom electrode disposed over a substrate and a top electrode disposed over the bottom electrode. A ferroelectric switching layer is arranged between the bottom electrode and the top electrode. The ferroelectric switching layer is configured to change polarization based upon one or more voltages applied to the bottom electrode or the top electrode. A seed layer is arranged between the bottom electrode and the top electrode. The seed layer and the ferroelectric switching layer have a non-monoclinic crystal phase. | 2021-10-28 |
20210335800 | VERTICAL SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A method for fabricating semiconductor device includes forming an alternating stack that includes a lower multi-layered stack and an upper multi-layered stack by alternately stacking a dielectric layer and a sacrificial layer over a substrate, forming a vertical trench that divides the upper multi-layered stack into dummy stacks, and forming an asymmetric stepped trench that is extended downward from the vertical trench to divide the lower multi-layered stack into a pad stack and a dummy pad stack, wherein forming the asymmetric stepped trench includes forming a first stepped sidewall that is defined at an edge of the pad stack, and forming a second stepped sidewall that is defined at an edge of the dummy pad stack and occupies less area than the first stepped sidewall. | 2021-10-28 |
20210335801 | MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a memory device including a substrate, a stack structure, a first set of vertical channel structures, a second set of vertical channel structures, and a first slit. The stack structure is disposed on the substrate. The first and second sets of vertical channel structures are arranged along a Y direction and penetrate through the stack structure to contact the substrate. The first slit is disposed between the first and second sets of vertical channel structures, and penetrates through the stack structure to expose the substrate. The first slit includes a plurality of first sub-slits discretely disposed along a X direction. | 2021-10-28 |
20210335802 | MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A memory device includes: first and second bit lines on a dielectric layer; first and second word lines between the first and second bit lines; a source line between the first and second word lines; a channel pillar penetrating through the first word line, the source line and the second word line, and connected to the first bit line, the source line, and the second bit line; a first charge storage structure surrounding a top surface and a bottom surface of the first word line and between a sidewall of the first word line and a lower portion of a sidewall of the channel pillar; and a second charge storage structure, surrounding a top surface and a bottom surface of the second word line and between a sidewall of the second word line and an upper portion of the sidewall of the channel pillar. | 2021-10-28 |
20210335803 | Integrated Circuitry, Memory Arrays Comprising Strings Of Memory Cells, Methods Used In Forming Integrated Circuitry, And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells - A method used in forming integrated circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack comprises a cavity therein that comprises a stair-step structure. At least a portion of sidewalls of the cavity is lined with sacrificial material. Insulative material is formed in the cavity radially inward of the sacrificial material. At least some of the sacrificial material is removed from being between the cavity sidewalls and the insulative material to form a void space there-between. Insulator material is formed in at least some of the void space. Other embodiments, including structure independent of method, are disclosed. | 2021-10-28 |
20210335804 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a first staircase structure, a second staircase structure, a conductive pillar, and a contact pillar. The first staircase structure includes conductive stair layers. The conductive pillar passes through the second staircase structure. The conductive pillar has an upper conductive pillar end and a lower conductive pillar end opposing to the upper conductive pillar end. The contact pillar is electrically connected on one conductive stair layer of the conductive stair layers. The contact pillar has an upper contact end and a lower contact end opposing to the upper contact end. The upper contact end and the lower contact end are respectively electrically connected to the upper conductive pillar end of the conductive pillar and the one conductive stair layer. | 2021-10-28 |
20210335805 | THREE-DIMENSIONAL MEMORY DEVICE EMPLOYING THINNED INSULATING LAYERS AND METHODS FOR FORMING THE SAME - A three-dimensional memory device includes an alternating stack of word lines and at least one insulating layers or air gaps located over a substrate, a memory opening fill structure extending through the alternating stack. The memory opening fill structure includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. The word lines are thicker than the insulating layers or air gaps. | 2021-10-28 |
20210335806 | THREE-DIMENSIONAL MEMORY DEVICES WITH DRAIN-SELECT-GATE CUT STRUCTURES AND METHODS FOR FORMING THE SAME - Embodiments of structures and methods for forming three-dimensional (3D) memory devices are provided. In an example, a 3D memory device includes a core region and a staircase region. The staircase region includes a plurality of stairs each has at least a conductor/dielectric pair extending in a lateral direction. The staircase region includes a drain-select-gate (DSG) cut structure extending along the lateral direction and a vertical direction, and a plurality of support structures extending in the DSG structure along the vertical direction. Of at least one of the support structures, a dimension along the lateral direction is greater than a dimension along a second lateral direction perpendicular to the lateral direction. | 2021-10-28 |
20210335807 | THREE-DIMENSIONAL MEMORY DEVICE AND METHOD FOR FORMING THE SAME - Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a P-type doped region of a substrate, an N-type doped semiconductor layer on the P-type doped region, a memory stack including interleaved conductive layers and dielectric layers on the N-type doped semiconductor layer, a channel structure extending vertically through the memory stack and the N-type doped semiconductor layer into the P-type doped region, an N-type doped semiconductor plug extending vertically into the P-type doped region, and a source contact structure extending vertically through the memory stack to be in contact with the N-type doped semiconductor plug. | 2021-10-28 |
20210335808 | THREE-DIMENSIONAL MEMORY DEVICE AND METHOD FOR FORMING THE SAME - Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes an N-type doped region of a substrate, an N-type doped semiconductor layer on the N-type doped region, a memory stack including interleaved conductive layers and dielectric layers on the N-type doped semiconductor layer, a channel structure extending vertically through the memory stack and the N-type doped semiconductor layer into the N-type doped region, and a source contact structure extending vertically through the memory stack and the N-type doped semiconductor layer into the N-type doped region. A first lateral dimension of a first portion of the source contact structure surrounded by the N-type doped region is greater than a second lateral dimension of a second portion of the source contact structure surrounded by the memory stack. | 2021-10-28 |
20210335809 | SEMICONDUCTOR DEVICES HAVING ISOLATION INSULATING LAYERS - A semiconductor device includes a substrate including cell array, extension, and through electrode areas; a memory stack on the substrate and including first gate electrodes, insulating layers, and mold layers, the first gate electrodes and the insulating layers being sequentially stacked, and the mold layers including an insulating material and being on the through electrode area at a same level as the first gate electrodes; a channel structure vertically penetrating the first gate electrodes; a through electrode vertically penetrating the mold layers; first isolation insulating layers vertically penetrating the memory stack, extending in a first direction, and being spaced apart from each other in a second direction; and a second isolation insulating layer between the channel structure and the through electrode area and extending in the second direction and vertically penetrating the first gate electrodes, and in plan view, the second isolation insulating layer intersects the first isolation insulating layers. | 2021-10-28 |
20210335810 | SEMICONDUCTOR DEVICES INCLUDING CHANNEL PATTERN AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a gate structure on a substrate, the gate structure including insulating layers and gate electrodes, which are alternately stacked, a channel structure extending through the gate structure, and a source conductive pattern between the substrate and the gate structure. The source conductive pattern includes a lower source conductive pattern and an upper source conductive pattern on the lower source conductive pattern. The channel structure includes an insulating pattern extending through the source conductive pattern, a data storage pattern, and a channel pattern between the insulating pattern and the data storage pattern. A lower surface of the channel pattern is at a level higher than an upper surface of the upper source conductive pattern, but lower than a lower surface of a lowermost one of the gate electrodes in a cross-sectional view of the semiconductor device with the substrate providing a base reference level. | 2021-10-28 |
20210335811 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes a substrate including a cell array region, a first gate electrode including an opening on the cell array region of the substrate, a plurality of second gate electrodes stacked above the first gate electrode and including convex portions having an outward curve extending toward the substrate, and a word line cutting region cutting the opening and the convex portions. | 2021-10-28 |
20210335812 | THREE-DIMENSIONAL MEMORY DEVICES WITH DRAIN-SELECT-GATE CUT STRUCTURES AND METHODS FOR FORMING THE SAME - Embodiments of structures and methods for forming three-dimensional (3D) memory devices are provided. In an example, a 3D memory device includes a core region and a staircase region. The staircase region includes a plurality of stairs each has at least a conductor/dielectric pair extending in a lateral direction. The staircase region includes a drain-select-gate (DSG) cut structure extending along the lateral direction and a vertical direction, and a plurality of support structures extending in the DSG structure along the vertical direction. Of at least one of the support structures, a dimension along the lateral direction is greater than a dimension along a second lateral direction perpendicular to the lateral direction. | 2021-10-28 |
20210335813 | METHODS FOR FORMING CHANNEL STRUCTURES IN THREE-DIMENSIONAL MEMORY DEVICES - Methods for forming channel structures in 3D memory devices are disclosed. In one example, a memory film and a sacrificial layer are subsequently formed along a sidewall and a bottom of a channel hole. A protective structure covering a portion of the sacrificial layer along the sidewall of the channel hole is formed. A portion of the sacrificial layer at the bottom of the channel hole that is not covered by the protective structure is wet etched. A portion of the memory film at the bottom of the channel hole that is not covered by a remainder of the sacrificial layer is wet etched. | 2021-10-28 |
20210335814 | THREE-DIMENSIONAL MEMORY DEVICE HAVING ADJOINED SOURCE CONTACT STRUCTURES AND METHODS FOR FORMING THE SAME - A plurality of holes are formed extending vertically in a first dielectric deck that includes interleaved a plurality of first sacrificial layers and a plurality of first dielectric layers over a substrate. A plurality of sacrificial structures are formed in the holes. A second dielectric deck is formed having interleaved a plurality of second sacrificial layers and a plurality of second dielectric layers over the first dielectric deck. A slit opening is formed extending in the second dielectric deck, the slit opening aligned with and over the sacrificial source contact structures. The sacrificial structures are removed through the slit openings such that the slit opening is in contact with the holes to form a slit structure. A plurality of conductor layers are formed in the first and second dielectric decks through the slit structure, forming a memory stack. A source contact structure is formed in the slit structure. | 2021-10-28 |
20210335815 | SEMICONDUCTOR DEVICES INCLUDING STACK OXIDE MATERIALS HAVING DIFFERENT DENSITIES OR DIFFERENT OXIDE PORTIONS, AND SEMICONDUCTOR DEVICES INCLUDING STACK DIELECTRIC MATERIALS HAVING DIFFERENT PORTIONS - Semiconductor structures may include a stack of alternating dielectric materials and control gates, charge storage structures laterally adjacent to the control gates, a charge block material between each of the charge storage structures and the laterally adjacent control gates, and a pillar extending through the stack of alternating oxide materials and control gates. Each of the dielectric materials in the stack has at least two portions of different densities and/or different rates of removal. Also disclosed are methods of fabricating such semiconductor structures. | 2021-10-28 |
20210335816 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor layer, a first electrode, first to third layers, and nitride portions of nitride molecules. The first layer is provided between the semiconductor layer and the first electrode. The second layer is provided between the first layer and the first electrode. The second energy of a conduction band edge of the second layer is lower than a first energy of a conduction band edge of the first layer. The second layer includes a first region and a second region. The first region is provided between the first layer and the second region. The third layer is provided between the second layer and the first electrode. The third energy of a conduction band edge of the third layer is higher than the second energy. | 2021-10-28 |
20210335817 | Integrated Assemblies Having Vertically-Spaced Channel Material Segments, and Methods of Forming Integrated Assemblies - Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and second regions proximate to the control gate regions. High-k dielectric material wraps around ends of the control gate regions, and is not along the second regions. Charge-blocking material is adjacent to the high-k dielectric material. Charge-storage material is adjacent to the charge-blocking material. The charge-storage material is configured as segments which are vertically stacked one atop another, and which are vertically spaced from one another by gaps. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies, and methods of forming integrated assemblies. | 2021-10-28 |
20210335818 | Integrated Assemblies Having Vertically-Spaced Channel Material Segments, and Methods of Forming Integrated Assemblies - Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and distal regions proximate the control gate regions. The control gate regions have front surfaces, top surfaces and bottom surfaces. The top and bottoms surfaces extend back from the front surfaces. High-k dielectric material is along the control gate regions. The high-k dielectric material has first regions along the top and bottom surfaces, and has second regions along the front surfaces. The first regions are thicker than the second regions. Charge-blocking material is adjacent to the second regions of the high-k dielectric material. Charge-storage material is adjacent to the charge-blocking material. Gate-dielectric material is adjacent to the charge-storage material. Channel material is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies. Some embodiments include methods of forming integrated assemblies. | 2021-10-28 |
20210335819 | SEMICONDUCTOR DEVICES INCLUDING UPPER AND LOWER SELECTORS - A semiconductor device includes a lower stack structure that includes a lower word line, an upper stack structure that is on the lower stack structure and includes an upper word line, a decoder that is adjacent to the lower stack structure and the upper stack structure, a signal interconnection that is connected to the decoder, a lower selector that is connected to the signal interconnection and further connected to the lower word line, and an upper selector that is connected to the signal interconnection, isolated from direct contact with the lower selector, and further connected to the upper word line. | 2021-10-28 |
20210335820 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE - A semiconductor device includes: a stack structure including conductive patterns and insulating layers, which are alternately stacked; a channel structure penetrating the stack structure; and a memory layer penetrating the stack structure, the memory layer being disposed between the channel structure and the stack structure. The memory layer includes memory parts and dummy parts, which are alternately arranged. Each of the memory parts includes a first part between the insulating layers and a second part between the dummy parts. The first part of the memory parts have ferroelectricity. | 2021-10-28 |
20210335821 | METHOD FOR FORMING INTEGRATED CIRCUIT - A method for forming an integrated circuit includes following operations. A substrate having a first region, a second region and an isolation structure is received. A portion of the substrate is removed such that the second region is recessed. A portion of the isolation structure is removed to obtain a first top surface, a second top surface lower than the first top surface, and a boundary between the first top surface and the second top surface. A first device is formed in the first region, a second device is formed in the second region, and a dummy structure is formed over the first top surface, the second top surface and the boundary. A dielectric structure is formed over the substrate. A top surface of the first device, a top surface of the second device and a top surface of the dummy structure are aligned with each other. | 2021-10-28 |
20210335822 | ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF - Disclosed is an array substrate, including a substrate, and a first data line, a first insulating layer and a second data line, which are disposed on the substrate in sequence. The first insulating layer is provided with a first via hole. The second data line is connected to the first data line through the first via hole. By configuring double-layer data lines, an area of the data lines is increased, thereby reducing the impedance of the data lines, thereby improving the charging capability of the remote pixels and the display quality of the panel. | 2021-10-28 |
20210335823 | ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF, AND DISPLAY PANEL - An array substrate, a manufacturing method thereof, and display panel are provided. Gate scanning lines and Light-shielding conductive layer are electrically connected, so that a width of the gate scanning line is substantially unchanged from the conventional technology to ensure an aperture ratio of a display panel. Therefore, an impedance of the wire used to transmit the scanning electrical signal is reduced, so that the display panel driving power consumption is reduced to increase the corresponding speed of pixel charging and discharging. | 2021-10-28 |
20210335824 | TFT ARRAY SUBSTRATE AND DISPLAY PANEL THEREOF - A thin-film transistor (TFT) array substrate includes a substrate layer and a metal layer disposed on the substrate layer. The metal layer includes a first metal layer and a second metal layer disposed on the first metal layer. The first metal layer includes a main body portion and a tail portion. The main body portion of the first metal layer is disposed corresponding to the second metal layer in an upper direction, and the tail portion of the first metal layer is disposed on an end of the main body portion of the first metal layer and extends outwardly from the second metal layer. The TFT array substrate using a novel metal layer structure to effectively improve a situation that light leakage occurred at the metal layer structure of an array substrate in a dark state, and thus to increase product contrast. | 2021-10-28 |
20210335825 | DOUBLE-SIDED DISPLAY PANEL AND DISPLAY DEVICE - A double-sided display panel and a display device are provided. The double-sided display panel includes a first display module, a second display module, a conductive layer, and a driving module. The conductive layer is electrically connected to at least one of the first thin film transistor substrate of the first display module and the second thin film transistor substrate of the second display module. | 2021-10-28 |
20210335826 | METHOD OF MANUFACTURING DISPLAY PANEL AND THE DISPLAY PANEL - A method of manufacturing a display panel is that when the preparation of a front side of the display panel is finished, a structure composed of a protective layer, a sacrificial layer, a planarization layer, and a passivation layer is introduced as a protective film. The protective film structure does not contaminate vacuum equipment such as CVD or PVD. Moreover, the protective film structure has characteristics of hardness and abrasion resistance, so it does not produce residual stripper on the conveyor and does not interfere with the manufacturing process for the back side of the display panel. Moreover, the flatness of a surface of the film layer formed by CVD and coating machine is conducive to transfer and adsorption. The protective film may be completely removed by the means of LLO and dry-etching. The method of the process can effectively realize the double-sided process for single glass. | 2021-10-28 |
20210335827 | ARRAY SUBSTRATE AND DISPLAY PANEL - An array substrate and a display panel are provided. The array substrate includes scanning lines, data lines, pixel electrodes disposed between the scanning lines and the data lines, and thin film transistors electrically connected to the scanning lines, data lines, and pixel electrodes. By disposing openings on positions of gate electrodes of the thin film transistors corresponding to drain electrodes, a problem of inconsistent parasitic capacitance between the gate electrodes and the drain electrodes of the thin film transistors due to position shifting of the drain electrodes of the thin film transistors can be solved, thereby improving display quality of the display panel using the array substrate. | 2021-10-28 |
20210335828 | DISPLAY PANEL - A display panel is provided. The display panel includes a base substrate, an active layer, a gate layer, and a threshold voltage adjustment metal layer. The threshold voltage adjustment metal layer is disposed on a side of the active layer away from the gate layer and is connected to the gate layer. When the threshold voltage adjustment metal layer is at a positive potential, a threshold voltage of a switching thin-film transistor is reduced, thereby easily turning on the switching thin-film transistor. When the threshold voltage adjustment metal layer is at a negative potential, the threshold voltage of the switching thin-film transistor is increased, thereby difficultly turning off the switching thin-film transistor. Therefore, a technical problem about high power consumption in the display panels existing in the prior art is solved. | 2021-10-28 |
20210335829 | DISPLAY PANEL AND ELECTRONIC DEVICE - The present disclosure provides a display panel and an electronic device. The display panel includes a plurality of pixels, and the pixels include a main-pixel region and a sub-pixel region. The main-pixel region includes a common electrode portion including a sharing electrode, and a voltage of the sharing electrode is a fixed value. The sub-pixel region comprises a sub-driving thin film transistor and a sharing thin film transistor, wherein a drain of the sharing thin film transistor is connected to the sharing electrode, and a source of the sharing thin film transistor is connected to a drain of the sub-driving thin film transistor. | 2021-10-28 |
20210335830 | FABRICATION METHOD OF ARRAY SUBSTRATE WITH GREATER ADHESION BETWEEN CONDUCTIVE LAYER AND CONNECTION MEMBER - An array substrate, a fabrication method thereof, and a display device are provided. The fabrication method includes forming a first conductive layer and a second conductive layer on both of a first area and a second area of a substrate; forming a bonding pin in the first area to electrically connect with a driving chip, wherein the second conductive layer is located at a side of the first conductive layer away from the substrate; and removing the second conductive layer in the second area, forming a conductive electrode in the second area to electrically connect with a light-emitting element by a connection member. | 2021-10-28 |