43rd week of 2021 patent applcation highlights part 63 |
Patent application number | Title | Published |
20210336031 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A semiconductor structure and a method for forming the semiconductor structure are provided. The semiconductor structure includes a substrate including a first region and a second region, a first gate structure over the first region, and first source-drain doped layers in the first region of the substrate on both sides of the first gate structure. The semiconductor structure also includes a second gate structure over the second region, and second source-drain doped layers in the second region of the substrate on both sides of the second gate structure. Further, the semiconductor structure includes a first protection layer over the second gate structure, a first conductive structure over a first source-drain doped layer, and an isolation layer over the first conductive structure. The first conductive structure is also formed on the first gate structure, and the first conductive structure has a top surface lower than the first protection layer. | 2021-10-28 |
20210336032 | QUBIT ARRAY REPARATION - A qubit array reparation system includes a reservoir of ultra-cold particle, a detector that determines whether or not qubit sites of a qubit array include respective qubit particles, and a transport system for transporting an ultra-cold particle to a first qubit array site that has been determined by the probe system to not include a qubit particle so that the ultra-cold particle can serve as a qubit particle for the first qubit array site. A qubit array reparation process includes maintaining a reservoir of ultra-cold particles, determining whether or not qubit-array sites contain respective qubit particles, each qubit particle having a respective superposition state, and, in response to a determination that a first qubit site does not contain a respective qubit particle, transporting an ultracold particle to the first qubit site to serve as a qubit particle contained by the first qubit site. | 2021-10-28 |
20210336033 | Gate Patterning Process for Multi-Gate Devices - A method includes providing first and second channel layers in a p-type region and an n-type region respectively, forming a gate dielectric layer around the first and second channel layers, and forming a sacrificial layer around the gate dielectric layer. The sacrificial layer merges in space between the first channel layers and between the second channel layers. The method further includes etching the sacrificial layer such that only portions of the sacrificial layer in the space between the first channel layers and between the second channel layers remain, forming a mask covering the p-type region and exposing the n-type region, removing the sacrificial layer from the n-type region, removing the mask, and forming an n-type work function metal layer around the gate dielectric layer in the n-type region and over the gate dielectric layer and the sacrificial layer in the p-type region. | 2021-10-28 |
20210336034 | Inner Spacer Features for Multi-Gate Transistors - A semiconductor device according to the present disclosure includes a channel member including a first connection portion, a second connection portion and a channel portion disposed between the first connection portion and the second connection portion, a first inner spacer feature disposed over and in contact with the first connection portion, a second inner spacer feature disposed under and in contact with the first connection portion, and a gate structure wrapping around the channel portion of the channel member. The channel member further includes a first ridge on a top surface of the channel member and disposed at an interface between the channel portion and the first connection portion. The first ridge partially extends between the first inner spacer feature and the gate structure. | 2021-10-28 |
20210336035 | Vertical Transport FET with Bottom Source and Drain Extensions - VTFET devices with bottom source and drain extensions are provided. In one aspect, a method of forming a VTFET device includes: patterning vertical fin channels in a substrate; forming sidewall spacers along the vertical fin channels having a liner and a spacer layer; forming recesses at a base of the vertical fin channels; indenting the liner; annealing the substrate under conditions sufficient to reshape the recesses; forming bottom source and drains in the recesses; forming bottom source and drain extensions in the substrate adjacent to the bottom source and drains; removing the sidewall spacers; forming bottom spacers on the bottom source and drains; forming gate stacks over the bottom spacers alongside the vertical fin channels; forming top spacers over the gate stacks; and forming top source and drains at tops of the vertical fin channels. A VTFET device by the method having bottom source and drain extensions is also provided. | 2021-10-28 |
20210336036 | METHOD FOR MANUFACTURING A TOP EMISSION INDIUM GALLIUM ZINC OXIDE THIN FILM TRANSISTOR DEVICE - The present invention discloses a method for manufacturing a top emission indium gallium zinc oxide thin film transistor device, includes a first lithographing step, a second lithographing step, a gate insulation layer forming step, a third lithographing step, a source via hole forming step, an indium gallium zinc oxide active layer exposing step, a source/drain forming step, a planarization layer forming step, a fourth lithographing step, a fifth lithographing step, and a sixth lithographing step. The polyimide electrode barrier spacer is used to manufacture the gate electrode and the source/drain. The polyimide electrode barrier spacers can directly form the source/drain and the gate electrode such that three masks are reduced to be one mask. Moreover, PI can increase density of current of a channel. Accordingly the manufacturing method is simplified and production rate thereof is improved. | 2021-10-28 |
20210336037 | METHOD OF MANUFACTURING DISPLAY PANEL - The disclosure provides a method of manufacturing a display panel, including: sequentially forming a buffer layer, an oxide semiconductor layer, and a photoresist layer on a substrate; removing the photoresist layer corresponding to a gate defining region to obtain a photoresist section; forming a first metal layer on the photoresist layer and the oxide semiconductor layer which is not covered by the photoresist layer; and peeling off the photoresist section to remove the first metal layer on the photoresist section, wherein the first metal layer which corresponds to the gate defining region remains to obtain a gate. | 2021-10-28 |
20210336038 | TRANSISTOR HAVING IN-SITU DOPED NANOSHEETS WITH GRADIENT DOPED CHANNEL REGIONS - Embodiments of the invention are directed to a method of performing fabrication operations to form a transistor. The fabrication operations include forming a nanosheet having a first nanosheet sidewall and a second nanosheet sidewall. The nanosheet is communicatively coupled to a source region at the first nanosheet sidewall. The nanosheet is communicatively coupled to a drain region at the second nanosheet sidewall. The nanosheet further includes a source-side nanosheet region that includes the first nanosheet sidewall. The nanosheet further includes a drain-side nanosheet region that includes the second nanosheet sidewall. Dopants are provided in the source-side nanosheet region using an in-situ doping process, wherein a doping concentration in the source-side nanosheet region is greater than a doping concentration of the drain-side nanosheet region. | 2021-10-28 |
20210336039 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Reliability and performance of a semiconductor device are improved. First, a first mask pattern is formed on the semiconductor substrate in each of first to third regions. Next, a second mask pattern made of a material that is different from a material configuring the first mask pattern is formed on a side surface of the first mask pattern and on the semiconductor substrate in each of the first to third regions. Next, by an anisotropic etching process performed to the semiconductor substrate, a plurality of fins protruding from the recessed upper surface of the semiconductor substrate are formed. In the manner, fins each having a different structure from that of a fin in the first region can be formed in the second and third regions. | 2021-10-28 |
20210336040 | MANUFACTURING METHOD OF TFT SUBSTRATE AND TFT SUBSTRATE - A TFT substrate and a manufacturing method thereof are provided. In the manufacturing method, a metal oxide semiconductor layer is irradiated with UV light by using a gate as a shielding layer, such that a portion of the metal oxide semiconductor layer irradiated by the UV light is conductorized to form a source, a drain, and a pixel electrode, and a portion of the metal oxide semiconductor layer shielded by the gate still retains semiconductor properties to form a semiconductor channel. The invention achieves the alignment of the source and the drain with the gate by processes of self-alignment of the gate and conductorization of the metal oxide semiconductor layer, and can effectively control an overlapping region of the source and drain and the gate. Thereby, the parasitic capacitance is reduced, and the display quality is improved. Also, the manufacturing method is simple, and the production efficiency is improved. | 2021-10-28 |
20210336041 | SEMICONDUCTOR CONTACT STRUCTURES - A semiconductor contact structure including a two-dimensional electron gas (2DEG) between a first and a second semiconductor layer and a silicon implant extending into at least a part of the first semiconductor layer and into at least a part of the second semiconductor layer and connected to the 2DEG along an interface between the 2DEG and the silicon implant, wherein the interface has a nonlinear shape. The structure further includes a contact connected to the 2DEG via the silicon implant. | 2021-10-28 |
20210336042 | HIGH ELECTRON MOBILITY TRANSISTOR - A high electron mobility transistor for analog applications comprising: a substrate; an epitaxial III-N semiconductor layer stack on top of said substrate, said epitaxial III-N semiconductor layer stack comprising: a first active III-N layer; and a second active III-N layer comprising a recess; with a two dimensional Electron Gas in between III-N; a gate on top of said epitaxial III-N semiconductor layer stack; and a passivation stack between said epitaxial III-N semiconductor layer stack and said gate, wherein said passivation stack comprises an electron accepting dielectric layer adapted to deplete said two dimensional Electron Gas when said gate is not biased; wherein said electron accepting dielectric layer extends in said recess and comprises magnesium nitride doped with silicon and/or aluminum. | 2021-10-28 |
20210336043 | GROUP III NITRIDE DEVICE AND METHOD OF FABRICATING A GROUP III NITRIDE-BASED DEVICE - In an embodiment, a Group III nitride-based transistor device includes a first passivation layer arranged on a first major surface of a Group III nitride-based layer, a second passivation layer arranged on the first passivation layer, a source ohmic contact, a drain ohmic contact and a gate positioned on the first major surface of a Group III nitride-based layer, and a field plate, the field plate being laterally arranged between and spaced apart from the gate and the drain ohmic contact. | 2021-10-28 |
20210336044 | HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; removing the hard mask to form a first recess for exposing the barrier layer; removing the hard mask adjacent to the first recess to form a second recess; and forming a p-type semiconductor layer in the first recess and the second recess. | 2021-10-28 |
20210336045 | HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - Provided are a high electron mobility transistor and a method of manufacturing the high electron mobility transistor. The high electron mobility transistor includes a gate electrode provided on a depletion forming layer. The gate electrode includes a first gate electrode configured to form an ohmic contact with the depletion forming layer, and a second gate electrode configured to form a Schottky contact with the depletion forming layer. | 2021-10-28 |
20210336046 | WRAP-AROUND BOTTOM CONTACT FOR BOTTOM SOURCE/DRAIN - A method of forming a vertical transport fin field effect transistor device is provided. The method includes replacing a portion of a sacrificial exclusion layer between one or more vertical fins and a substrate with a temporary inner spacer. The method further includes removing a portion of a fin layer and the sacrificial exclusion layer between the one or more vertical fins and the substrate, and forming a bottom source/drain on the temporary inner spacer and between the one or more vertical fins and the substrate. The method further includes replacing a portion of the bottom source/drain with a temporary gap filler, and replacing the temporary gap filler and temporary inner spacer with a wrap-around source/drain contact having an L-shaped cross-section. | 2021-10-28 |
20210336047 | MONOLITHIC CHARGE COUPLED FIELD EFFECT RECTIFIER EMBEDDED IN A CHARGE COUPLED FIELD EFFECT TRANSISTOR - An integrated circuit includes a MOSFET device and a monolithic diode device, wherein the monolithic diode device is electrically connected in parallel with a body diode of the MOSFET device. The monolithic diode device is configured so that a forward voltage drop Vf | 2021-10-28 |
20210336048 | Semiconductor Device and Method - A semiconductor device including a source/drain region having a V-shaped bottom surface and extending below gate spacers adjacent a gate stack and a method of forming the same are disclosed. In an embodiment, a method includes forming a gate stack over a fin; forming a gate spacer on a sidewall of the gate stack; etching the fin with a first anisotropic etch process to form a first recess adjacent the gate spacer; etching the fin with a second etch process using etchants different from the first etch process to remove an etching residue from the first recess; etching surfaces of the first recess with a third anisotropic etch process using etchants different from the first etch process to form a second recess extending below the gate spacer and having a V-shaped bottom surface; and epitaxially forming a source/drain region in the second recess. | 2021-10-28 |
20210336049 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor layer having a first main surface on one side and a second main surface on the other side, a unit cell including a diode region of a first conductivity type formed in a surface layer portion of the first main surface of the semiconductor layer, a well region of a second conductivity type formed in the surface layer portion of the first main surface of the semiconductor layer along a peripheral edge of the diode region, and a first conductivity type region formed in a surface layer portion of the well region, a gate electrode layer facing the well region and the first conductivity type region through a gate insulating layer and a first main surface electrode covering the diode region and the first conductivity type region on the first main surface of the semiconductor layer, and forming a Schottky junction with the diode region and an ohmic junction with the first conductivity type region. | 2021-10-28 |
20210336050 | Solid-State Device with Optical Waveguide as Floating Gate Electrode - A semiconductor device includes a floating gate that can be charged in a nonvolatile manner. The floating gate is also structured as an optical waveguide, and maybe optically coupled to a photonic circuit, such as an interferometer. | 2021-10-28 |
20210336051 | SMALL PITCH SUPER JUNCTION MOSFET STRUCTURE AND METHOD - The present invention provides semiconductor devices with super junction drift regions that are capable of blocking voltage. A super junction drift region is an epitaxial semiconductor layer located between a top electrode and a bottom electrode of the semiconductor device. The super junction drift region includes a plurality of pillars having P type conductivity, formed in the super junction drift region, which are surrounded by an N type material of the super junction drift region. | 2021-10-28 |
20210336052 | POWER MOS DEVICE WITH LOW GATE CHARGE AND A METHOD FOR MANUFACTURING THE SAME - A power MOS device with low gate charge and a method for manufacturing the same. The device includes an M-shaped gate structure, which reduces the overlapped area between control gate electrode and split gate electrode. A low-k material is introduced to reduce dielectric constant of the isolation medium material. The combination of the M-shaped gate structure and low-k material can reduce parasitic capacitance Cgs of the device, thereby increasing switching speed and reducing switching losses. | 2021-10-28 |
20210336053 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device structure can include: (i) a first semiconductor layer having dopants of a first type; (ii) a second semiconductor layer having the dopants of the first type on the first semiconductor layer, where the second semiconductor layer is lightly-doped relative to the first semiconductor layer; (iii) first and second column regions spaced from each other in the second semiconductor layer, where the second column region is arranged between two of the first column regions; and (iv) first and second first sub-column regions laterally arranged in the second column region, where a doping concentration of the first sub-column region decreases in a direction from the first column region to the second sub-column region, and where a doping concentration of the second sub-column region decreases in a direction from the first column region to the first sub-column region. | 2021-10-28 |
20210336054 | SWITCHING LDMOS DEVICE AND METHOD FOR MAKING THE SAME - A switching LDMOS device is formed first well in a semiconductor substrate that includes an LDD region and a first body doped region; a first heavily doped region serving as a source region is provided in the LDD region, and a second heavily doped region serving as a drain region is provided in the first body doped region; a channel of the switching LDMOS device is formed at a surface layer of the semiconductor substrate between the LDD region and the body doped region and below the gate structure; and one side of the LDD region and one side of the body doped region which are away from the gate structure both are provided with a field oxide or STI, and one side of the field oxide or STI is in contact with the first heavily doped region or the second heavily doped region. | 2021-10-28 |
20210336055 | SEMICONDUCTOR DEVICE, METHOD OF FABRICATING THE SAME, AND ELECTRONIC APPARATUS INCLUDING THE SAME - A semiconductor device, including: a substrate; a first source/drain layer, a channel layer, and a second source/drain layer sequentially stacked on the substrate and adjacent to each other, and a gate stack formed around an outer circumference of the channel layer; wherein at least one interface structure is formed in at least one of the first source/drain layer and the second source/drain layer, the conduction band energy levels at both sides of the interface structure are different and/or the valence band energy levels are different. | 2021-10-28 |
20210336056 | Field-Effect Transistor Devices with Sidewall Implant Under Bottom Dielectric Isolation - FET devices with bottom dielectric isolation and sidewall implants in the source and drain regions to prevent epitaxial growth below the bottom dielectric isolation are provided. In one aspect, a semiconductor FET device includes: a device stack(s) disposed on a substrate, wherein the device stack(s) includes active layers oriented vertically over a bottom dielectric isolation layer; STI regions embedded in the substrate at a base of the device stack(s), wherein a top surface of the STI regions is recessed below a top surface of the substrate exposing substrate sidewalls under the bottom dielectric isolation region, wherein the sidewalls of the substrate include implanted ions; source and drains on opposite sides of the active layers; and gates surrounding a portion of each of the active layers, wherein the gates are offset from the source and drains by inner spacers. A method of forming a semiconductor FET device is also provided. | 2021-10-28 |
20210336057 | STRAINED SEMICONDUCTOR MONOCRYSTALLINE NANOSTRUCTURE - A semiconductor structure comprises a semiconductor substrate having a top layer and one or more semiconductor monocrystalline nanostructures. Each nanostructure has a first and a second extremity defining an axis parallel to the top surface of the semiconductor substrate and separated therefrom by a distance, and a source structure epitaxially grown on the first extremity and a drain structure epitaxially grown on the second extremity. The source and drain structures are made of a p-doped (or alternatively n-doped) semiconductor monocrystalline material having a smaller (or alternatively larger) unstrained lattice constant than the unstrained lattice constant of the semiconductor monocrystalline material making the semiconductor monocrystalline nanostructure on which they are grown, thereby creating compressive (or alternatively tensile) strain in that semiconductor monocrystalline nanostructure. | 2021-10-28 |
20210336058 | EPITAXIAL STRUCTURE HAVING SUPER-LATTICE LAMINATES - An epitaxial structure includes a substrate, a lower super-lattice laminate, a middle super-lattice laminate, an upper super-lattice laminate and a channel layer. The lower super-lattice laminate includes a plurality of first lower film layers and a plurality of second lower film layers stacked alternately. The first lower film layer includes aluminum nitride. The second lower film layer includes aluminum gallium nitride. The middle super-lattice laminate includes a plurality of first middle film layers and a plurality of second middle film layers stacked alternately. The first middle film layer includes aluminum nitride. The second middle film layer includes gallium nitride doped with a doping material. The upper super-lattice laminate includes a plurality of first upper film layers and a plurality of second upper film layers stacked alternately. The first upper film layer includes gallium nitride doped with the doping material. The second upper film layer includes gallium nitride. | 2021-10-28 |
20210336059 | OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR - An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor. | 2021-10-28 |
20210336060 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device which includes a thin film transistor having an oxide semiconductor layer and excellent electrical characteristics is provided. Further, a method for manufacturing a semiconductor device in which plural kinds of thin film transistors of different structures are foamed over one substrate to form plural kinds of circuits and in which the number of steps is not greatly increased is provided. After a metal thin film is formed over an insulating surface, an oxide semiconductor layer is formed thereover. Then, oxidation treatment such as heat treatment is performed to oxidize the metal thin film partly or entirely. Further, structures of thin film transistors are different between a circuit in which emphasis is placed on the speed of operation, such as a logic circuit, and a matrix circuit. | 2021-10-28 |
20210336061 | DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - A display apparatus includes: a substrate on which a first area, a second area spaced apart from the first area, and a bending area between a first area and a second area and bent along a bending axis are defined; a first thin-film transistor (“TFT”) and a second TFT; and a first conductive layer and a second conductive layer. The first TFT includes: a first active layer including polycrystalline silicon; a first gate electrode; and a first electrode disposed at a level which is the same as a level of the first conductive layer, and the second TFT includes: a second active layer including an oxide semiconductor; a second gate electrode; and a second electrode disposed at a level which is the same as a level of the second conductive layer. | 2021-10-28 |
20210336062 | THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF - The present disclosure provides a thin film transistor and a manufacturing method thereof. The thin film transistor includes a substrate, a light shielding layer, an intermediate buffer layer, and a buffer layer, wherein the light shielding layer is formed on the substrate, the buffer layer is located above the substrate and the light shielding layer, the intermediate buffer layer is formed between the buffer layer and the light shielding layer, and the intermediate buffer layer is made of ceramic material. | 2021-10-28 |
20210336063 | Semiconductor Device and Method - In an embodiment, a device includes: a first interconnect structure including metallization patterns; a second interconnect structure including a power rail; a device layer between the first interconnect structure and the second interconnect structure, the device layer including a first transistor, the first transistor including an epitaxial source/drain region; and a conductive via extending through the device layer, the conductive via connecting the power rail to the metallization patterns, the conductive via contacting the epitaxial source/drain region. | 2021-10-28 |
20210336064 | THIN FILM TRANSISTOR, DISPLAY PANEL, AND METHOD OF FABRICATING THIN FILM TRANSISTOR - A thin film transistor includes a base substrate and an active layer on the base substrate. The active layer includes a source electrode contact part, a drain electrode contact part, and a channel part between the source electrode contact part and the drain electrode contact part. The source electrode contact part and the drain electrode contact part are lightly doped parts. The source electrode contact part includes a first barrier part. The drain electrode contact part includes a second barrier part. Each of the first barrier part and the second barrier part includes a semiconductor material having an acceptor defect or an acceptor-like defect. Each of the source electrode contact part and the drain electrode contact part includes a semiconductor material having a donor defect or a donor-like defect. The first barrier part and the second barrier part are respectively on two sides of the channel part. | 2021-10-28 |
20210336065 | ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE - The embodiments of the present disclosure provide an array substrate and a method for manufacturing the same, and a display device. The array substrate includes a substrate, wherein the substrate has a display region and a peripheral region surrounding the display region, the display region has a plurality of pixels arranged in an array, and each of the plurality of pixels includes a light transmission region and a light shielding region, and a light shielding block covering at least a part of the light transmission region of at least one pixel close to the peripheral region of the plurality of pixels. | 2021-10-28 |
20210336066 | THIN FILM TRANSISTOR, METHOD FOR FABRICATING THE SAME, METHOD FOR CONTROLLING THE SAME, DISPLAY PANEL AND DISPLAY DEVICE - This disclosure relates to the field of display technologies, and discloses a thin film transistor, a method for fabricating the same, a method for controlling the same, a display panel, and a display device. The thin film transistor includes: a base substrate, a semiconductor active layer on one side of the base substrate, a source electrically connected with one end of the semiconductor active layer, a drain electrically connected with the other end of the semiconductor active layer, a gate insulated from the semiconductor active layer, the source, and the drain, and a modulation electrode insulated from the semiconductor active layer, the gate, the source, and the drain. The modulation electrode is proximate to the drain, and an orthographic projection of the modulation electrode on the base substrate overlaps with an orthographic projection of the semiconductor active layer on the base substrate | 2021-10-28 |
20210336067 | SEMICONDUCTOR COMPONENT AND METHOD OF FABRICATING THEREOF - A semiconductor component includes a substrate; a polysilicon layer formed on the substrate, and the polysilicon layer includes a source, a channel, and a drain, and the source and the drain are formed at two sides of the polysilicon layer, and the channel is formed between the source and the drain; a gate insulating layer formed on the polysilicon layer; a gate formed on the gate insulating layer and formed directly above the channel; an interlayer dielectric layer formed above the gate and covering the gate and implanted with hydrogen atoms by ion implantation and rapidly annealed at high temperature to form a hydrogenated interlayer dielectric layer; a metal conducting wire passing through an upper surface of the hydrogenated interlayer dielectric layer and contacting with the source or the drain; and a passivation layer covering the hydrogenated interlayer dielectric layer. A method of fabricating the semiconductor component is also provided. | 2021-10-28 |
20210336068 | THIN FILM TRANSISTOR, METHOD OF FABRICATING THIN FILM TRANSISTOR, AND DISPLAY APPARATUS HAVING THIN FILM TRANSISTOR - A thin film transistor is provided. The thin film transistor includes a base substrate; a first target layer on the base substrate; a first insulating layer on a side of the first target layer away from the base substrate; an intermediate layer on a side of the first insulating layer away from the first target layer; a second insulating layer on a side of the intermediate layer away from the first insulating layer; and a second target layer on a side of the second insulating layer away from the intermediate layer. The first target layer is electrically connected to the second target layer. The intermediate layer is one of a gate electrode and an active layer, and the first target layer and the second target layer together constitute another one of the gate electrode and the active layer. | 2021-10-28 |
20210336069 | VARIABLE CAPACITOR - A variable capacitor includes a semiconductor substrate, a well region, and a gate electrode. The well region is disposed in the semiconductor substrate. The gate electrode is disposed on the semiconductor substrate, and the gate electrode overlaps a part of the well region in a thickness direction of the semiconductor substrate. A conductivity type of the gate electrode is complementary to a conductivity type of the well region for improving electrical performance of the variable capacitor. | 2021-10-28 |
20210336070 | METHODS OF FORMING A COLORED CONDUCTIVE RIBBON FOR INTEGRATION IN A SOLAR MODULE - The present disclosure describes methods of forming a colored conductive ribbon for a solar module which includes combining a conductive ribbon with a channeled ribbon holder, applying a color coating to at least the conductive ribbon within the channel, curing the color coating on the conductive ribbon, and separating the conductive ribbon from the channeled holder. | 2021-10-28 |
20210336071 | PHOTOSENSITIVE COMPONENT, DETECTION SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME - The present disclosure relates to a photosensitive component, a detection substrate and a method for manufacturing the detection substrate. The photosensitive component includes: a first electrode layer, a photoelectric conversion layer, a second electrode layer, an insulating layer and a reflective layer. The photoelectric conversion layer is located on the first electrode layer. The second electrode layer is located on a surface of the photoelectric conversion layer away from the first electrode layer. The insulating layer covers side surfaces of the photoelectric conversion layer and at least a part of a surface of the second electrode layer away from the photoelectric conversion layer, and the insulating layer includes a transparent material. The reflective layer covers the insulating layer, and the reflective layer is configured to reflect at least a part of light entering the insulating layer to the side surfaces of the photoelectric conversion layer. | 2021-10-28 |
20210336072 | ARRANGEMENT, METHODS FOR PRODUCING AN ARRANGEMENT AND OPTOELECTRONIC DEVICE - An arrangement is disclosed. The arrangement comprises at least one semiconductor structure configured to convert a primary radiation into a secondary radiation; an encapsulation layer covering the at least one semiconductor structure; and at least one reflective layer arranged on the encapsulation layer. The semiconductor structure is arranged in a center of the arrangement, and a lateral extent of the arrangement is chosen such that an optically resonant condition is fulfilled for a wavelength of the secondary radiation in the encapsulation layer. Methods for producing an arrangement and an optoelectronic device are also disclosed. | 2021-10-28 |
20210336073 | METHOD OF PATTERNING QUANTUM DOT LIGHT EMITTING DEVICE AND QUANTUM DOT LIGHT EMITTING DEVICE - A method of patterning a quantum dot light emitting device and a quantum dot light emitting device are provided. A quantum dot material is printed by providing a printing mesh having a predetermined pattern, which avoids issues such as slow speed and complex process brought by printing, transfer, and the like processes in a conventional method of patterning a quantum dot light emitting device in the prior art. This can reduce printing process and save printing time. | 2021-10-28 |
20210336074 | METHOD OF FABRICATING A MICRO LIGHT EMITTING DIODE DISPLAY SUBSTRATE, AND MICRO LIGHT EMITTING DIODE DISPLAY SUBSTRATE - A method of fabricating a micro light emitting diode (micro LED) display substrate. The method includes forming a definition layer on a growth substrate for defining a plurality of subpixel areas, the definition layer formed to include a plurality of lateral walls, each of the plurality of subpixel areas surrounded by a respective one of the plurality of lateral walls; forming a plurality of semiconductor layers of a plurality of micro LEDs on the growth substrate in the plurality of subpixel areas defined by the definition layer; transferring the plurality of semiconductor layers of the plurality of micro LEDs on the growth substrate onto a target substrate; and removing the growth substrate from the plurality of semiconductor layers of the plurality of micro LEDs transferred onto the target substrate. | 2021-10-28 |
20210336075 | MICRO LIGHT EMITTING DIODE APPARATUS AND FABRICATING METHOD THEREOF - A method of fabricating a micro light emitting diode (micro LED) apparatus includes forming a first substrate including a first silicon layer, a second silicon layer, and a silicon oxide layer sandwiched between the first silicon layer and the second silicon layer; forming a plurality of micro LEDs on a side of the second silicon layer distal to the silicon oxide layer; bonding the first substrate having the plurality of micro LEDs with a second substrate; and removing the silicon oxide layer and the first silicon layer. | 2021-10-28 |
20210336076 | METHOD OF FABRICATING LIGHT-EMITTING DIODE DISPLAY PANEL - The present application provides a method of fabricating a light-emitting diode (LED) display panel, including the following steps: forming an LED substrate including a first substrate, an LED chip disposed on the first substrate, and a first electrode disposed on the LED chip; forming a driving substrate including a second substrate and a second electrode disposed on the second substrate; activating surfaces of the first electrode and the second electrode; aligning and pre-bonding the first electrode with the second electrode; and bonding the first electrode and the second electrode. | 2021-10-28 |
20210336077 | QUANTUM ROD LIGHT EMITTING DIODE DEVICE - The present invention discloses a quantum rod light emitting diode device, including a substrate, and a cathode, an electron functional layer, a light emitting layer, a hole functional layer and an anode sequentially stacked on the substrate. The light emitting layer includes quantum rods disposed therein. The quantum rods are oriented along a same direction. The light emitting layer of the quantum rod light emitting diode device of the present invention include the oriented quantum rods to change incident light into polarized light, which enhances transmittance of polarized light. | 2021-10-28 |
20210336078 | MICRO-LED CHIP AND MANUFACTURING METHOD THEREOF, AND DISPLAY PANEL - The present invention provides a micro-LED chip, a manufacturing method of the micro-LED chip, and a display panel. The micro-LED chip includes a plurality of sub-chips connected in series. The first sub-chip and the last sub-chip are connected to a first electrode and a second electrode, respectively. Accordingly, a voltage across the micro-LED chip is increased, power consumption of a driving thin film transistor (TFT) is reduced, and a high power consumption problem of driving TFTs in conventional micro-LED displays is improved. | 2021-10-28 |
20210336079 | SEMICONDUCTOR DEVICE - The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having a first side and a second side opposite to the first side; a first optical element at the first side of the substrate; and a semiconductor stack on the substrate. The semiconductor stack includes a first reflective structure; a second reflective structure; a cavity region between the first reflective structure and the second reflective structure and having a first surface and a second surface opposite to the first surface; and a confinement layer in one of the second reflective structure and the first reflective structure. The semiconductor device further includes a first electrode and a second electrode on the first surface. | 2021-10-28 |
20210336080 | LIGHT-EMITTING DIODE AND MANUFACTURING METHOD THEREFOR - A light-emitting diode includes a substrate, a distributed Bragg reflector (DBR) structure and a semiconductor layered structure. The DBR structure is disposed on the substrate. The semiconductor layered structure is disposed on the DBR structure opposite to the substrate, and is configured to emit a light having a first wavelength. The DBR structure has a reflectance of not greater than 30% for the light having the first wavelength, and a reflectance of not smaller than 50% for a laser beam having a second wavelength that is different from the first wavelength. | 2021-10-28 |
20210336081 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light-emitting device includes: a substrate, an epitaxial layer structure disposed on the substrate, a first current blocking layer disposed on the epitaxial layer structure, a second current blocking layer disposed on the epitaxial layer structure, a current spreading layer disposed on the epitaxial layer structure and covering the first current blocking layer; a first electrode disposed on a side of the current spreading layer facing away from the epitaxial layer structure, and a second electrode disposed on the epitaxial layer structure and covering the second current blocking layer. The first current blocking layer includes a first main blocking portion and a first extended blocking portion. The second current blocking layer includes a second main blocking portion and a second extended blocking portion. The second extended blocking portion includes spacings. The first extended blocking portion is formed with convex structures. The convex structures are aligned with the spacings. | 2021-10-28 |
20210336082 | SOLID-STATE LIGHT-EMITTING DEVICE - A solid-state light-emitting device includes: a substrate; an epitaxial layer structure on the substrate and including a first-type area and a second-type area; a first current blocking layer disposed on the epitaxial layer structure and located in the first-type area; a current spreading layer covering the first current blocking layer so that the first current blocking layer is located between the current spreading layer and the epitaxial layer structure; a first adhesive reinforcing layer disposed on a side of the current spreading layer away from the first current blocking layer and including a plurality of first through holes; a first electrode disposed on a side of the first adhesion reinforcing layer away from the current spreading layer and filled into the plurality of first through holes to electrically contact with the current spreading layer. Therefore, the light-emitting efficiency of the solid-state light-emitting device is improved. | 2021-10-28 |
20210336083 | PIXEL OF MICRO DISPLAY HAVING INCLINED SIDE - Disclosed is a unit pixel of a micro-display capable of minimizing light emitted through a side surface. A side surface of the unit pixel having a vertically stacked pixel structure is etched and has inclination angle. Light directed toward the side surface is reflected by the side surface inclined at an angle, and the light is emitted in a direction perpendicular to the growth surface or the surface of the growth substrate. | 2021-10-28 |
20210336084 | DISPLAY DEVICE - A display device with improved light-emitting efficiency is disclosed. The display device includes a plurality of pixels, a light emitting device provided in each of the pixels, the light emitting device having first and second surfaces which are opposite to each other, first and second electrodes electrically and respectively connected to the first and second surfaces of the light emitting device, and a metal oxide pattern interposed between the second surface of the light emitting device and the second electrode. The metal oxide pattern includes first and second regions. The first region encloses the second region, and the second region has a contact hole exposing at least a portion of the second surface. The second electrode is coupled to the second surface through the contact hole, and the first and second regions have crystalline phases different from each other. | 2021-10-28 |
20210336085 | DISPLAY DEVICE AND METHOD OF MANUFACTURING LIGHT EMITTING DEVICE - Disclosed are a display device and a manufacturing method thereof. The display device includes a plurality of pixels, a light emitting device provided in each of the plurality of pixels, the light emitting device having a first surface and a second surface, which are opposite to each other, a first electrode electrically connected to the first surface of the light emitting device, a second electrode electrically connected to the second surface of the light emitting device, and a metal oxide pattern interposed between the second surface of the light emitting device and the second electrode. The metal oxide pattern is provided to cover a portion of the second surface and to expose a remaining portion of the second surface. The second electrode is electrically connected to the exposed remaining portion of the second surface, and the metal oxide pattern includes single-crystalline or polycrystalline alumina. | 2021-10-28 |
20210336086 | SURFACE LIGHT SOURCE CHIP AND LIGHT EMITTING DIODE THEREOF - A surface light source and a light emitting diode thereof are provided. The surface light source chip includes a sapphire substrate, an N-type GaN buffer layer under the sapphire substrate, and a chip positive electrode area and a chip negative electrode area formed under the N-type GaN buffer layer, wherein the chip positive electrode area includes an N-type GaN layer, a multiple quantum well (MQW) emitting layer, an omni-directional reflector (ODR) layer and a chip positive electrode from top to bottom sequentially, and the chip negative electrode area includes a chip negative electrode. The light emitting diode includes the surface light source chips mentioned above. | 2021-10-28 |
20210336087 | SEMICONDUCTOR LIGHT-EMITTING ELEMENT AND METHOD OF MANUFACTURING SEMICONDUCTOR LIGHT-EMITTING ELEMENT - A semiconductor light-emitting element includes: an n-type clad layer; an active layer; a p-type clad layer; a first p-type contact layer; a second p-type contact layer; and a p-side electrode. The AlN ratio of the p-type clad layer is 50% or higher. The first p-type contact layer has an AlN ratio of 5% or lower, has a p-type dopant concentration equal to or higher than 8×10 | 2021-10-28 |
20210336088 | PIXEL AND DISPLAY DEVICE INCLUDING THE SAME - A pixel includes a first electrode and a second electrode spaced from each other in a first direction on a substrate; a plurality of light emitting elements between the first electrode and the second electrode; an intermediate pattern located between the first electrode and the second electrode in the first direction and located between the substrate and the plurality of light emitting elements in a thickness direction of the substrate; a first contact electrode electrically connecting one end portion of each of the light emitting elements and the first electrode; and a second contact electrode electrically connecting an other end portion of each of the light emitting elements and the second electrode. | 2021-10-28 |
20210336089 | Semiconductor Light Emitting Chip and Its Manufacturing Method - A semiconductor light emitting chip includes a substrate and an N-type semiconductor layer sequentially developed from the substrate, an active region, a P-type semiconductor layer, a reflective layer, at least two insulating layers, an anti-diffusion layer and an electrode set. One of the insulating layers is extended to surround the inner peripheral portion of the reflective layer, and another the insulating layer is extended to surround the outer peripheral portion of the reflective layer, such that the insulating layer isolates the anti-diffusion layer from the P-type semiconductor layer. The electrode set includes an N-type electrode and a P-type electrode, wherein the N-type electrode is electrically connected to the N-type semiconductor layer, and the P-type electrode is electrically connected to the P-type semiconductor layer. | 2021-10-28 |
20210336090 | LIGHT-EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - A light-emitting device includes a semiconductor stack including a first semiconductor layer, a second semiconductor layer and an active area between the first semiconductor layer and the second semiconductor layer, wherein the first semiconductor layer including an upper surface; an exposed region formed in the semiconductor stack to expose the upper surface; a first protective layer covering the exposed region and a portion of the second semiconductor layer, wherein the first protective layer includes a first part with a first thickness formed on the upper surface and a second part with a second thickness formed on the second semiconductor layer, the first thickness is smaller than the second thickness; a first reflective structure formed on the second semiconductor layer and including one or multiple openings; and a second reflective structure formed on the first reflective structure and electrically connected to the second semiconductor layer through the one or multiple openings. | 2021-10-28 |
20210336091 | OPTICALLY TRANSPARENT ADHESION LAYER TO CONNECT NOBLE METALS TO OXIDES - A reflective layer for use in lighting devices and methods of forming the reflective layer are provided. The reflective layer may include a dielectric layer including one or more insulating materials. An intermediate layer may be formed on the dielectric layer. The intermediate layer may include one or more materials having a higher enthalpy of reaction than the one or more insulating materials. Because of the higher enthalpy of reaction, atoms of the one or more materials in the intermediate layer may form bonds with atoms of the one or more insulating materials. A metal layer may be formed on the intermediate layer to reflect light emitted from an active region of a light emitting diode (LED). | 2021-10-28 |
20210336092 | LED WITH STACKED STRUCTURE - The present disclosure relates to an LED board with a stacked structure, which includes: a metal plate; a printed circuit board attached onto an upper side of the metal plate and having at least one through-hole exposing a part of the upper side of the metal plate; at least one LED chip mounted on the metal plate exposed through the through-hole; a stacked portion having a phosphor-accommodating hole larger than the through-hole formed to include the LED chip and coupled onto the printed circuit board; and a phosphor filled in the phosphor-accommodating hole to cover the LED chip. | 2021-10-28 |
20210336093 | LIGHT-EMITTING DIODE CHIP WITH ELECTRICAL OVERSTRESS PROTECTION - Solid-state lighting devices including light-emitting diodes (LEDs) and more particularly LED chip structures with electrical overstress protection are disclosed. LED chip structures are disclosed that include built-in electrical overstress protection. An exemplary LED chip may include an active LED structure that is arranged as a primary light-emitting structure and a separate active LED structure that is arranged as an electrical overstress protection structure. The electrical overstress protection structure may be electrically connected in reverse relative to the primary light-emitting structure. In this manner, under normal operating conditions, forward current will flow through the primary light-emitting structure to generate desired light emissions, and during an electrical overstress event, reverse current may flow through the electrical overstress protection structure, thereby protecting the light-emitting structure from damage. | 2021-10-28 |
20210336094 | LIGHT EMITTING DEVICE, RESIN PACKAGE, RESIN-MOLDED BODY, AND METHODS FOR MANUFACTURING LIGHT EMITTING DEVICE, RESIN PACKAGE AND RESIN-MOLDED BODY - A light emitting device includes: a resin package including: a resin part, and a plurality of leads including a first lead and a second lead, wherein the resin package has a concave portion having a bottom face at which a part of an upper surface of the first lead and a part of an upper surface of the second lead are exposed from the resin part; a light emitting element mounted on the bottom face of the concave portion; and a sealing member covering the light emitting element in the concave portion. The plurality of leads comprise a plurality of notch parts including a first notch part on a first side corresponding to a first outer side surface of the resin package and a second notch part on a second side corresponding to a second outer side surface of the resin package. | 2021-10-28 |
20210336095 | MICRO LIGHT EMITTING DIODE DISPLAY PANEL, MICRO LIGHT EMITTING DIODE DISPLAY APPARATUS, AND METHOD OF FABRICATING MICRO LIGHT EMITTING DIODE DISPLAY PANEL - A micro light emitting diode (micro LED) display panel includes a carrier substrate layer; a plurality of vias respectively extending into the carrier substrate layer; a plurality of micro LEDs on the carrier substrate layer; and a wavelength conversion layer including a wavelength conversion material filled in the plurality of vias. | 2021-10-28 |
20210336096 | DISPLAY PANEL AND MANUFACTURING METHOD THEREOF - The present invention discloses a display panel and a manufacturing method thereof. The display panel includes: a substrate; blue light-emitting diodes (LEDs) disposed in an array on the substrate and provided with a gap between two neighboring blue LEDs; a light conversion layer having a plurality of quantum dot photoresist units, wherein each of the plurality of quantum dot photoresist units is correspondingly disposed on each of the blue LEDs; and a scattering particle layer disposed in a same layer as the light conversion layer and having a plurality of scattering particle units, wherein each of the plurality of scattering particle units is correspondingly disposed on each of the blue LEDs. | 2021-10-28 |
20210336097 | VERTICAL BLUE LIGHT EMITTING DIODE AND METHOD FOR MANUFACTURING SAME - A vertical blue LED includes: a conductive substrate, the conductive substrate including a first surface and a second surface opposite to the first surface a nitride epitaxial layer; a metal reflective layer, positioned on the first surface; a nitride epitaxial layer, positioned on a surface of the metal reflective layer and including a P-type GaN layer, a quantum well layer, a preparation layer, and an N-type GaN layer that are sequentially stacked along a direction perpendicular to the conductive substrate, wherein a thickness of the nitride epitaxial layer is less than a wavelength of blue light; an N-type electrode, positioned on a surface of the N-type GaN layer; and a P-type electrode, positioned on the second surface. | 2021-10-28 |
20210336098 | LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING THE LIGHT-EMITTING DEVICE - A light-emitting device includes a support; a light-emitting element on or above the support; a first wavelength conversion member on or above the light-emitting element, the first wavelength conversion member having an area larger than that of the light-emitting element in a top view; a first light-transmissive member covering a lower surface of an extension region of the first wavelength conversion member an a lateral surface of the light-emitting element; a first light-reflective member on lateral sides of the first wavelength conversion member and the first light-transmissive member; and a second wavelength conversion member disposed on or above the first wavelength conversion member. A thickness of the second wavelength conversion member above a peripheral portion of the first wavelength conversion member is smaller than a thickness of the second wavelength conversion member above a central portion of the first wavelength conversion member. | 2021-10-28 |
20210336099 | MICRO LED DEVICE AND METHOD FOR MANUFACTURING SAME - A micro-LED device of the present disclosure includes a crystal growth substrate ( | 2021-10-28 |
20210336100 | DISPLAY DEVICE AND MANUFACTURING METHOD OF DISPLAY DEVICE - A display device and a manufacturing method of the display device are provided. The display device includes an array substrate and micro light emitting diode devices. A plurality of micro-cavity structures are disposed on surfaces of the micro light emitting diode devices. Through filling the micro-cavity structures by quantum dot film layers disposed on the micro light emitting diode devices, energy transfer effect between the micro light emitting diode devices and the quantum dots is enhanced, thereby reducing light loss in a photoluminescence process and improving a light utilization rate. | 2021-10-28 |
20210336101 | Optoelectronic Device and Method for Manufacturing Optoelectronic Devices - In an embodiment an optoelectronic device includes an optoelectronic component with a first main surface, a second main surface and a plurality of side surfaces interconnecting the first and second main surfaces and a conversion element arranged at the first main surface of the optoelectronic component, wherein the conversion element includes a frame of a reflective material and a conversion material located within the frame, wherein an interface between the frame and the conversion material runs slanted having an angle of smaller than 180° and larger than 90° between the interface and an adjacent side surface of the plurality of side surfaces, and wherein the frame protrudes laterally beyond a light emitting area of the first main surface of the optoelectronic component. | 2021-10-28 |
20210336102 | LIGHT SOURCE MODULE AND BACKLIGHT UNIT HAVING THE SAME - A backlight unit includes one or more light sources operable to emit light and a light guide plate arranged adjacent to the one or more light sources, reflected lights exiting the one or more light sources via the second surfaces and entering the light guide plate. A light source includes a light emitting device having a substrate and a semiconductor stack disposed on the substrate. The reflector is structured and positioned to block light emitted from a first surface of the light emitting device by reflecting the light emitted from the first surface toward second surfaces of the light source. | 2021-10-28 |
20210336103 | LIGHT-EMITTING DEVICES AND METHODS FOR MANUFACTURING THE SAME - A light-emitting device is provided. The light-emitting device includes a first substrate. The light-emitting device also includes a second substrate including a light-shielding structure. The light-emitting device further includes a first light-emitting module and a second light-emitting module being adjacent to each other. The first light-emitting module and the second light-emitting module are disposed between the first substrate and the second substrate. The first light-emitting module and the second light-emitting module are spaced apart by a gap, and the light-shielding structure at least partially covers the gap in a top view direction of the light-emitting device. | 2021-10-28 |
20210336104 | LIGHT SOURCE STRUCTURE, ELECTRONIC DEVICE AND MANUFACTURING METHOD OF LIGHT SOURCE STRUCTURE - A light source structure, an electronic device and a manufacturing method of a light source structure are disclosed. The light source structure includes a light-emitting unit, a printed circuit board and a bonding layer. The light-emitting unit includes a substrate and at least one light-emitting element on the substrate. The printed circuit board includes a first surface, and the light-emitting unit is disposed on the first surface of the printed circuit board via the substrate. The bonding layer is disposed between the substrate and the first surface of the printed circuit board, and for adhesively bonding the substrate and the printed circuit board together. | 2021-10-28 |
20210336105 | DISPLAY PANEL AND METHOD OF MANUFACTURING DISPLAY PANEL - A display panel and a method of manufacturing a display panel are provided. In a solution, a plurality of grooves are formed on at least one metal layer by an etching process, and a connection portion and the at least one metal layer are connected by an adhesive. The adhesive can flow into the grooves during a bonding process to form a plurality of protrusions to fill the grooves, thereby increasing a contact area with the at least one metal layer and increasing bonding strength between the adhesive and the at least one metal layer. It is possible to avoid poor soldering, dark spots, and the like of a light emitting device. | 2021-10-28 |
20210336106 | ARRAY SUBSTRATE AND FABRICATION METHOD THEREOF - An array substrate and a method of fabricating the array substrate are disclosed. The array substrate includes a substrate including a plurality of pixel units arranged in an array. Each of the pixel units has a first electrode and a second electrode, and a first gap is provided between the first electrode and the second electrode. A bonding adhesive is disposed at the first gap. A micro light-emitting diode is disposed on the first electrode, the second electrode, and the bonding adhesive to prevent a failure of the micro light-emitting diode and improve product yield. | 2021-10-28 |
20210336107 | DISPLAY PANEL AND METHOD OF FABRICARING SAME, AND DISPLAY DEVICE - A display panel and a method of fabricating the same, and a display device are provided. The display panel has: a first substrate having a first lead at a first edge of the first substrate and a second lead at a second edge of the first substrate; a second substrate having a third lead at a third edge of the second substrate and a fourth lead at a fourth edge of the second substrate; and connection lines connected the first lead to the fourth lead and connected the second lead to the third lead. | 2021-10-28 |
20210336108 | DISPLAY DEVICE - A display device includes a first electrode disposed on a substrate, a second electrode disposed on the substrate and spaced apart from the first electrode, at least one light-emitting element extending in a direction, disposed between the first electrode and the second electrode, and electrically connected to the first electrode and the second electrode, and an insulating pattern layer disposed on the first electrode and the second electrode, the insulating pattern layer including a fixer disposed on at least part of the at least one light-emitting element, and a barrier surrounding the at least one light-emitting element. | 2021-10-28 |
20210336109 | LIGHT-EMITTING DEVICE - A light-emitting device includes: a substrate; n light-emitting elements (n being a natural number of 2 or more) mounted on the substrate, each comprising a first bonding member electrically connected to a first semiconductor layer, and a second bonding member electrically connected to a second semiconductor layer; and n+1 interconnects provided on the substrate, the n+1 interconnects comprising a first interconnect comprising a first external connection portion, a second interconnect comprising a second external connection portion, and a third interconnect comprising a third external connection portion. In a top-view, the first light-emitting element is located between a first side of the substrate and a second light-emitting element, and the second light-emitting element is located between a first light-emitting element and a second side. | 2021-10-28 |
20210336110 | OPTOELECTRONIC SEMICONDUCTOR DEVICE HAVING A SUPPORT ELEMENT AND AN ELECTRIC CONTACT ELEMENT, AN OPTOELECTRONIC COMPONENT AND A METHOD OF PRODUCING THE OPTOELECTRONIC SEMICONDUCTOR DEVICE - An optoelectronic semiconductor device includes a support element having a first main surface, an optoelectronic semiconductor chip which is arranged over the support element and adjacent to the first main surface, and an electrical contact element for contacting the optoelectronic semiconductor chip. The electric contact element is arranged in an opening formed in the first main surface of the support element. | 2021-10-28 |
20210336111 | Method for Producing an Optoelectronic Component, and Optoelectronic Component - A method for producing an optoelectronic component and an optoelectronic component are disclosed. In an embodiment a method includes providing a semiconductor chip having an active region for radiation emission, applying a seed layer on the semiconductor chip, wherein the seed layer includes a first metal and a second metal being different from the first metal, and wherein the second metal is less noble than the first metal, applying a structured photoresist layer directly to the seed layer, applying a solder layer at least to regions of the seed layer which are not covered by the photoresist layer and wherein a proportion of the second metal in the seed layer is between 0.5 wt % and 10 wt %. | 2021-10-28 |
20210336112 | LIGHT EMITTING DEVICE - A light emitting device includes a flexible substrate, a light emitting element, a conductive connecting material and a first holding member. The flexible substrate includes a flexible base and a wire. The first holding member is arranged on an opposite side surface to a surface of a side of the substrate on which the light emitting element is mounted. The first holding member surrounds a region corresponding to a region on the substrate including the light emitting element and the conductive connecting material in a plan view. The first holding member is arranged adjacent to the wire. The first holding member includes an inner region arranged on an inner side of the first holding member, and having higher rigidity than rigidity of the flexible base, and an outer region arranged adjacent to the inner region outside the inner region, and having lower rigidity than rigidity of the inner region. | 2021-10-28 |
20210336113 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light-emitting device includes a lead frame, a semiconductor light-emitting element mounted on the top surface of the bonding region, and a case covering part of the lead frame. The bottom surface of the bonding region is exposed to the outside of the case. The lead frame includes a thin extension extending from the bonding region and having a top surface which is flush with the top surface of the bonding region. The thin extension has a bottom surface which is offset from the bottom surface of the bonding region toward the top surface of the bonding region. | 2021-10-28 |
20210336114 | STRUCTURES AND METHODS FOR ELECTRICALLY CONNECTING PRINTED COMPONENTS - A printed structure includes a destination substrate comprising two or more contact pads disposed on or in a surface of the destination substrate, a component disposed on the surface, and two or more electrically conductive connection posts. Each of the connection posts extends from a common side of the component. Each of the connection posts is in electrical and physical contact with one of the contact pads. The component is tilted with respect to the surface of the destination substrate. Each of the connection posts has a flat distal surface. | 2021-10-28 |
20210336115 | Light-Emitting Diode, Method for Manufacturing the Same, Backlight Source and Display Device - The present disclosure provides a light-emitting diode, a method for manufacturing the same, a backlight source and a display device. The light-emitting diode includes a support having a bottom wall, a light-emitting chip on the support, and a die bonding structure. A through hole is provided in the bottom wall. At least a portion of the die bonding structure is located in the through hole. The light-emitting chip is attached to the bottom wall through the die bonding structure. | 2021-10-28 |
20210336116 | THERMOELECTRIC ARRAY - An apparatus includes a thermoelectric generator and a lens. The thermoelectric generator includes a hot plate, and is configured to convert heat directly into electrical energy. The lens faces the sun on one side and faces the hot plate on the other side. The lens is configured to concentrate heat from the sun and onto the hot plate. | 2021-10-28 |
20210336117 | THERMOELECTRIC MATERIAL AND THERMOELECTRIC DEVICE INCLUDING THE SAME - A thermoelectric material which minimize the content of components that degrade thermoelectric performance and thus can be usefully used in thermoelectric devices including the same. | 2021-10-28 |
20210336118 | BUMPLESS SUPERCONDUCTOR DEVICE - An integrated circuit is provided that comprises a first substrate having a plurality of conductive contact pads spaced apart from one another on a surface of the first substrate, a dielectric layer overlying the first substrate and the plurality of conductive contact pads, and a second substrate overlying the dielectric layer. A plurality of superconducting contacts extend through the second substrate and the dielectric layer to the first substrate, wherein each superconducting contact of the plurality of superconducting contacts is aligned with and in contact with a respective conductive contact pad of the plurality of conductive contact pads. | 2021-10-28 |
20210336119 | USE OF SELECTIVE HYDROGEN ETCHING TECHNIQUE FOR BUILDING TOPOLOGICAL QUBITS - Embodiments of a Majorana-based qubit are disclosed herein. The qubit is based on the formation of superconducting islands, some parts of which are topological (T) and some parts of which are non-topological. Also disclosed are example techniques for fabricating such qubits. In one embodiment, a semiconductor nanowire is grown, the semiconductor nanowire having a surface with an oxide layer. A dielectric insulator layer is deposited onto a portion of the oxide layer of the semiconductor nanowire, the portion being designed to operate as a non-topological segment in the quantum device. An etching process is performed on the oxide layer of the semiconductor nanowire that removes the oxide layer at the surface of the semiconductor nanowire but maintains the oxide layer in the portion having the deposited dielectric insulator layer. A superconductive layer is deposited on the surface of the semiconductor nanowire, including over the dielectric insulator layer. | 2021-10-28 |
20210336120 | COMPOSITE SUPERCONDUCTING MATERIALS AND PROCESSES FOR THE PRODUCTION THEREOF - Superconductors and processes that form superconductors as composites of electrically polarizable ferroelectric materials and electrically conductive materials. The materials are chosen such that the binding energy of charge carriers within the materials exceeds the repulsive energy of the carriers and the energy carried by thermal vibrations (phonons) within the materials. | 2021-10-28 |
20210336121 | JOSEPHSON JUNCTIONS WITH REDUCED STRAY INDUCTANCE - Methods, systems and apparatus for forming Josephson junctions with reduced stray inductance. In one aspect, a device includes a substrate; a first superconductor layer on the substrate; an insulator layer on the first superconductor layer; a second superconductor layer on the insulator layer, wherein the first superconductor layer, the insulator layer, and the second superconductor layer form a superconductor tunnel junction; and a third superconductor layer directly on a surface of the first superconductor layer and directly on a surface of the second superconductor layer to provide a first contact to the superconducting tunnel junction and a second contact to the superconductor tunnel junction, respectively. | 2021-10-28 |
20210336122 | ACTUATOR DEVICE BASED ON AN ELECTROACTIVE MATERIAL - An electroactive material actuator is clamped along one edge ( | 2021-10-28 |
20210336123 | Area Element - A surface element with a first layer, which has a conductive loop embedded in an insulating material, and with a sensor layer forming a second layer that is in contact with the conductive loop. The sensor layer is designed for detecting at least one external input variable. Dependent upon this detection, a current flowing through the conductive loop is affected. The surface element can be operated in a reverse operation such that by feeding currents into the conductive loop, the one or each of multiple sensor layer(s) generates output variables. | 2021-10-28 |
20210336124 | PIEZOELECTRIC POLYVINYLIDENE FLUORIDE MATERIAL, METHOD FOR MANUFACTURING SAME, AND FINGERPRINT RECOGNITION MODULE - A piezoelectric polyvinylidene fluoride (PVDF) material, a method for manufacturing the same, and a fingerprint recognition module are provided. The polyvinylidene PVDF material includes PVDF, a first solvent, a second solvent, a fluorosurfactant, and an inducing material. Material of the inducing material is one of carbon nanotubes, carbon black, and gold nanorods. Because of the high anisotropy of the inducing material, molecular orientation of the PVDF material is induced, thereby improving piezoelectric performance of the piezoelectric PVDF material. Problems of conventional piezoelectric PVDF materials, which are used in ultrasonic fingerprint recognition modules, such as poor piezoelectric performance and high-energy loss are improved. | 2021-10-28 |
20210336125 | PLANARIZATION METHOD - The invention provides a planarization method, which can make the local flatness of the product to be processed more uniform. The product has a cavity filled with oxide and includes a first electrode layer, a piezoelectric layer and a second electrode layer superposed on the cavity. The first electrode layer covers the cavity and includes a first inclined face around the first electrode layer, and the piezoelectric layer covers the first electrode layer and is arranged on the first electrode layer. The planarization method includes: depositing a passivation layer on the second electrode layer and etching the passivation layer completely until the thickness of the passivation layer is reduced to the required thickness. | 2021-10-28 |
20210336126 | MEMORY DEVICE COMPRISING A TOP VIA ELECTRODE AND METHODS OF MAKING SUCH A MEMORY DEVICE - An illustrative device disclosed herein includes at least one layer of insulating material, a conductive contact structure having a conductive line portion and a conductive via portion and a memory cell positioned in a first opening in the at least one layer of insulating material. In this illustrative example, the memory cell includes a bottom electrode, a memory state material positioned above the bottom electrode and an internal sidewall spacer positioned within the first opening and above at least a portion of the memory state material, wherein the internal sidewall spacer defines a spacer opening and wherein the conductive via portion is positioned within the spacer opening and above a portion of the memory state material. | 2021-10-28 |
20210336127 | BiSb Topological Insulator with Seed Layer or Interlayer to Prevent Sb Diffusion and Promote BiSb (012) Orientation - A spin-orbit torque (SOT) magnetic tunnel junction (MTJ) device includes a substrate, a seed layer over the substrate, and a bismuth antimony (BiSb) layer having (0120) orientation on the seed layer. The seed layer includes a silicide layer and a surface control layer. The silicide layer includes a material of NiSi, NiFeSi, NiFeTaSi, NiCuSi, CoSi, CoFeSi, CoFeTaSi, CoCuSi, or combinations thereof. The surface control layer includes a material of NiFe, NiFeTa, NiTa, NiW, NiFeW, NiCu, NiCuM, NiFeCu, CoTa, CoFeTa, NiCoTa, Co, CoM, CoNiM, CoNi, NiSi, CoSi, NiCoSi, Cu, CuAgM, CuM, or combinations thereof, in which M is Fe, Cu, Co, Ta, Ag, Ni, Mn, Cr, V, Ti, or Si. | 2021-10-28 |
20210336128 | MRAM STRUCTURE WITH TERNARY WEIGHT STORAGE - A memory device is provided that includes at least one MTJ pillar which can have a ternary program state as compared to a binary program state in a conventional device. The MTJ pillar contains a lower MTJ structure that includes at least a first magnetic reference material, a first tunnel barrier and a first magnetic free layer material, and an upper MTJ structure that includes at least a second magnetic reference material, a second tunnel barrier and a second magnetic free layer material; the upper MTJ structure is stacked atop the lower MTJ structure. The first and second magnetic free layer materials have different designs and/or compositions resulting in different switching voltages. | 2021-10-28 |
20210336129 | CONFINED CELL STRUCTURES AND METHODS OF FORMING CONFINED CELL STRUCTURES - Techniques for reducing damage in memory cells are provided. Memory cell structures are typically formed using dry etch and/or planarization processes which damage certain regions of the memory cell structure. In one or more embodiments, certain regions of the cell structure may be sensitive to damage. For example, the free magnetic region in magnetic memory cell structures may be susceptible to demagnetization. Such regions may be substantially confined by barrier materials during the formation of the memory cell structure, such that the edges of such regions are protected from damaging processes. Furthermore, in some embodiments, a memory cell structure is formed and confined within a recess in dielectric material. | 2021-10-28 |
20210336130 | METHOD OF MANUFACTURING MRAM DEVICE WITH ENHANCED ETCH CONTROL - A method of manufacturing a semiconductor device includes: forming a substrate over the substrate, the substrate defining a logic region and a memory region; depositing a bottom electrode layer across the logic region and the memory region; depositing a magnetic tunnel junction (MTJ) layer over the bottom electrode layer; depositing a first conductive layer over the MTJ layer; depositing a sacrificial layer over the first conductive layer; etching the sacrificial layer in the memory region to expose the first conductive layer in the memory region while keeping the first conductive layer in the logic region covered; depositing a second conductive layer in the memory region and the logic region; patterning the second conductive layer to expose the MTJ layer in the memory region; and etching the patterned second conductive layer and the MTJ layer to form a top electrode and an MTJ, respectively, in the memory region. | 2021-10-28 |