43rd week of 2021 patent applcation highlights part 68 |
Patent application number | Title | Published |
20210336531 | Power Supply Apparatus - The present disclosure provides a power supply apparatus, which provides an output voltage outputted by a DC/DC power circuit to a power supply system of a load and includes: an external terminal which a load-side ground potential is applied to; an adding portion configured for adding the load-side ground potential applied to the external terminal to a set reference voltage; a low-pass filter (LPF) including at least one resistor and at least one capacitor, wherein the LPF inputs an LPF input voltage based on an adding result of the adding portion; and an error amplifier, wherein the error amplifier is inputted an LPF output voltage from the LPF as a reference voltage and inputted a feedback voltage based on the LPF output voltage. The error amplifier is included in the DC/DC power circuit. The output voltage is controlled according to an output of the error amplifier. | 2021-10-28 |
20210336532 | METHOD OF CONTROLLING TIME PARAMETER - Disclosed is a method of controlling a time parameter performed by a power controller having a power pin, a ground pin, a driving pin, a time parameter selecting pin, a feedback pin, and a current sensing pin. The power controller is in collocation with a rectification unit, a transformer, a switch unit, a power output unit, and a feedback unit. A Pulse Width Modulation (PWM) frequency of a driving signal, an Over-Voltage Protection (OVP) delay time, and an Under-Voltage Protection (UVP) delay time are preset in the power controller. An external time parameter selecting signal is received through the time parameter selecting pin to dynamically update the PWM frequency, the OVP delay time, or the UVP delay time, thereby greatly increasing efficiency of power conversion and avoiding malfunction of OVP or UVP. | 2021-10-28 |
20210336533 | DISCHARGE OF AN AC CAPACITOR USING TOTEM-POLE POWER FACTOR CORRECTION (PFC) CIRCUITRY - An AC capacitor is coupled to a totem-pole type PFC circuit. In response to detection of a power input disconnection, the PFC circuit is controlled to discharge the AC capacitor. The PFC circuit includes a resistor and a first MOSFET and a second MOSFET coupled in series between DC output nodes with a common node coupled to the AC capacitor. When the disconnection event is detected, one of the first and second MOSFETs is turned on to discharge the AC capacitor with a current flowing through the resistor and the turned on MOSFET. Furthermore, a thyristor may be simultaneously turned on, with the discharge current flowing through a series coupling of the MOSFET, resistor and thyristor. Disconnection is detected by detecting a zero-crossing failure of an AC power input voltage or lack of input voltage decrease or input current increase in response to MOSFET turn on for a DC input. | 2021-10-28 |
20210336534 | VOLTAGE CONVERTER CIRCUIT - A voltage converter circuit may include: a first input node; a second input node; a first output node; a second output node; one or more charge pumps that convert a first input voltage supplied to the first input node up to a first output voltage and convert a second input voltage supplied to the second input node down to a second output voltage; and a control circuit to control the one or more charge pumps according to two operational modes. In the first operation mode, the control circuit supplies the first input voltage to the first input node, leaves the second input node floating, and outputs the first output voltage at the first output node. In the second operation mode, the control circuit supplies the second input voltage to the second input node, leaves the first input node floating, and outputs the second output voltage at the second output node. | 2021-10-28 |
20210336535 | POWER SUPPLY SYSTEM WITH STABLE LOOP - The invention relates to the field of power and electronic technologies, particularly to a power supply system with a stable loop comprising a PMOS transistor, a NMOS transistor, a first comparator and a voltage control circuit connected between a comparison terminal and the ground; wherein, a current-limiting acquisition port is configured to acquire on-state current of the PMOS transistor; and the current-limiting protection circuit outputs an voltage signal of the comparison result as the control signal of the pulse width modulation driver when the acquired on-current state of the PMOS transistor is less than a preset current value; and outputs a turn-off signal for turning off the pulse width modulation driver as the control signal when the acquired on-current state of the PMOS transistor is greater than a preset current value. The present invention has the advantages that relatively high loop stability can be ensured and high reliability is achieved. | 2021-10-28 |
20210336536 | TECHNIQUES TO IMPROVE CURRENT REGULATOR CAPABILITY TO PROTECT THE SECURED CIRCUIT FROM POWER SIDE CHANNEL ATTACK - This disclosure relates to current flattening circuits for an electrical load. The current flattening circuits incorporate randomize various parameters to add noise onto the supply current. This added noise may act to reduce the signal to noise ratio in the supply current, increasing the difficulty of identifying a computational artifact signal from power rail noise. | 2021-10-28 |
20210336537 | POWER SOURCE SWITCHING DEVICE - A power source switching device that includes: a switch connected to a signal input terminal via a first resistor element and configured to fix a potential of the signal input terminal at a predetermined potential by adopting an ON state in a case in which a selection signal is not input; and a switch control circuit configured to perform control to place the switch in an OFF state based on a state signal indicating an operational state of a circuit that operates when supplied with power from a power source selected according to the selection signal in a case in which a potential of the selection signal is different from the predetermined potential, and to perform control to place the switch in the ON state in a case in which the selection signal is not input. | 2021-10-28 |
20210336538 | DC-COUPLED HYBRID ENERGY SYSTEM AND METHOD FOR CONVERTING DC VOLTAGES - A method is provided for setting an operating parameter for a DC to DC voltage converter. A load is operated, using a controller, with the operating parameter at a first value. A measurement of an actual inductor current at an inductor of the DC to DC voltage converter, a measurement of an actual load current are provided. The method then determines a reference value for the inductor current, based on the actual load current combined with an inductor current adjustment value based on a desired output voltage at the DC load. The reference value for the inductor current is then compared to the actual inductor current, and the operating parameter is maintained at the first value if the reference value is greater than the actual inductor current. The operating parameter is changed to a second value if the reference value is less than the actual inductor current. | 2021-10-28 |
20210336539 | SYSTEM AND METHOD OF AUTOMATIC CALIBRATION TO MAXIMIZE LOAD CURRENT SUPPORT OF DC-DC CONVERTER OPERATING IN PULSE-PAIRING MODE - A DC-DC converter including converter circuitry, a voltage detector providing a low voltage signal, and pulse-pairing circuitry. The converter circuitry may be configured according to a buck or a boost configuration switching between a zero and peak current levels. The pulse-pairing circuitry includes a paired pulse generator, a load detector, and a maximum on timing controller. In response to the low voltage signal, the paired pulse generator activates an on signal for a pair of equal duration on pulses separated by a predetermined pulse separation interval. The on time periods are based on an adjustable time value and a peak current indication. The load detector provides a load adjust signal for adjusting the time value based on sampling the low voltage signal and an off time signal at the start of the second pulse. The maximum on timing controller adjusts the adjustable time value based on the load adjust signal. | 2021-10-28 |
20210336540 | CASCADED CONVERTER CIRCUIT CONTROL - A cascaded converter system can include a first boost circuit configured to output a first voltage that is higher than an input voltage, and a second boost circuit configured to output a second voltage that is higher than the first voltage. The system can include an intermediate capacitor disposed in parallel between the first boost circuit and the second boost circuit. The system can include a controller configured to control the first and second boost circuit to reduce an RMS current to the intermediate capacitor and/or an area under an intermediate capacitor current plot. | 2021-10-28 |
20210336541 | DC-DC CONVERTER - The present disclosure discloses example DC-DC converters. One example DC-DC converter includes a first capacitor, a second capacitor, a switched capacitor SC circuit, and an inductor circuit. An input end of the SC circuit is coupled to a voltage input end, and an output end of the SC circuit is coupled to a voltage output end. The first capacitor and the second capacitor are sequentially connected in series between the voltage input end and the voltage output end. One end of the inductor circuit is selectively coupled between the first capacitor and the second capacitor or to a ground end, and the other end of the inductor circuit is coupled to the voltage output end. | 2021-10-28 |
20210336542 | BUCK-BOOST VOLTAGE CONVERTER - In some examples, a converter circuit can be configured to operate in a buck-boost mode. The converter circuit can include a ramp generator that can be configured to generate first and second ramp signals that at least partially overlap respective portions of a buck-boost region during each intermediate clock cycle between clock cycles of a clock signal. By generating the first and second ramp signals during each intermediate clock cycle, first and second drivers can be provided to toggle switches of a power stage, such that an output voltage provided by the power stage can be averaged out over clock cycles of the clock signal to allow for a gradual transition between buck and boost modes of operation of the converter circuit. In some examples, the converter circuit can be configured to operate in a test mode and can be configured to implement trimming of a ramp signal. | 2021-10-28 |
20210336543 | CURRENT EMULATION IN A POWER SUPPLY - An apparatus comprises an emulator and a corresponding compensator. During operation, the emulator produces, at different instants of time, an emulated output current value representative of an amount of current supplied from an output voltage to a load. In general, the compensator provides selective compensation to the emulated output current value over time. For example, for a first time duration, compensation adjustments from the compensator are used to modify the emulated output current value. For a second duration of time, compensation adjustments from the compensator are not used to modify the emulated output current value. Disabling or discontinuing application of adjustments (such as based on the actual measured output current) during the second time duration (such as during a respective transient condition) provides more accurate and timely generation of a respective emulated output current value. | 2021-10-28 |
20210336544 | POWER STAGES AND CURRENT MONITOR OUTPUT SIGNAL (IMON) GENERATION CIRCUIT - Apparatus and associated methods relate to implementing an auto-inductance-detection architecture to reconstruct current monitor output (IMON) when a low-side switch in a power stage is on. In an illustrative example, an IMON generation circuit may include a variable resistor. A close loop control (e.g., OTA, switches, and variable resistor) may be configured to adjust a resistance value of the variable resistor automatically. The IMON generation circuit may also include a low pass filter coupled to a switching node of the power stage to receive a corresponding signal and provide a DC value. The difference between the corresponding signal and the DC value may be configured to enable or disable the close loop control. By providing the close loop control, the IMON generation circuit may advantageously perform auto-inductance detection (AID) and provide a more accurate IMON reconstruction method. | 2021-10-28 |
20210336545 | Power Supply Device and Charging Control Method - A power supply device and a charging control method are provided. The power supply device includes: a transformer; a first conversion circuit, provided at a primary side of the transformer and configured to convert an alternating current provided by a power grid into a pulsating voltage; a second conversion circuit, provided at a secondary side of the transformer and configured to generate an output current of the power supply device; a feedback circuit, configured to generate a feedback signal of the output current; and a switch control unit, configured to control the pulsating voltage according to a power-grid synchronization signal and the feedback signal, such that waveforms of the output current and the synchronization signal are consistent, the synchronization signal being a pulsating signal, a frequency of the synchronization signal being n or 1/n times that of the alternating current, and n being a positive integer not less than 1. | 2021-10-28 |
20210336546 | SYNCHRONOUS RECTIFIER CONTROLLER AND CONTROL METHOD THEREOF - A synchronous rectifier controller for controlling a rectifier switch is disclosed. The synchronous rectifier controller includes a fully-ON controller and a regulator. Capable of being triggered by a channel voltage of the rectifier switch, the fully-ON controller turns the rectifier switch fully ON for a fully-ON time in view of a predetermined condition. The regulator, disabled during the fully-ON time and enabled after the fully-ON time, turns the rectifier switch ON to regulate the channel voltage within a predetermined voltage range. | 2021-10-28 |
20210336547 | SWITCHING POWER SUPPLY UNIT AND ELECTRIC POWER SUPPLY SYSTEM - A switching power supply unit includes a pair of input terminals, a pair of output terminals, a transformer, an inverter circuit, a rectifying and smoothing circuit, and a driver. The inverter circuit includes first to fourth switching devices, a first capacitor, a resonant inductor, and a resonant capacitor. The rectifying and smoothing circuit includes a rectifying circuit including rectifying devices, and a smoothing circuit. The first to fourth switching devices are coupled in series in this order between two input terminals constituting the pair of input terminals. The first capacitor is disposed between a connection point between the first and second switching devices and a connection point between the third and fourth switching devices. The resonant inductor, the resonant capacitor, and a primary winding are coupled in series in no particular order between a connection point between the second and third switching devices and one of the two input terminals. | 2021-10-28 |
20210336548 | ISOLATED CONVERTER WITH HIGH BOOST RATIO - An isolated converter with high boost ration includes a transformer, a first bridge arm, a second bridge arm, and a boost circuit. The transformer includes a secondary side having a secondary side first node and a secondary side second node. The first bridge arm includes a first diode and a second diode. The second bridge arm includes a third diode and a fourth diode. The boost circuit includes at least one fifth diode coupled between the first bridge arm and the secondary side second node, at least one sixth diode coupled between the second bridge arm and the secondary side first node, and at least two capacitors coupled to the secondary side first node and the secondary side second node. | 2021-10-28 |
20210336549 | BIDIRECTIONAL POWER CONVERTER - A power conversion apparatus includes: matrix converter circuitry to perform power conversion between a primary side electric power and a secondary side electric power; rectifier circuitry to convert the primary side electric power to charge a capacitor; and control circuitry to: set a changeover reference voltage at a first reference voltage when the primary side voltage magnitude is a first voltage magnitude and set the changeover reference voltage at a second reference voltage when the primary side voltage magnitude is a second voltage magnitude; and select, based on the changeover reference voltage and the terminal voltage, a connection state from: a first connection state in which the rectifier circuitry is connected to the capacitor by a first route including a current limit device; and a second connection state in which the rectifier circuitry is connected to the capacitor by a second route that bypasses the current limit device. | 2021-10-28 |
20210336550 | METHOD FOR PRE-CHARGING A CASCADE CONVERTER AND CASCADE CONVERTER - The present application provides a method for pre-charging a cascade converter and a cascade converter. The cascade converter includes a main transformer, multiple power units, a control unit and a precharge unit. Power units connected with the precharge unit are a first power unit group, and other power units are a second power unit group. The control unit controls first switch set in the precharge unit to be turned on, and low-voltage AC power supply in the precharge unit performs pre-charging for a bus capacitor through an inverter circuit in the first power unit group. When a voltage of the bus capacitor reaches a first voltage threshold, the control unit controls a rectifier circuit in the first power unit group to work to magnetize the main transformer, thereby performing pre-charging for bus capacitors in the second power unit group. | 2021-10-28 |
20210336551 | UNINTERRUPTIBLE POWER SUPPLY AND METHOD OF OPERATION - An uninterruptible power supply (UPS) is provided that includes a split direct current (DC) link having a first capacitor coupled between a positive DC link terminal and a first node, and a second capacitor coupled between the first node and a negative DC link terminal. The UPS also includes a rectifier coupled to an input of the split DC link and a controller coupled to the rectifier. The rectifier includes first, second, and third legs, wherein each leg is configured to convert a first alternating current (AC) voltage received from an AC source into a DC voltage to be provided to the split DC link, and a fourth leg configured to balance DC link voltages of the first and second capacitors. The controller is configured to maintain functionality of the rectifier during at least one of a partial utility power outage, a full utility outage, and a failure of at least one of the first, second, third, and fourth legs. | 2021-10-28 |
20210336552 | POWER ELECTRONIC ARRANGEMENT WITH DC VOLTAGE CONNECTION ELEMENT AND METHOD FOR ITS PRODUCTION - A power converter module has a switching device with a substrate with a first and a second DC voltage conductor track and a first and a second DC voltage terminal element connected in an electrically conducting manner with the correct polarity, and having a first and a second DC voltage connection element. The first DC voltage terminal element is connected to the first DC voltage connection element in an electrically conducting manner with the correct polarity by means of a first materially-bonded connection, wherein the second DC voltage terminal element is connected to the second DC voltage connection element in an electrically conducting manner with the correct polarity by means of a second materially-bonded connection. | 2021-10-28 |
20210336553 | POWER ELECTRONIC ARRANGEMENT WITH A MULTI-PHASE POWER SEMICONDUCTOR MODULE - A power electronic arrangement has a plurality of single-phase power semiconductor modules and one multi-phase power semiconductor module, wherein each single-phase power semiconductor module has a first, at least frame-like housing, two first DC voltage terminal elements, a first AC voltage terminal element, first auxiliary terminal elements and a first switching device. The multi-phase power semiconductor module has a second, at least frame-like housing, two second DC voltage terminal elements, at least two second AC voltage terminal elements, second auxiliary terminal elements and a second switching device. The first and second DC voltage terminal elements each form a stack in a section of their length and on the terminal sections are designed identically. All the power semiconductor modules are arranged in a row in the direction of the normal vectors of the respective first longitudinal side. The first and second DC voltage terminal elements of all power semiconductor modules are arranged on the same, a first, narrow side. | 2021-10-28 |
20210336554 | CIRCUIT FOR CONTROLLING SWITCHING POWER SUPPLY AND METHOD FOR CONTROLLING SWITCHING POWER SUPPLY BY USING CIRCUIT - A circuit for controlling a switching power supply and a method for controlling a switching power supply by using the circuit for controlling the switching power supply, the circuit for controlling a switching power supply is configured to control a power stage circuit of a converter of the switching power supply. The circuit for controlling the switching power supply includes an external magnetic field direct detection unit, a current limit threshold unit, an operating frequency unit, a pulse width unit and a logic unit. The external magnetic field direct detection unit includes a Hall device and a Hall detection component. In accordance with the circuit for controlling the switching power supply of the present disclosure, the intensity of the external magnetic field can be detected directly at the chip level, and the operating mode of the switching power supply system can be adjusted timely. | 2021-10-28 |
20210336555 | AC TO DC CONVERTERS - A converter circuit includes first and second input terminals, control circuitry, and a storage capacitor. The first and second input terminals are configured for connection to an AC power supply to receive an AC signal. The control circuitry is coupled to the first and second input terminals. A terminal of the storage capacitor is coupled to an output node of the control circuitry. The storage capacitor is charged by the control circuitry and configured for use as a DC power source. The control circuitry is configured to couple the first input terminal to the storage capacitor during a portion of a positive half-cycle of the input AC signal to charge the storage capacitor and to decouple the first input terminal from the storage capacitor during an entirety of each negative half-cycle of the input AC signal, to thereby prevent discharging of the storage capacitor by the input AC signal. | 2021-10-28 |
20210336556 | Power Conversion Device - In order to reduce noise current leaking out from a frame to which semiconductor devices constituting a three-level power conversion circuit are attached to the outside of a power conversion device, the frame to which the semiconductor devices constituting the three-level power conversion circuit with which the power conversion device is equipped are attached is configured to be electrically connected to a neutral point of the three-level power conversion circuit. The noise current leaking out from the frame is thereby drawn back to the neutral point of the three-level power conversion circuit to suppress the flowing out of the noise current to the outside of the power conversion device and reduce the noise current. | 2021-10-28 |
20210336557 | SYSTEM AND METHOD OF UTILIZING LLC CONVERTERS - In one or more embodiments, one or more systems, methods, and/or processes may: receiving, by a first circuit of an inductor-inductor-capacitor (LLC) converter, a pulse width modulation (PWM) signal to control a gate of a metal-oxide-semiconductor field-effect transistor (MOSFET) of a plurality of metal-oxide-semiconductor field-effect transistors (MOSFETs) of the LLC converter; provide, by the first circuit, current to a transformer based at least on amplifications of the PWM by at least one of the plurality of power MOSFETs; determine, by the second circuit, if a voltage value associated with a drain of the power MOSFET is above a threshold voltage value; if so, suppress, by the second circuit, the PWM signal to the gate of the power MOSFET; and if not, permit, by the second circuit, the PWM signal to the gate of the power MOSFET. | 2021-10-28 |
20210336558 | Detector and Power Conversion Apparatus - Provided is a detector. The detector includes: one or more detection diodes configured to detect a change in an environment of a detection target; a Y capacitor including a plurality of capacitors separately disposed between one end of the detection diodes and a GND and between the other end of the detection diodes and the GND; and a rectifier circuit disposed at least between one end of the detection diodes and the GND or between the other end of the detection diodes and the GND, connected in series with the Y capacitor, and configured to transmit a common-mode current accompanying noise induced in the detection diodes to the GND and cut off a normal-mode loop current that flows between the plurality of capacitors and the detection diodes. | 2021-10-28 |
20210336559 | TRIBOELECTRIC NANOGENERATOR USING IONIC ELASTOMER - The present invention relates to an triboelectric nanogenerator using an ionic elastomer that increases internal electric capacity and allows a large amount of electric charge to be located on a surface to generate a large amount of electrical energy. The triboelectric nanogenerator according to the present invention includes a first electrode; an ionic elastomer disposed on the first electrode and including an elastomer and an ionic liquid; a second electrode disposed to be spaced apart from the first electrode and electrically connected to the first electrode; and an insulator disposed under the second electrode, selectively contacting the ionic elastomer, and formed of a material that has a negative charge compared to the ionic elastomer. In this case, the ionic elastomer and the insulator are brought into contact with each other or are separated from each other by external force, and electrical energy is generated between the first and second electrodes when the ionic elastomer and the insulator are brought into contact with each other and separated from each other. | 2021-10-28 |
20210336560 | DETERMINING AND APPLYING A VOLTAGE TO A PIEZOELECTRIC ACTUATOR - The invention relates to a method and an actuator system for determining and applying a voltage to a piezoelectric actuator (PEA) to achieve a given setpoint displacement. The method involves determining a relation d | 2021-10-28 |
20210336561 | SELF-RESONANCE TUNING PIEZOELECTRIC ENERGY WITH BROADBAND FREQUENCY - Proposed is a self-resonance tuning piezoelectric energy harvester with broadband frequency, including: a piezoelectric beam which is extended along a horizontal direction; a fixing member which fixes opposite ends of the piezoelectric beam; and a mobile mass which the piezoelectric beam passes through, and which is capable of self-movement along the piezoelectric beam through a through-hole which has a free space in addition to a space which the piezoelectric beam passes through, wherein as the mobile mass moves to a position of the piezoelectric beam, generated displacement of a piezoelectric beam is increased, and as the generated displacement becomes greater than the free space, the mobile mass is fixed to a position of a piezoelectric beam at which resonance will occur. | 2021-10-28 |
20210336562 | BIONIC ARM - A bionic arm comprises a bionic palm and at least one finger. The at least one finger comprises a nanofiber actuator. A nanofiber actuator comprises a composite structure and a vanadium dioxide layer. The composite structure comprises a carbon nanotube wire and an aluminum oxide layer. The aluminum oxide layer is coated on a surface of the carbon nanotube wire, and the aluminum oxide layer and the carbon nanotube wire are located coaxially with each other. The vanadium dioxide layer is coated on a surface of the composite structure, and the vanadium dioxide layer and the composite structure are located non-coaxially with each other. | 2021-10-28 |
20210336563 | NANO MANIPULATER - A nano manipulator comprises a base and a clamping structure. The clamping structure comprises two nanofiber actuators located on the base and spaced from each other. Each of the two nanofiber actuators comprises a composite structure and a vanadium dioxide layer. The composite structure comprises a carbon nanotube wire and an aluminum oxide layer. The aluminum oxide layer is coated on a surface of the carbon nanotube wire, and the aluminum oxide layer and the carbon nanotube wire are located coaxially with each other. The vanadium dioxide layer is coated on a surface of the composite structure, and the vanadium dioxide layer and the composite structure are located non-coaxially with each other. | 2021-10-28 |
20210336564 | NANOFIBER ACTUATOR AND METHOD FOR MAKING THE SAME - A nanofiber actuator comprises a composite structure and a vanadium dioxide layer. The composite structure comprises a carbon nanotube wire and an aluminum oxide layer. The aluminum oxide layer is coated on a surface of the carbon nanotube wire, and the aluminum oxide layer and the carbon nanotube wire are located coaxially with each other. The vanadium dioxide layer is coated on a surface of the composite structure, and the vanadium dioxide layer and the composite structure are located non-coaxially with each other. | 2021-10-28 |
20210336565 | MOTOR DRIVING DEVICE INCLUDING SINGLE INVERTER FOR SINGLE-PHASE MOTOR AND THREE-PHASE MOTOR AND APPLIANCE HAVING THE SAME - A motor driving device controls a three-phase motor and a single-phase motor to operate in parallel. The motor driving device includes a dc terminal in which an upper and a lower DC-link capacitor are located. The motor driving device also includes a neutral terminal disposed between the upper and lower DC-link capacitors. The motor driving device includes an inverter that includes three pairs of upper switching elements and lower switching elements. Two pairs of upper switching elements and lower switching elements among three pairs are connected to an a-phase terminal and a b-phase terminal of the three-phase motor, respectively. The other pair of upper switching elements and lower switching elements among three pairs is connected to a first terminal of the single-phase motor. The neutral terminal is connected to a second terminal of the single-phase motor. A c-phase terminal of the three-phase motor is connected to the single-phase motor. | 2021-10-28 |
20210336566 | RANGING APPARATUS AND SCAN MECHANISM THEREOF, CONTROL METHOD, AND MOBILE PLATFORM - A scan mechanism of a ranging apparatus includes a plurality of optical elements, a plurality of motors, and a controller or a plurality of controllers. The plurality of motors correspond to the plurality of optical elements. A motor includes a hollow rotor. An optical element is arranged at the rotor of a corresponding motor. The controller controls the plurality of motors. At least one of the plurality of controllers controls at least two of the plurality of motors. When one controller controls at least two motors, the controller controls the at least two motors to rotate at a predetermined angle difference based on a first synchronization strategy. When one controller controls one motor, the controller controls the motor and another at least one motor to rotate at the predetermined angle difference based on a second synchronization strategy. | 2021-10-28 |
20210336567 | FEEDBACK COMPENSATION OF PARAMETER IMBALANCE INDUCED CURRENT HARMONICS IN SYNCHRONOUS MOTOR DRIVES - A method for compensating parameter imbalance induced current harmonics in a synchronous motor drive includes reading an output current signal and extracting, based on the output current signal, a signature of a parameter imbalance corresponding to the synchronous motor drive. The method also includes compensating, based on the signature, for the current harmonics induced by parameter imbalance in a closed loop using a feedback path. | 2021-10-28 |
20210336568 | MOTOR CONTROL APPARATUS AND MOTOR CONTROL APPARATUS CONTROL METHOD - A motor control apparatus that is configured to perform a power distribution control on three-phase coils of a brushless motor and that is configured to perform a rotation control of a rotor includes: a plurality of switching elements that are arranged to be capable of switching a current which is allowed to flow through the coils; a plurality of sensors that are configured to detect a rotation position of the rotor; and a control part that is configured to output a drive signal for controlling a power distribution pattern of each switching element according to a position detection signal which is obtained by correcting a position detection signal as an output of the plurality of sensors by using a predetermined correction coefficient, wherein the control part is configured to add a correction angle that corresponds to a difference between the position detection signals before and after correction of a predetermined sensor among the plurality of sensors to a setting value of an advance angle of the power distribution control and select an output pattern that includes a plurality of power distribution patterns and that is used when selecting the power distribution pattern, from a plurality of different output patterns in accordance with the advance angle to which the correction angle is added and a power distribution angle of the power distribution control. | 2021-10-28 |
20210336569 | DC Bus Discharge Control Method, Apparatus and Device, and Storage Medium - Provided is a Direct Circuit (DC) bus discharge control method, including that: an active discharge instruction is received; a motor current signal is acquired according to the active discharge instruction; the motor current signal is converted into a current signal in a stator coordinate system; a voltage control signal in the stator coordinate system is output based on the current signal in the stator coordinate system and a current reference instruction of a preset stator coordinate system, the current reference instruction of the preset stator coordinate system being a high-frequency alternating current; and the voltage control signal in the stator coordinate system is converted into a three-phase voltage control signal, and a working state of a switching device is controlled according to the three-phase voltage control signal. | 2021-10-28 |
20210336570 | CONTROL APPARATUS AND METHOD OF CONTROLLING THE SAME - A control apparatus that controls a stepping motor, comprises a determination unit configured to determine a current value to be applied to the stepping motor by looking up a first driving table, which is to be looked up when driving is to be performed in a first driving direction, and a second driving table, which is to be looked up when driving is to be performed in a second driving direction in reverse of the first driving direction. The determination unit includes an interpolation calculation unit configured to calculate the current value by interpolation calculation that looks up both the first driving table and the second driving table, in a case in which driving is to be performed in a driving direction different from a driving direction of a preceding driving operation. | 2021-10-28 |
20210336571 | Closed-Loop Stepper Motor Control System, Drive Device And Automation Device. - A closed-loop stepper motor control system, drive device and automation device, wherein the system comprises a microprocessor ( | 2021-10-28 |
20210336572 | METHODS AND SYSTEMS FOR DETECTING A ROTOR POSITION AND ROTOR SPEED OF AN ALTERNATING CURRENT ELECTRICAL MACHINE - A method for determining rotor characteristic of an alternating current (AC) electrical machine includes obtaining a reference voltage signal, one or more phase currents, and rotor data. The method includes determining orthogonal components of an extended back electromotive force (BEMF) model of the AC electrical machine based on the reference voltage signal, the one or more phase current characteristics, and the rotor data. The method includes determining a product of the orthogonal components of the extended BEMF model. The method includes determining a squared-magnitude of the orthogonal components of the extended BEMF mode. The method includes determining the rotor characteristic of the AC electrical machine based on the product of the orthogonal components and the squared-magnitude of the orthogonal components. | 2021-10-28 |
20210336573 | SYNCHRONOUS MOTOR DRIVE SYSTEM AND SYNCHRONOUS MOTOR DRIVE METHOD - The present disclosure is constructed on the prior art inverter architecture, a pulse code width modulation (PCWM). This is an open loop motor control system without sensing its rotor position. The present disclosure employs a closed loop method to track the optimum efficiency motor operating point directly. A bench load test is conducted to gather information for an AI type control, which includes both load angle vs. voltage command charts and power factor vs. voltage command charts, with load levels as parameters for certain frequency command ranges. This way, the optimum efficiency motor operating points are generated a priori. The AI type control is mechanized to track the optimum efficiency motor operating points. | 2021-10-28 |
20210336574 | METHOD AND SYSTEM FOR BRUSHLESS WOUND FIELD SYNCHRONOUS MACHINES - An electric machine includes a stator having a stator winding disposed thereon. A rotor is electromagnetically exposed to the stator. A field winding and an induction winding are disposed on the rotor. A rectifier is electrically coupled to the induction winding and the field winding. Upon application of a voltage to the stator winding, the stator winding produces a first rotating magnetic field and a second rotating magnetic field that has a different spatial frequency than the first rotating magnetic field. The first rotating magnetic field interacts asynchronously with the induction winding to produce an alternating current in the induction winding. The rectifier changes the alternating current to a direct current that is supplied to the field winding. The field winding interacts synchronously with the second rotating magnetic field. | 2021-10-28 |
20210336575 | ELECTRIC POWER TOOL - An electric power tool includes: a brushless motor having a plurality of stator windings and configured to rotate in accordance with voltages applied to the plurality of stator windings, an induced voltage being generated in accordance with a rotation of the brushless motor; a rectifier circuit configured to rectify an AC voltage; a smoothing capacitor configured to smooth the AC voltage rectified by the rectifier circuit to a pulsation voltage having a maximum value larger than the induced voltage and a minimum value smaller than the induced voltage; and an inverter circuit configured to perform switching operations to output the pulsation voltage to the plurality of stator windings by rotation. | 2021-10-28 |
20210336576 | TEMPERATURE ESTIMATION DEVICE, MOTOR CONTROL DEVICE, AND TEMPERATURE ESTIMATION METHOD - A temperature estimation device estimates a drive duty ratio by taking account of the influence of ambient temperature on the energization to a coil part, on the basis of a drive duty ratio and the ambient temperature, and estimates the power consumption of a motor when the coil part is energized with the estimated drive duty ratio, the power consumption of the motor, this power consumption being accompanied by the heat dissipation of the coil part, the power difference between both the power consumption values, the temperature time constant of the coil part, and a temperature variation during a period of the temperature time constant of the coil part, and estimates the temperature variation of the coil part from the ambient temperature on the basis of these estimated values and a last temperature variation of the coil part. | 2021-10-28 |
20210336577 | Motor Control Circuit - The present disclosure is related to ensuring a period for detecting a phase current from a DC bus current of an inverter. A motor control circuit of the present disclosure includes: a voltage command generator and a PWM signal generator. The voltage command generator detects a phase current from a DC bus current of an inverter driving an AC motor, and generating three-phase voltage commands. The PWM signal generator generates three-phase PWM signals to the inverter according to a comparison result of the three-phase voltage commands and a triangular wave signal with a predetermined frequency and outputs the three-phase PWM signals to the inverter. The PWM signal generator corrects a maximum or minimum voltage command by synchronizing the maximum or minimum voltage command with an intermediate command in a first period of multiple consecutive PWM periods. | 2021-10-28 |
20210336578 | A SOLAR POWER PLANT AND METHOD OF INSTALLING A SOLAR POWER PLANT - A solar power plant comprising a pliable mat having a photovoltaic (PV) module fixed thereon by means of an attachment assembly which comprises at least one elongate module profile secured to an edge of the PV module, and a corresponding elongate mat profile attached to the mat, and the profiles are configured such that the PV module is secured to the mat by bringing the module profile into contact with the corresponding mat profile. There is also provided a method of installing a floating photovoltaic power plant. | 2021-10-28 |
20210336579 | Rope Transmission Structure, Solar Energy Tracker and Application Method thereof - Disclosed are a rope transmission structure, a solar energy tracker and the application method thereof, relating to the technical field of solar power generation. The rope transmission structure includes a driving wheel, a driven wheel, a main transmission rope and a plurality of tracking units. The main transmission rope is connected end to end, and one end of the main transmission rope is sleeved on the driving wheel and the other end thereof is sleeved on the driven wheel. The plurality of tracking units are provided at intervals along a lengthwise direction of the main transmission rope. A rotating member is hinged on a mounting bracket, and one end of a first branch rope is connected to the rotating member and the other end thereof is connected to the main transmission rope. | 2021-10-28 |
20210336580 | SELF-ALIGNING PANEL CLEANER - Disclosed is a self-aligning device, apparatus, and method for cleaning panels including photovoltaic panels. In an embodiment of the invention, a panel cleaner comprises a manifold, a plurality of nozzles operatively connected to the manifold, wherein the manifold supplies fluid to the plurality of nozzles, a guide comprising a hub and a plurality of spokes extending radially from the hub, wherein the guide is rotatable about an axis defined by a concentric center of the hub, and a plurality of wheels. In another embodiment of the invention, a method of cleaning an array of panels with a panel cleaner, each panel positioned adjacent to at least one other panel forming a panel gap between said panels, the steps comprising: inserting a guide spoke of a first guide within the panel gap, the guide spoke connected to a hub flange of a first hub assembly, wherein the first hub assembly is attached to a first axle; spraying pressurized fluid from a plurality of nozzles operatively connected to a manifold, the manifold offset from the first axle by an upright; and moving the panel cleaner over the surfaces of the panels in the array of panels using a plurality of wheels in a direction parallel to the panel gap in which the guide spoke is inserted. | 2021-10-28 |
20210336581 | FRESNEL LIGHT-CONCENTRATING APPARATUS AND LIGHT-CONCENTRATING SOLAR SYSTEM - A Fresnel condenser device and a condenser-type solar energy system are provided, wherein the condenser device comprises first and second Fresnel lens layers, each lens layer comprising at least one condenser-type Fresnel lens; and a straight box-shaped light guiding layer, the first and second Fresnel lens layers being disposed respectively on two ends thereof, and the straight box-shaped light guiding layer is configured to direct a light from the first Fresnel lens layer down to the second Fresnel lens layer. By utilizing two Fresnel lens layers to respectively perform light convergence and using the straight box-shaped light guiding layer therebetween to help direct the light from an upper layer to a lower layer, the condenser device can not only adapt to a wide range of incident angles, but also obtain a large light convergence ratio at a low height. | 2021-10-28 |
20210336582 | LOW COST DISPATCHABLE SOLAR POWER - A method of operating a solar energy plant and a solar plant are disclosed. Thermal energy produced in the plant is used to heat a first volume of water and charge a hot store in the plant. Electricity produced in the plant operates a heat engine or other device, such as a refrigeration unit, to extract heat and consequently cool a second volume of water and charge a cold store. As desired, energy is transferred from the hot store to a heat engine and energy is transferred from the heat engine to the cold store to operate the heat engine to produce power in the plant. | 2021-10-28 |
20210336583 | RADIO FREQUENCY OSCILLATOR - The disclosure relates to a radio frequency oscillator, the radio frequency oscillator comprising a resonator circuit being resonant at an excitation of the resonator circuit in a differential mode and at an excitation of the resonator circuit in a common mode, wherein the resonator circuit has a differential mode resonance frequency at the excitation in the differential mode, and wherein the resonator circuit has a common mode resonance frequency at the excitation in the common mode, a first excitation circuit being configured to excite the resonator circuit in the differential mode to obtain a differential mode oscillator signal oscillating at the differential mode resonance frequency, and a second excitation circuit being configured to excite the resonator circuit in the common mode to obtain a common mode oscillator signal oscillating at the common mode resonance frequency. | 2021-10-28 |
20210336584 | Source Switched Split LNA - A receiver front end amplifier capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. Further switches used for switching degeneration inductors, gate capacitors, and gate to ground capacitors for each leg can be used to further improve the matching performance of the invention. | 2021-10-28 |
20210336585 | POWER AMPLIFIER DEVICES CONTAINING FRONTSIDE HEAT EXTRACTION STRUCTURES AND METHODS FOR THE FABRICATION THEREOF - Power amplifier devices and methods for fabricating power amplifier devices containing frontside heat extraction structures are disclosed. In embodiments, the power amplifier device includes a substrate, a radio frequency (RF) power die bonded to a die support surface of the substrate, and a frontside heat extraction structure further attached to the die support surface. The frontside heat extraction structure includes, in turn, a transistor-overlay portion in direct thermal contact with a frontside of the RF power die, a first heatsink coupling portion thermally coupled to a heatsink region of the substrate, and a primary heat extraction path extending from the transistor-overlay portion to the first heatsink coupling portion. The primary heat extraction path promotes conductive heat transfer from the RF power die to the heatsink region and reduce local temperatures within a transistor channel of the RF power die during operation of the power amplifier device. | 2021-10-28 |
20210336586 | NOISE FILTERING CIRCUIT AND AN ELECTRONIC CIRCUIT INCLUDING THE SAME - A noise filtering circuit including: an amplifier which receives a reference bias through a first input terminal, generates an amplified output voltage and outputs the amplified output voltage through an output terminal, and receives an output voltage generated on the basis of the amplified output voltage through a second input terminal; a resistance component connected between the output terminal of the amplifier and the second input terminal; and a capacitor connected to the resistance component. | 2021-10-28 |
20210336587 | RF Power Amplifier Performance by Clipping Prevention of Large PAPR Signals - Preventing RF signal distortion and signal error producing memory events in a Radio Frequency (RF) power amplifier (RFPA). An element, disposed prior to the Radio Frequency (RF) power amplifier (RFPA) in a signal path of a RF signal input to the RFPA, may enforce a maximum allowable amplitude in a high PAPR instantaneous high peak of the RF signal. An element may also increase or supplement a bias of the Radio Frequency (RF) power amplifier (RFPA) when a high PAPR instantaneous high peak is detected in the RF signal prior to receipt by the RFPA. Additionally, a first element operable detects when an instantaneous output voltage of the Radio Frequency (RF) power amplifier (RFPA) is below a predetermined voltage, and in response, a second element supplies additional current to prevent the output voltage of the RFPA from falling below a predetermined threshold voltage. | 2021-10-28 |
20210336588 | RF Switch with Split Tunable Matching Network - An improved architecture for a radio frequency (RF) power amplifier, impedance matching network, and selector switch. One aspect of embodiments of the invention is splitting the functionality of a final stage impedance matching network (IMN) into two parts, comprising a base set of off-chip IMN components and an on-chip IMN tuning component. The on-chip IMN tuning component may be a digitally tunable capacitor (DTC). In one embodiment, an integrated circuit having a power amplifier, an on-chip IMN tuner, and a selector switch is configured to be coupled to an off-chip set of IMN components. In another embodiment, an integrated circuit having an on-chip IMN tuner and a selector switch is configured to be coupled through an off-chip set of IMN components to a separate integrated circuit having an RF power amplifier. | 2021-10-28 |
20210336589 | RADIO FREQUENCY POWER AMPLIFIER WITH HARMONIC SUPPRESSION - In a radio frequency power amplifier with harmonic suppression, one end of an input matching circuit is connected with a radio frequency input end; and another end is connected with a base of a power amplification transistor having a collector connected with a power supply voltage through a first matching branch, and an emitter connected with a first connection point on a package substrate. The collector of the power amplification transistor is connected with a radio frequency output end through a second matching branch that is connected with the package substrate. A harmonic control circuit has a first end connected with the collector of the power amplification transistor, and a second end connected with a second connection point on the package substrate. | 2021-10-28 |
20210336590 | CONSTANT LEVEL-SHIFT BUFFER AMPLIFIER CIRCUITS - A push-pull dynamic amplifier is operable in reset and amplification phases. The amplifier includes first NMOS and PMOS input transistors that are electrically coupled to a first input terminal and a first output terminal. Second NMOS and PMOS input transistors are electrically coupled to a second input terminal and a second output terminal. First and second reset switches are electrically coupled to the first and second output terminals, respectively. A power supply switch is electrically coupled to the first and the second PMOS transistors, and a ground switch is electrically coupled to the first and the second NMOS transistors. During the reset phase, the reset switches are closed and the power supply switch and the ground switch are opened. During the amplification phase, the reset switches are opened and the power supply switch and the ground switch are closed. | 2021-10-28 |
20210336591 | MULTI-FINGER TRANSISTOR AND POWER AMPLIFIER CIRCUIT - A multi-finger transistor includes unit transistors each including a first terminal electrically connected to a reference potential, a second terminal that receives an RF signal and a bias current, and a third terminal that outputs an amplified signal; a common input terminal electrically connected in parallel to the second terminals of the unit transistors and that receives the RF signal; a common bias terminal electrically connected in parallel to the second terminals of the unit transistors and that receives the bias current; a common output terminal electrically connected in parallel to the third terminals of the unit transistors and that outputs the amplified signal; and first resistance elements each of which is electrically connected between the common input terminal and the second terminal of a corresponding one of the unit transistors and each of which cuts a DC component of the bias current. | 2021-10-28 |
20210336592 | POWER AMPLIFIER CIRCUIT - A power amplifier circuit includes a first amplifier circuit configured to amplify a first signal of a first frequency band and output a first amplified signal having a first power, a second amplifier circuit configured to amplify a second signal of the first frequency band or a second frequency band different from the first frequency band and output a second amplified signal having a second power different from the first power, and a first variable adjustment circuit disposed between the second amplifier circuit and a first circuit subsequent to the second amplifier circuit, the first variable adjustment circuit being configured to be capable of adjusting a first impedance of the first circuit seen from the second amplifier circuit. | 2021-10-28 |
20210336593 | AMPLIFICATION INTERFACE, AND CORRESPONDING MEASUREMENT SYSTEM AND METHOD FOR CALIBRATING AN AMPLIFICATION INTERFACE - A thermally-isolated-metal-oxide-semiconducting (TMOS) sensor has inputs coupled to first and second nodes to receive first and second bias currents, and an output coupled to a third node. A tail has a first conduction terminal coupled to the third node and a second conduction terminal coupled to a reference voltage. A control circuit applies a control signal to a control terminal of the tail transistor based upon voltages at the first and second nodes so that a common mode voltage at the first and second nodes is equal to a reference common mode voltage. A differential current integrator has a first input terminal coupled to the second node and a second input terminal coupled to the first node, and provides an output voltage indicative of an integral of a difference between a first output current at the first input terminal and a second output current at the second input terminal. | 2021-10-28 |
20210336594 | MULTISTAGE VARIABLE GAIN AMPLIFIER FOR SENSOR APPLICATION - Various technologies described herein pertain to variable gain amplification for a sensor application. A multistage variable gain amplifier system provides variable gain amplification of an input signal. The multistage variable gain amplifier system includes a plurality of amplification stages. The multistage variable gain amplifier system further includes a power detector configured to detect a power level of an input signal received by the multistage variable gain amplifier system. The multistage variable gain amplifier system also includes a controller configured to control the amplification stages based on the power level of the input signal. The multistage variable gain amplifier system can output an output signal such that the amplification stages are controlled to adjust a gain applied to the input signal by the multistage variable gain amplifier system to output the output signal. | 2021-10-28 |
20210336595 | Dynamic Audio Normalization Process - Methods, systems, and apparatuses are described herein for improved processing audio in a video stream. A system may split audio in a frame of video content into multiple bands based on their audio levels. The system may then dynamically compress and dynamically normalize the audio level in each band. When dynamically compressing the bands, the system may determine, based on stored information, what audio level range is acceptable for an end user and may smooth and maintain the ranges of the audio to be within the acceptable range. The system may include the dynamically normalized and dynamically compressed frames as a second audio track in the video content. A computing device receiving the video content may select the second audio track during playback. If an end user selects the second audio track, the video is delivered with the modified sound of the second audio track. | 2021-10-28 |
20210336596 | PLANARIZATION METHOD - The invention provides a planarization method, which can make the local flatness of the product to be processed more uniform. The product has a cavity filled with oxide and includes a first electrode layer, a piezoelectric layer and a second electrode layer superposed on the cavity. The first electrode layer covers the cavity and includes a first inclined face around the first electrode layer, and the piezoelectric layer covers the first electrode layer and is arranged on the first electrode layer. The planarization method includes: depositing a passivation layer on the second electrode layer and etching the passivation layer completely until the thickness of the passivation layer is reduced to the required thickness. | 2021-10-28 |
20210336597 | CUSTOMIZABLE TUNABLE FILTERS - Customizable tunable filters are provided herein. In certain implementations, a tunable filter including: a first filter bank including a plurality of high-pass filters each having a different cutoff frequency, and a second filter bank including a plurality of low-pass filters each having a different cutoff frequency. The tunable filter further includes a first pair of switches configured to select a first filter chosen from the first filter bank, and a second pair of switches configured to select a second filter chosen from the second filter bank. The tunable filter operates with a first cutoff frequency of the first filter and with a second cutoff frequency of the second filter. | 2021-10-28 |
20210336598 | MATCHING CIRCUIT AND COMMUNICATION DEVICE - A matching circuit includes first and second ports, an autotransformer, and first and second capacitors. The autotransformer includes a first terminal coupled to a first port, a second terminal coupled to a second port, and a common terminal coupled to a reference potential, and includes a series parasitic inductor and a parallel parasitic inductor. The first capacitor is coupled in shunt to the second terminal, and defines a low pass filter together with the series parasitic inductor. The second capacitor is coupled in series between the first port and the first terminal, and defines a high pass filter together with the parallel parasitic inductor. | 2021-10-28 |
20210336599 | Resonator Device, Electronic Device, And Moving Object - A quartz crystal resonator includes a quartz crystal resonator element, a thermistor, and a package base having a first principal surface and a second principal surface having an opposed surface relationship with each other, the quartz crystal resonator element is mounted on the first principal surface side, the thermistor is housed in a recessed section of the second principal surface side of the package base, a plurality of electrode terminals connected to the quartz crystal resonator element or the thermistor is disposed on the second principal surface side of the package base, and a distance in a first direction perpendicular to the first principal surface from a mounting surface of the electrode terminals to the thermistor is equal to or longer than 0.05 mm. | 2021-10-28 |
20210336600 | VIBRATOR DEVICE AND VIBRATOR MODULE - The vibrator device includes a vibrator element, a relay substrate, a base, an element-side bonding member for bonding the vibrator element and the relay substrate to each other, and a base-side bonding member for bonding the base and the relay substrate to each other. Further, the element-side bonding member has a first bonding member and s second bonding member arranged side by side along an A axis. Further, an X axis of a first quartz crystal substrate provided to the vibrator element is parallel to the A axis, and a second quartz crystal substrate provided to the relay substrate is a Z-cut quartz crystal substrate. | 2021-10-28 |
20210336601 | METHOD OF MANUFACTURING VIBRATOR ELEMENT, VIBRATOR ELEMENT, AND VIBRATOR - A method of manufacturing a vibrator element having a vibrating part which vibrates in a thickness-shear mode, and a thin-wall part which is coupled to the vibrating part, and which is thinner than the vibrating part includes a preparation step of preparing a quartz crystal substrate, a resist film formation step of forming a resist film in a vibrating part area of the quartz crystal substrate where the vibrating part is formed, an etching step of etching the quartz crystal substrate via the resist film, then ending the etching in a state in which the resist film remains in the vibrating part area to thereby form the vibrating part and the thin-wall part, and a resist film removal step of removing the resist film remaining. | 2021-10-28 |
20210336602 | VIBRATION ELEMENT, VIBRATOR, AND METHOD FOR PRODUCING VIBRATION ELEMENT - A vibrator, a vibrating element and a method for producing the vibrating element may include vibrating piece having a central portion and a peripheral portion. The vibrator, the vibrating element and the method may further include a pair of excitation electrodes provided on a first side and a second side of a main surface of the central portion. The vibrator, the vibrating element and the method may further include a pair of connection electrodes provided on the peripheral portion and electrically connected to the pair of excitation electrodes. The vibrator, the vibrating element and the method may further include a substrate configured to be connected to the pair of connection electrodes via an electrically-conductive holding member interposed therebetween and configured to support the vibration element in an excitable manner. | 2021-10-28 |
20210336603 | FORMATION METHOD OF FILTER DEVICE - A formation method of a filter device includes: forming a first layer by providing a first substrate and forming a resonance device preprocessing layer with a first side and a second side opposite to the first side, wherein the first substrate is located on the first side; forming a second layer by providing a second substrate and forming a first passive device with a third side and a fourth side opposite to the third side, wherein the second substrate is located on the third side; connecting the first layer located on the fourth side and the second layer located on the second side; removing the first substrate; and forming at least one first resonance device based on the resonance device preprocessing layer. The resonance device and the passive device are integrated in one die to form a filter device, which requires less space in an RF front-end chip. | 2021-10-28 |
20210336604 | FILTER DEVICE, RF FRONT-END DEVICE AND WIRELESS COMMUNICATION DEVICE - A filter device, an RF front-end device and a wireless communication device are provided. The filter device includes a substrate, a passive device and at least one resonance device, wherein the passive device has a first side and a second side opposite to the first side, the substrate is located on the first side, and the at least one resonance device is located on the second side. The RF filter device formed by integrating the resonance device (such as an SAW or BAW resonance device) and the passive device (such as an IPD) can broaden the pass-band width, has a high out-of-band rejection, and occupies less space in an RF front-end chip. | 2021-10-28 |
20210336605 | FREQUENCY CONTROL OF SPURIOUS SHEAR HORIZONTAL MODE BY ADDING HIGH VELOCITY LAYER IN A LITHIUM NIOBATE FILTER - An electronic device comprises a first surface acoustic wave (SAW) resonator and a second SAW resonator, each including interleaved interdigital transducer (IDT) electrodes, the first and second SAW resonators being formed on a same piezoelectric substrate, the first SAW resonator having IDT electrodes with a different finger pitch than the IDT electrodes of the second SAW resonator; a dielectric material layer disposed on the IDT electrodes of the first and second SAW resonators; and a high velocity layer disposed within the dielectric material layer disposed on the IDT electrodes of the first SAW resonator, the second SAW resonator lacking a high velocity layer disposed within the dielectric material layer disposed on the IDT electrodes. | 2021-10-28 |
20210336606 | GLITCH FILTER HAVING A SWITCHED CAPACITANCE AND RESET STAGES - A glitch filter is provided. The glitch filter receives an input signal and sets a voltage level of an intermediary input node in accordance with a state of the input signal. The glitch filter charges or discharges a switched capacitance based on the voltage level of the intermediary input node and charges or discharges a filter capacitance based on a charge of the switched capacitance. The glitch filter sets a state of an output signal based on the charge of the filter capacitance. The glitch filter includes a reset stage that at least partially filters a burst of glitches in the input signal from the output signal by controlling the charge of the switched capacitance based on the state of the input signal and the state of the output signal. | 2021-10-28 |
20210336607 | Apparatus for Offset Cancellation in Comparators and Associated Methods - An apparatus includes a comparator. The comparator includes first and second pregain stages, and a switch network coupled to the first and second pregain stages. A plurality of switches in the switch network are operable to provide a feedback path around at least one of the first and second pregain stages. The comparator further includes a latch coupled to the second pregain stage. | 2021-10-28 |
20210336608 | SYNCHRONIZING PULSE-WIDTH MODULATION CONTROL - In described examples, a pulse width modulation (PWM) system includes an initiator and a receiver. The initiator includes an initiator counter and an initiator PWM signal generator. The initiator counter advances an initiator count in response to an initiator clock signal. The initiator PWM signal generator generates an initiator PWM signal in response to the initiator count. The receiver includes a receiver counter, a receiver PWM signal generator, and circuitry configured to reset the receiver count. The receiver counter advances a receiver count in response to a receiver clock signal. The receiver PWM signal generator generates a receiver PWM signal in response to the receiver count. The circuitry resets the receiver count in response to a synchronization signal and based on an offset. | 2021-10-28 |
20210336609 | LEVEL SHIFTER - A level shifter includes: a first inverter configured to receive an input signal in a low voltage domain and shift the input signal from the low voltage domain to a first output signal at a first output terminal in a high voltage domain higher than the low voltage domain in response to a logical high state of a first clock signal in the low voltage domain; a second inverter configured to receive a complement of the input signal and shift the complement of the input signal from the low voltage domain to a second output signal at a second output terminal in the high voltage domain in response to the logical high state; a first NMOS sensing transistor and a second NMOS sensing transistor; a PMOS transistor configured to equalize the first output signal and the second output signal in response to a logical low state of the first clock signal. | 2021-10-28 |
20210336610 | SUPERCONDUCTING LATCH SYSTEM - One example includes a superconducting latch system. The system includes a first input stage configured to receive a first input pulse and a second input stage configured to receive a second input pulse. The system also includes a storage loop configured to switch from a first state to a second state in response to receiving the first input pulse, and to switch from the second state to the first state in response to the second input pulse. The first state corresponds to no flux in the storage loop and the second state corresponds to a flux in the storage loop. The system further includes an output stage configured to generate an output pulse in the second state of the storage loop. | 2021-10-28 |
20210336611 | AREA EFFICIENT SLEW-RATE CONTROLLED DRIVER - According to certain aspects, a driver includes an output transistor coupled between a first rail and an output of the driver, a first current source coupled to a gate of the output transistor, a second current source, and a switch, wherein the switch and the second current source are coupled in series between the gate of the output transistor and a second rail. The driver also includes a current sensor configured to generate a sense current based on an output current of the driver, and a reference current source configured to generate a reference current, wherein the current sensor and the reference current source are coupled to a control input of the switch. | 2021-10-28 |
20210336612 | METHODS AND APPARATUSES FOR TEMPERATURE INDEPENDENT DELAY CIRCUITRY - Methods and apparatuses are provided for temperature independent resistive-capacitive delay circuits of a semiconductor device. For example, delays associated with ZQ calibration or timing of the RAS chain may be implemented that to include circuitry that exhibits both proportional to absolute temperature (PTAT) characteristics and complementary to absolute temperature (CTAT) characteristics in order to control delay times across a range of operating temperatures. The RC delay circuits may include a first type of circuitry having impedance with PTAT characteristics that is coupled to an output node in parallel with a second type of circuitry having impedance with CTAT characteristics. The first type of circuitry may include a resistor and the second type of circuitry may include a transistor, in some embodiments. | 2021-10-28 |
20210336613 | SYSTEM AND METHOD FOR ADJUSTING CYCLE OF A SIGNAL - A duty cycle adjustment system includes a time-to-digital converter to generate a plurality of time-to-digital codes from an input signal, a duty cycle index generator to compute a duty cycle of the input signal based upon the plurality of time-to-digital codes, and assign a duty cycle index based upon the computed duty cycle, an input phase assignment generator to generate a first output and a second output based upon the duty cycle index, a first delay line to delay the first output to generate a third output, and a duty cycle generator to adjust the duty cycle of the input signal based upon the third output and the second output. | 2021-10-28 |
20210336614 | Apparatus for Offset Cancellation in Comparators and Associated Methods - An apparatus includes a comparator. The comparator includes a plurality of pregain stages, and a switch network coupled to the plurality of pregain stages. The comparator further includes a latch coupled to the plurality of pregain stages. | 2021-10-28 |
20210336615 | PWM WAVEFORM GENERATION DEVICE AND METHOD THEREOF - The PWM waveform generation device comprises a time-division multiplexing module, wherein the time-division multiplexing module is configured for receiving a first preprocessing signal and a second preprocessing signal output by two system clock sources, performing a first time-division processing on the first preprocessing signal to obtain a first time-division signal, and performing a second time-division processing on the second preprocessing signal to obtain a second time-division signal according to a preset strategy, performing multiplexing processing on the first time-division signal and the second time-division signal to obtain a PWM output signal, wherein an output frequency of the PWM output signal is a default standard clock frequency. The present invention has the advantages that the cycle length of one cycle of a PWM waveform depends on cycles of two preprocessing waveforms and the number of the cycles, such that the output waveform frequency may be calibrated to a desired frequency. | 2021-10-28 |
20210336616 | GATE DRIVE CONTROL METHOD FOR SiC AND IGBT POWER DEVICES TO CONTROL DESATURATION OR SHORT CIRCUIT FAULTS - A gate-drive controller for a power semiconductor device includes a master control unit (MCU) and one or more comparators that compare the output signal of the power semiconductor device to a reference value generated by the MCU. The MCU, in response to a turn-off trigger signal, generates a first intermediate drive signal for the power semiconductor device and generates a second intermediate drive signal, different from the first drive signal, when a DSAT signal indicates that the power semiconductor device is experiencing de-saturation. The MCU generates a final drive signal for the power semiconductor when the output signal of the one or more comparators indicates that the output signal of the power semiconductor device has changed relative to the reference value. The controller may also include a timer that causes the drive signals to change in predetermined intervals when the one or more comparators do not indicate a change. | 2021-10-28 |
20210336617 | MILLER CLAMP DRIVE CIRCUIT - The present invention provides a Miller clamp drive circuit, including a drive chip which includes an output terminal configured to output a driving signal, a clamp terminal, a power terminal and a controllable switch connected between the clamp terminal and the power terminal; a drive resistor, one terminal of which is connected to the output terminal of the drive chip and the other terminal of which is used to connect to a control electrode of a power switching transistor; and a Miller clamp circuit including a first voltage divider circuit which is connected between the other terminal of the drive resistor and the clamp terminal and configured to have a preset voltage drop, and a second voltage divider circuit connected between the clamp terminal and the power terminal. The Miller clamp drive circuit of the present invention increases the Miller clamp voltage and decreases the tailing time of the power switching transistor. | 2021-10-28 |
20210336618 | Gate drive apparatus control method - An apparatus includes a capacitive device configured to provide bias power for a high-side switch, a gate drive path having variable resistance connected between the capacitive device and a gate of the high-side switch, wherein the gate drive path having variable resistance is of a first resistance value in response to a turn-on of the high-side switch, and the gate drive path having variable resistance is of a second resistance value in response to a turn-off of the high-side switch, and wherein the second resistance value is greater than the first resistance value, and a control switch connected between the gate of the high-side switch and ground. | 2021-10-28 |
20210336619 | TOUCHLESS TRIGGER APPARATUS - A touchless trigger apparatus is touchless button, comprising a photon-gate side, a photon-gate distal side more than 1 cm (11.0 in) and less than 30 cm (11.0 in) across the photon-gate opening, to the photon-gate side. An electro-optical sensor is connected to the photon-gate side. An ASIC controller is connected to the output of the electro-optical sensor. Lastly a button face is within the opening of the photon gate. Alternatively, a touchless trigger apparatus is a touchless pushbutton, or a touchless switch. Any person or primate trained to use a button, pushbutton or switch could intuitively learn to use a touchless trigger apparatus due to its recognizable combination of elements and low-latency feedback before touching the button, the pushbutton or the switch. | 2021-10-28 |
20210336620 | Self Timed Level Shifter Circuit - Systems and methods are provided for a level shifter. A level shifter includes a network of transistors configured to receive a signal at a first node in a first voltage domain and to generate a corresponding signal at a second node in a second voltage domain during a transition period of time. A self timing circuit is configured to receive an initiation signal based on the signal at the first node and to generate a voltage transition accelerator signal that is used to pull up the second node prior to the expiration of the transition period of time. | 2021-10-28 |
20210336621 | METHOD AND ARRANGEMENT FOR READING OUT THE STATE OF A QUBIT - For reading out a state of a qubit, a readout input waveform is injected into a system that comprises an information storage element for storing the state of the qubit and a readout resonator that is electromagnetically coupled to said information storage element. A readout output waveform is extracted from said system and detected. The injection of the readout input waveform takes place through an excitation port that is also used to inject excitation waveforms to the information storage element for affecting the state of the qubit. A phase of the readout input waveform is controllably shifted in the course of injecting it into the system. | 2021-10-28 |
20210336622 | COMPUTE DATAFLOW ARCHITECTURE - An example integrated circuit includes an array of circuit tiles; interconnect coupling the circuit tiles in the array, the interconnect including interconnect tiles each having a plurality of connections that include at least a connection to a respective one of the circuit tiles and a connection to at least one other interconnect tile; and a plurality of local crossbars in each of the interconnect tiles, the plurality of local crossbars coupled to form a non-blocking crossbar, each of the plurality of local crossbars including handshaking circuitry for asynchronous communication. | 2021-10-28 |
20210336623 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM - A semiconductor device includes a clock generator which receives an input clock and generates an output clock, a reference voltage generator which receives the input clock or the output clock, generates a sub-reference voltage in accordance with a frequency of the input clock or a frequency of the output clock, and generates a reference voltage using the sub-reference voltage and a preset error voltage, and a clock detector which receives the output clock, generates a first output voltage in accordance with the output clock, and compares the generated first output voltage with the reference voltage to output an error signal based on the output clock, wherein the preset error voltage is set in accordance with a degree of preset error of the output clock. | 2021-10-28 |
20210336624 | VOLTAGE-CONTROLLED OSCILLATOR CALIBRATION - A computer system may periodically calibrate an oscillator subsystem, which includes a voltage-controlled oscillator circuit configured to generate an oscillator signal using code signal. In response to activation of a calibration mode, an iterative calibration operation may be performed on the voltage-controlled oscillator circuit. In some cases, performing a given iteration of the calibration operation includes determining a value of the code signal using a number of pulses in the oscillator signal sampled during a particular time period, along with previous values of the code signal and a slope of an error function associated with the difference between a desired frequency and a current frequency of the oscillator signal. In other cases, iterations may employ variable sampling times with error handling, in order to decrease the duration of the calibration operation while maintaining a target accuracy. | 2021-10-28 |
20210336625 | Method and Apparatus for Generating Output Frequency Locked to Input Frequency - A digitally controlled oscillator (DCO) that generates an output frequency clock signal without drift and can be rapidly locked to an input or reference clock is described. A variable-modulus-fixed-increment form of DCO is configured to divide the frequency of a nominally fixed frequency oscillator. A constant is derived from the ratio of a fixed increment to the desired output frequency; this constant is multiplied by the frequency of the oscillator and the modulus adjusted to keep the ratio of the input clock and the output clock constant. The frequency of the oscillator is conveniently measured by counting the number of cycles between input cycles of a reference frequency. The oscillator must be greater in frequency than the expected output and is most accurate in cases where the reference frequency is low compared to the expected output frequency. | 2021-10-28 |
20210336626 | TECHNIQUE FOR SMOOTHING FREQUENCY TRANSITIONS DURING CLOCK DITHERING - An apparatus includes a power converter circuit configured to generate a voltage level on a regulated power supply node using a clock signal, and a clock generation circuit configured to dither a frequency of the clock signal. To transition from a first frequency to a second frequency, the clock generation circuit is configured to change, during an initial transition period, the clock signal between the first and second frequencies such that a particular percentage of clock pulses have the second frequency. During one or more intermediate transition periods, the clock generation circuit is configured to change the clock signal between the first and second frequencies such that a percentage of clock pulses having the second frequency increases relative to a prior transition period. During a final transition period of the series, the clock generation circuit is configured to set the frequency of the clock signal to the second frequency. | 2021-10-28 |
20210336627 | VARIABLE RESOLUTION DIGITAL EQUALIZATION - A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing. | 2021-10-28 |
20210336628 | HYBRID DIGITAL AND ANALOG SIGNAL GENERATION SYSTEMS AND METHODS - An analog signal generating source comprising two or more digital-to-analog converters (DAC) combined to generate one or more frequency components. The analog signal source comprises a first path for generating substantially low frequency signals, the first path comprising a first one of the DACs; and a second path for generating substantially high frequency signals, the second path comprising a second one of the DACs. The analog signal source also comprises a data processor for processing an input signal and providing the processed input signal to the first and second paths; a combining circuit configured to combine outputs of the first and second paths into the source signal; a feedback portion configured to sense the source signal; and a servo loop configured to use the sensed source signal to adjust as need to maintain the source signal to substantially agree with the input signal. | 2021-10-28 |
20210336629 | RANGING SYSTEMS AND METHODS FOR DECREASING TRANSITIVE EFFECTS IN MULTI-RANGE MATERIALS MEASUREMENTS - A measurement system includes a gain chain configured to amplify an analog input signal; a range selector configured to select a gain between the analog input signal and a plurality of analog-to-digital converter (ADC) outputs from a plurality of ADCs, wherein each ADC output has a path, and a gain of each output path is made up of a plurality of gain stages in the gain chain; and a mixer configured to combine the plurality of ADC outputs into a single mixed output. | 2021-10-28 |
20210336630 | ANALOG-TO-DIGITAL CONVERTER WITH INTERPOLATION - An analog-to-digital converter (ADC) including: a signal input adapted to receive an analog signal; a first reference voltage input adapted to receive a first reference voltage; a second reference voltage input adapted to receive a second reference voltage, the second reference voltage is different than the first reference voltage; a first delay circuit having a first delay input coupled to the signal input, a second delay input coupled to the first reference voltage input, a first delay output and a second delay output; a second delay circuit having a third delay input coupled to the signal input, a fourth delay input coupled to the second reference voltage input; a third delay output and a fourth delay output; a first comparator having a first comparator input coupled to the first delay output, a second comparator input coupled to the second delay output and a first comparator output; and a second comparator having a third comparator input coupled to the third delay output, a fourth comparator input coupled to the fourth delay output and a second comparator output. | 2021-10-28 |