46th week of 2015 patent applcation highlights part 54 |
Patent application number | Title | Published |
20150325223 | GUITAR-SECURING DEVICE - Guitar-securing device characterized in that it comprises an element for fastening to a surface, which has an arm, a structural element, connected to said arm, and that runs via the rear part of the guitar, said structural element having at least a first element for connection to a first stud for a strap of said guitar and/or an element for joining to the neck of the guitar. | 2015-11-12 |
20150325224 | PEDALBOARD SUPPORT FOR ELECTRIC INSTRUMENTS - A pedalboard support for electric instruments of the type comprising at least two parallel longitudinal sections, each longitudinal section having a top surface to support pedals and an under surface, characterised in that each section comprises at least two grooves forming open channels to receive attachment means, the support further comprising at least two end pieces, each of the pieces joining the longitudinal sections at one of their ends through attachment means. | 2015-11-12 |
20150325225 | METHOD FOR MUSICAL COMPOSITION, MUSICAL COMPOSITION PROGRAM PRODUCT AND MUSICAL COMPOSITION SYSTEM - A musical composition method, a musical composition program product, and a musical composition system are disclosed in the invention. The composition method comprises two main steps: a pitch input step enables the user to enter pitch symbols that displayed on a display device; a beat input step that provides the user a prompt signal on each beat based on predetermined tempo enables the user to input action signals based on desired rhythm. The time points of action signals are assigned as the time points for the corresponding pitch symbols. After assigning their time points, the pitch symbols are regarded as completed notes and form a song. The composition program product can be executed on an electronic device, performing the steps of the aforesaid composition method. The composition system utilizes a pitch input interface and a beat input interface on an electronic device to provide musical composition functions. | 2015-11-12 |
20150325226 | SYSTEMS AND METHODS FOR PROVIDING IMMERSIVE AUDIO EXPERIENCES IN COMPUTER-GENERATED VIRTUAL ENVIRONMENTS - Described herein are systems and method for providing an immersive audio experience in a computer-generated virtual environment. An audio-mixer is placed at a location in a domain of the virtual environment and receives a separate audio feed from each of the audio source nodes directly connected to the audio-mixer. The audio-mixer mixes the received audio feeds in dependence on corresponding location, position and intrinsic loudness information to generate a separate spatialized mixed audio feed for each of the directly connected audio listener nodes. The audio-mixer sends, to each of the audio listener nodes directly connected to the audio-mixer, the separate spatialized mixed audio feed generated for the audio listener. An audio-mixer also receives and sends non-spatialized mixed audio feeds to/from other audio-mixers. The location of the audio-mixer is preferably moved to account for audio source nodes moving and/or changes to which audio source nodes are directly connected to the audio-mixer. | 2015-11-12 |
20150325227 | WHISTLE ASSEMBLY - A whistle assembly may include a main body, a cord insert, and a cord. The main body may include a mouth-receiving end connected to a cord end. A channel may be formed through at least a portion of the cord end. The cord insert may include a housing having a cord passage. The cord insert is retained within the channel of the main body. The cord has an end that is securely retained within the cord passage of the cord insert that is within the channel of the main body. | 2015-11-12 |
20150325228 | ULTRASONIC TRANSDUCER USING FERROELECTRIC POLYMER - An ultrasound transducer includes a highly crystalline film, an upper electrode, a lower electrode, a first low melting point polymer film disposed between the highly crystalline film and the upper electrode, and a second low melting point polymer film disposed between the highly crystalline film and the lower electrode. | 2015-11-12 |
20150325229 | Dynamically Configurable ANR Filter Block Topology - An active noise reduction (ANR) circuit includes a digital feed-forward ANR pathway coupled to a feed-forward microphone, to detect environmental sounds in an environment external to a casing, and to a first acoustic driver to output sounds within the casing. The digital feed-forward ANR pathway applies a plurality of filters using a first set of coefficients to convert signals from the feed-forward microphone to feed-forward anti-noise sounds to reduce environmental sounds within the casing. In response to a stimulus, the digital feed-forward ANR pathway applies the plurality of filters using a second set of coefficients, which reduce the degree of feed-forward ANR to enable human speech sounds in the environment external to the casing to be conveyed from the feed-forward microphone to the acoustic driver with less reduction than provided by the first plurality of filters. | 2015-11-12 |
20150325230 | AUDIO PROCESSING DEVICE, METHOD, AND PROGRAM - Provided is an audio processing device including a narration canceling section configured to generate a narration canceling signal by removing a narration component from an input signal, and a reverberation adding section configured to add a reverberation effect to the narration canceling signal. | 2015-11-12 |
20150325231 | FACILITATING TEXT-TO-SPEECH CONVERSION OF A DOMAIN NAME OR A NETWORK ADDRESS CONTAINING A DOMAIN NAME - To facilitate text-to-speech conversion of a username, a first or last name of a user associated with the username may be retrieved, and a pronunciation of the username may be determined based at least in part on whether the name forms at least part of the username. To facilitate text-to-speech conversion of a domain name having a top level domain and at least one other level domain, a pronunciation for the top level domain may be determined based at least in part upon whether the top level domain is one of a predetermined set of top level domains. Each other level domain may be searched for one or more recognized words therewithin, and a pronunciation of the other level domain may be determined based at least in part on an outcome of the search. The username and domain name may form part of a network address such as an email address, URL or URI. | 2015-11-12 |
20150325232 | SPEECH SYNTHESIZER, AUDIO WATERMARKING INFORMATION DETECTION APPARATUS, SPEECH SYNTHESIZING METHOD, AUDIO WATERMARKING INFORMATION DETECTION METHOD, AND COMPUTER PROGRAM PRODUCT - According to an embodiment, a speech synthesizer includes a source generator, a phase modulator, and a vocal tract filter unit. The source generator generates a source signal by using a fundamental frequency sequence and a pulse signal. The phase modulator modulates, with respect to the source signal generated by the source generator, a phase of the pulse signal at each pitch mark based on audio watermarking information. The vocal tract filter unit generates a speech signal by using a spectrum parameter sequence with respect to the source signal in which the phase of the pulse signal is modulated by the phase modulator. | 2015-11-12 |
20150325233 | METHOD AND SYSTEM FOR ACHIEVING EMOTIONAL TEXT TO SPEECH - A method and system for achieving emotional text to speech. The method includes: receiving text data; generating emotion tag for the text data by a rhythm piece; and achieving TTS to the text data corresponding to the emotion tag, where the emotion tags are expressed as a set of emotion vectors; where each emotion vector includes a plurality of emotion scores given based on a plurality of emotion categories. A system for the same includes: a text data receiving module; an emotion tag generating module; and a TTS module for achieving TTS, wherein the emotion tag is expressed as a set of emotion vectors; and wherein emotion vector includes a plurality of emotion scores given based on a plurality of emotion categories. | 2015-11-12 |
20150325234 | Systems and Methods for Configuring Matching Rules Related to Voice Input Commands - Systems, devices and methods are provided for configuring matching rules related to voice input commands. For example, a first mapping relation between one or more first original terms in a preset term database and one or more first identification terms is established; the first mapping relation is stored in a first mapping relation table; one or more first voice input commands are configured for the first identification terms or one or more first statements including the first identification terms; and a second mapping relation between the first identification terms or the first statements and the first voice input commands is stored into a second mapping relation table. | 2015-11-12 |
20150325235 | Language Model Optimization For In-Domain Application - Systems and methods are provided for optimizing language models for in-domain applications through an iterative, joint-modeling approach that expresses training material as alternative representations of higher-level tokens, such as named entities and carrier phrases. From a first language model, an in-domain training corpus may be represented as a set of alternative parses of tokens. Statistical information determined from these parsed representations may be used to produce a second (or updated) language model, which is further optimized for the domain. The second language model may be used to determine another alternative parsed representation of the corpus for a next iteration, and the statistical information determined from this representation may be used to produce a third (or further updated) language model. Through each iteration, a language model may be determined that is further optimized for the domain. | 2015-11-12 |
20150325236 | CONTEXT SPECIFIC LANGUAGE MODEL SCALE FACTORS - The customization of recognition of speech utilizing context-specific language model scale factors is provided. Training audio may be received from a source in a training phase. The received training audio may be recognized utilizing acoustic and language models being combined utilizing static scale factors. A comparison may then be made of the recognition results to a transcription of the training audio. The recognition results may include one or more hypotheses for recognizing speech. Context specific scale factors may then be generated based on the comparison. The context specific scale factors may then be applied for use in the speech recognition of audio signals in an application phase. | 2015-11-12 |
20150325237 | USER QUERY HISTORY EXPANSION FOR IMPROVING LANGUAGE MODEL ADAPTATION - Query history expansion may be provided. Upon receiving a spoken query from a user, an adapted language model may be applied to convert the spoken query to text. The adapted language model may comprise a plurality of queries interpolated from the user's previous queries and queries associated with other users. The spoken query may be executed and the results of the spoken query may be provided to the user. | 2015-11-12 |
20150325238 | Voice Recognition Method And Electronic Device - A voice recognition method and an electronic device are described. The method is applicable in an electronic device having a voice recognition system. The method includes acquiring first voice information of a user; recognizing the first voice information on the basis of a first recognition file library, acquiring a first recognition result, where the first recognition file library is a recognition file library updated from a second recognition file library of the voice recognition system on the basis of usage information expressing usage and syntax habits of the user, the first recognition file library includes an M-number of recognition entries, the second recognition file library includes an N-number of recognition entries, where M is an integer greater than or equal to one, and N is an integer greater than or equal to one. | 2015-11-12 |
20150325239 | DEVICES AND SYSTEMS FOR REMOTE CONTROL - Remote controllers and systems thereof are disclosed. The remote controller remotely operates a receiving host, in which the receiving host provides voice input and speech recognition functions. The remote controller comprises a first input unit and a second input unit for generating a voice input request and a speech recognition request. The generated voice input and speech recognition requests are then sent to the receiving host, thereby forcing the receiving host to perform the voice input and speech recognition functions. | 2015-11-12 |
20150325240 | METHOD AND SYSTEM FOR SPEECH INPUT - Inputting speech includes receiving feature information obtained by a client, the feature information comprising speech signals and user feature image signals, recognizing first candidate recognition data matching the user feature image signals, determining target recognition data based at least on the first candidate recognition data, and outputting the target recognition data. | 2015-11-12 |
20150325241 | METHOD FOR PROCESSING DATA AND ELECTRONIC DEVICE THEREOF - An operation method of an electronic device is provided. The method includes detecting audio information from all or some of media data, determining a setting duration as at least one duration which satisfies a reference condition using the audio information, and displaying the setting duration on a display. | 2015-11-12 |
20150325242 | SOUND TRANSMISSION-BASED VERIFICATION METHOD - A sound transmission-based verification method comprises: a client receiving a data packet set generated by a server according to request information, and converting the data packet set into audio data and play the audio data; a dynamic password apparatus collecting the audio data played by the client, decoding the audio data to obtain data information, and when the information is integral, generating and outputting display information; after the client receives a dynamic password, the client sending the dynamic password to the server; and the server generating, according to the request information, a verifying dynamic password to verify whether the dynamic password is valid, and if the dynamic password is valid, performing an operation according to the request information. | 2015-11-12 |
20150325243 | AUDIO ENCODER AND DECODER WITH PROGRAM LOUDNESS AND BOUNDARY METADATA - Apparatus and methods for generating an encoded audio bitstream, including by including program loudness metadata and audio data in the bitstream, and optionally also program boundary metadata in at least one segment (e.g., frame) of the bitstream. Other aspects are apparatus and methods for decoding such a bitstream, e.g., including by performing adaptive loudness processing of the audio data of an audio program indicated by the bitstream, or authentication and/or validation of metadata and/or audio data of such an audio program. Another aspect is an audio processing unit (e.g., an encoder, decoder, or post-processor) configured (e.g., programmed) to perform any embodiment of the method or which includes a buffer memory which stores at least one frame of an audio bitstream generated in accordance with any embodiment of the method. | 2015-11-12 |
20150325244 | SYSTEM, MEDIUM, AND METHOD OF ENCODING/DECODING MULTI-CHANNEL AUDIO SIGNALS - An system, method, and method of encoding/decoding a multi-channel audio signal, including a decoding level generation unit producing decoding-level information that helps a bitstream including a number of audio channel signals and space information to be decoded into a number of audio channel signals, wherein the space information includes information about magnitude differences and/or similarities between channels, and an audio decoder decoding the bitstream according to the decoding-level information. Accordingly, even a single input bitstream can be decoded into a suitable number of channels depending on the type of a speaker configuration used. Scalable channel decoding can be achieved by partially decoding an input bitstream. In the scalable channel decoding, a decoder may set decoding levels and outputs audio channel signals according to the decoding levels, thereby reducing decoding complexity. | 2015-11-12 |
20150325245 | LOUDSPEAKER BEAMFORMING - In one embodiment, a method comprising receiving at a microphone located at a first location audio received from plural speakers, the audio received at a first amplitude level; and responsive to moving the microphone away from the first location to a second location, causing adjustment of the audio provided by the plural speakers to target the first amplitude level at the microphone. | 2015-11-12 |
20150325246 | REVERSIBLE AUDIO DATA HIDING - The present invention provides a method of reversible audio data hiding. The method of data hiding and restoring comprises the steps of: protecting audio by embedding information into the audio according to variance calculation associated to the audio, wherein the quality of the protected audio is degraded after embedding the information into the audio; publishing the protected audio widely as a trial for listen version; and decoding the protected audio for a user who purchased the copyright of the audio by extracting the original audio from the protected audio. | 2015-11-12 |
20150325247 | Semiconductor Device, Radio Communication Terminal Using the Same, and Control Method - A communication terminal according to one aspect of the present invention includes a baseband LSI that performs baseband processing for communication, an application LSI that includes a vocoder function and performs processing according to an application, an audio LSI that performs one of D/A conversion and A/D conversion on audio data, and a switch circuit that is installed in the application LSI and connects a data path between the audio processor LSI and the baseband LSI. | 2015-11-12 |
20150325248 | SYSTEM AND METHOD FOR PROSODICALLY MODIFIED UNIT SELECTION DATABASES - Systems, methods, and computer-readable storage devices to improve the quality of synthetic speech generation. A system selects speech units from a speech unit database, the speech units corresponding to text to be converted to speech. The system identifies a desired prosodic curve of speech produced from the selected speech units, and also identifies an actual prosodic curve of the speech units. The selected speech units are modified such that a new prosodic curve of the modified speech units matches the desired prosodic curve. The system stores the modified speech units into the speech unit database for use in generating future speech, thereby increasing the prosodic coverage of the database with the expectation of improving the output quality. | 2015-11-12 |
20150325249 | Reverse Hearing Aid [RHA] - Method and apparatus for speech aid for use in treating speech impaired individuals utilizing a Throat Microphone paired with a wireless communications device, with or without Bluetooth pairing capability; or a portable device, which will capture low energy sound waves from speech impaired individuals, transmitted wirelessly to be reproduced from a speaker, and stored for future use through a recording device and utilizing speech to text. | 2015-11-12 |
20150325250 | METHOD AND APPARATUS FOR PRE-PROCESSING SPEECH TO MAINTAIN SPEECH INTELLIGIBILITY - An audio system processes a speech signal to maintain a target value of the speech intelligibility index (SII) while minimizing the overall speech level so that speech intelligibility is preserved across different environmental sound levels while possible distortions and overall loudness are mitigated. In one embodiment, a hearing aid processes a speech signal received from another device to maintain a target value of the SII while minimizing the overall speech level before mixing the speech signal with a microphone signal. | 2015-11-12 |
20150325251 | SYSTEM AND METHOD FOR AUDIO NOISE PROCESSING AND NOISE REDUCTION - Electronic system for audio noise processing and noise reduction comprises: first and second noise estimators, selector and attenuator. First noise estimator processes first audio signal from voice beamformer (VB) and generate first noise estimate. VB generates first audio signal by beamforming audio signals from first and second audio pick-up channels. Second noise estimator processes first and second audio signal from noise beamformer (NB), in parallel with first noise estimator and generates second noise estimate. NB generates second audio signal by beamforming audio signals from first and second audio pick-up channels. First and second audio signals include frequencies in first and second frequency regions. Selector's output noise estimate may be a) second noise estimate in the first frequency region, and b) first noise estimate in the second frequency region. Attenuator attenuates first audio signal in accordance with output noise estimate. Other embodiments are also described. | 2015-11-12 |
20150325252 | METHOD AND DEVICE FOR ELIMINATING NOISE, AND MOBILE TERMINAL - A method and device for eliminating noise, and a mobile terminal. The method comprises: extracting, from the voice of a talker, an audio fingerprint of the talker voice in advance ( | 2015-11-12 |
20150325253 | SPEECH ENHANCEMENT DEVICE AND SPEECH ENHANCEMENT METHOD - A speech enhancement device which includes: a speech production section detection unit configured to detect a speech production section in which a speaker produces speech, from an input signal generated by a speech input unit; a timer unit configured to measure an elapsed time from a starting point of the speech production section; a gain determination unit configured to determine a gain, which represents a level of enhancement of the input signal, according to the elapsed time; and an enhancement unit configured to enhance the input signal or a spectrum signal of the input signal in the speech production section according to the gain, whereby the input signal is enhanced only at necessary portions thereof. | 2015-11-12 |
20150325254 | METHOD AND APPARATUS FOR DISPLAYING SPEECH RECOGNITION INFORMATION - A method and an apparatus for displaying speech recognition information are provided. The method includes acquiring at least one of speech recognition information based on speech recognized by performing speech recognition, and response information indicating a processing result of the speech recognition information, displaying a speech recognition history list including the acquired information, in a first window region, selecting at least one of the acquired information included in the speech recognition history list, and updating response information corresponding to the selected at least one piece of acquired information. | 2015-11-12 |
20150325255 | METHOD OF PROVIDING DYNAMIC SPEECH PROCESSING SERVICES DURING VARIABLE NETWORK CONNECTIVITY - A user device provides dynamic speech processing services during variable network connectivity with a network server. The user device includes a monitor that monitors a level of network connectivity between the user device and the network server. A user device speech processor processes speech data and is initiated based on a determination that the level of network connectivity between the user device and the network server is impaired. The monitor determines when the level of network connectivity between the user device and the network server is no longer impaired. | 2015-11-12 |
20150325256 | METHOD AND APPARATUS FOR DETECTING VOICE SIGNAL - The invention discloses a method including: performing in a unit of first timeframe frame length, framing on a continuous voice sample to obtain a plurality of first timeframes, detecting energy of each of the first timeframes, and determining a target first timeframe including a potential abrupt exception of a voice signal by analyzing a relationship between the energy of the plurality of first timeframes; performing, in a unit of second timeframe frame length, framing on the continuous voice sample to obtain a plurality of second timeframes, and processing each of the second timeframes to acquire a tone feature, and determining, by analyzing a tone feature of at least one of the second timeframes including at least one target second timeframe, whether the potential abrupt exception of a voice signal included in the target first timeframe included in the target second timeframe is a real abrupt exception of a voice signal. | 2015-11-12 |
20150325257 | SYSTEMS AND METHODS FOR READING DATA FROM A STORAGE MEDIUM - A system for reading data from a storage medium. The system includes a reader and a data determination circuit. The reader is configured to receive a first signal from a first position relative to the storage medium and read a second signal from a second position relative to the storage medium. Each of the first signal and the second signal includes a combination of first data stored in a first track and second data stored in a second track. The data determination circuit is configured to determine third data stored at a predetermined position using the combination of the first data stored in the first track and the second data stored in the second track as received in the first signal and the combination of the first data stored in the first track and the second data stored in the second track as received in the second signal. | 2015-11-12 |
20150325258 | STIFF DISCRETE INSERT ARRAY FOR THERMAL PTR MANAGEMENT WITH DESIRED INDUCED STRESS STATE THAT REDUCES TENDENCY FOR WRITE POLE ERASURE - Embodiments of the present invention generally relate to a magnetic device having a discontinuous array of columns disposed near a magnetic pole. Each column has a length extending perpendicular to an air bearing surface and a width. The length is greater than the width. | 2015-11-12 |
20150325259 | High Coercivity Magnetic Film for Use as Hot Seed in a Magnetic Write Head and Method to Grow it - A sub-structure, suitable for use as a hot seed on which to form a perpendicular magnetic main write pole, is described. It is made up of a buffer layer of atomic layer deposited alumina on which there are one or more seed layers having a body-centered cubic (bcc) crystal structure. Finally, a magnetic film made of FeCo or FeNi with an as deposited coercivity of 60-110 Oe lies on the seed layer(s). Coercivity is lowered somewhat after the annealing step. It is critical that the high coercivity magnetic film be deposited at a very low deposition rate of around 1 Angstrom per second. The magnetic film is preferably annealed at 220° C. for 2 hours in a 250 Oe applied magnetic field. | 2015-11-12 |
20150325260 | SENSOR STACK STRUCTURE - A reader stack, such as for a magnetic storage device, the stack having a top synthetic antiferromagnetic (SAF) layer, a magnetic capping layer adjacent to the top SAF layer, an RKKY coupling layer adjacent to the magnetic capping layer opposite the top SAF layer, and a free layer adjacent to the RKKY coupling layer opposite the magnetic capping layer. Also included is a method for biasing a free layer in a reader stack by providing an exchange coupling between the free layer and a top synthetic antiferromagnetic (SAF) layer using a layer having RKKY coupling property positioned between the free layer and the top SAF layer and a magnetic capping layer between the SAF layer and the layer having RKKY coupling property. | 2015-11-12 |
20150325261 | OPTICAL REFLECTORS FOR USE WITH A NEAR-FIELD TRANSDUCER - An apparatus is includes a near field transducer positioned adjacent a media-facing surface and at the end of a waveguide having at least one core layer and a cladding layer. The apparatus also includes at least one optical reflector positioned adjacent opposing cross-track edges of the near field transducer and/or adjacent a down-track side of the near-field transducer. | 2015-11-12 |
20150325262 | DEVICE AND METHOD FOR CONTROLLING THE POSITION OF A HEAD RELATIVE TO A TAPE WITHIN A TAPE TRANSPORT SYSTEM - Controlling the position of a head within a tape transport system. A track-follow control system (TFCS) includes a controller device for generating a control signal as a function of a position error signal (PES), wherein the PES indicates a difference between the actual and target positions of the head relative to the tape, and an actuator for changing the actual position. The TFCS is adapted to select a controller device configuration from a plurality of configurations dependent on an operating tape speed. The configurations are predetermined depending on a vibration frequency domain profile indicative of environmental vibrations induced to the head and tape to determine the control signal for adjusting an actuator output signal relative to a lateral tape motion signal. The TFCS is also adapted to feed-back a signal depending on a difference of the actuator output signal and the lateral tape motion signal to generate the PES. | 2015-11-12 |
20150325263 | SLIDER AND/OR HARD DISC INCLUDING COATING, AND OPTIONALLY ONE OR MORE ADDITIVES THAT CAN DISSIPATE ELECTRICAL CHARGE - The present disclosure relates to reducing a potential difference among a slider body and a hard disc drive platter by providing a hard disc drive platter and/or slider body with a coating that includes one or more additives that can dissipate electrical charge. | 2015-11-12 |
20150325264 | METHOD USING EPITAXIAL TRANSFER TO INTEGRATE HAMR PHOTONIC INTEGRATED CIRCUIT (PIC) INTO RECORDING HEAD WAFER - Embodiments of the present invention generally relate to a method for forming a HAMR device having a photonic integrated circuit that includes an optical detector, an optical emitter, and an optical element distinct from the optical detector and the optical emitter, where the elements of the photonic integrated circuit are aligned with a near field transducer. The method includes forming one or more layers on a substrate, bonding the layers to a partially fabricated recording head, removing the substrate using epitaxial lift-off, and forming the optical elements on the partially fabricated recording head. | 2015-11-12 |
20150325265 | MAGNETIC TAPE DEVICE AND METHOD FOR CONTROLLING MAGNETIC TAPE DEVICE - A magnetic tape device, includes: a base member movable in a front-back direction of a cabinet; a tape drive mounted rotatably to the base member at least between a first position facing a front surface of the cabinet and a second position facing a side surface of the cabinet; and a rotation unit configured to rotate the tape drive from the first position to the second position when a magazine detachably containing a magnetic tape cartridge is inserted into the cabinet, and to rotate the tape drive from the second position to the first position when the magazine is removed from the cabinet. | 2015-11-12 |
20150325266 | Multi-Dimensional Optimization of Read Channel - Variations of the Nelder-Mead direct search method are employed to find read channel parameter settings in a discrete field having three or more dimensions. The three or more dimensions correspond to read channel parameters, at least some of which are highly correlated. The steps of the Nelder-Mead method are executed according to a methodology to arrive at substantially optimal parameter settings for a read channel, even where a discrete function defining parameter outcomes is noisy. In some embodiments, dimensional collapse, considered inefficient in a two-dimensional field, is allowed in order to reach an optimal solution in a greater-than-two-dimensional field. | 2015-11-12 |
20150325267 | SYSTEM AND METHOD OF SMART AUDIO LOGGING FOR MOBILE DEVICES - A mobile device that is capable of automatically starting and ending the recording of an audio signal captured by at least one microphone is presented. The mobile device is capable of adjusting a number of parameters related with audio logging based on the context information of the audio input signal. | 2015-11-12 |
20150325268 | DOWNLOADING VIDEOS WITH COMMERCIALS TO MOBILE DEVICES - Among other things, a video is downloaded to a mobile device. The video includes a TV show and commercials embedded within the TV show. The video is stored persistently on the mobile device. At least part of the video is played on the mobile device while the device is offline. Metadata is stored on the mobile device that indicates an expiry applicable to at least one of the commercials embedded in the video. The mobile device performs an action at a time related to the expiry. | 2015-11-12 |
20150325269 | Synchronisation of Audio and Video Playback - A method of playing audio content to a viewer in synchronisation with a video content. The method comprises receiving and digitising an ultrasonic signal comprising ultrasonic synchronisation signal(s), the ultrasonic synchronisation signal(s) comprising a timecode-carrying part that encodes a respective timecode through modulation of ultrasonic carrier signal(s), the ultrasonic synchronisation signal(s) comprising further an ultrasonic marker signal conterminous with the timecode-carrying part. The timecode-carrying part is identified based on a received ultrasonic marker signal and decoded to determine the corresponding timecode. The stored audio content is played back from a playback point determined based on the timecode. | 2015-11-12 |
20150325270 | MOTION INFORMATION DISPLAY APPARATUS AND METHOD - A motion information display apparatus according to an embodiment includes obtaining circuitry, identifying circuitry, and display controlling circuitry. The obtaining circuitry obtains a plurality of pieces of moving image information, and motion information that indicates a motion of a subject included in each of the moving image information. The identifying circuitry identifies a frame corresponding to a timing of a predetermined motion, from each frame group included in each of the moving image information, based on the motion information. The display controlling circuitry performs display control of the plurality of pieces of moving image information, using the frame corresponding to a timing of a predetermined motion. | 2015-11-12 |
20150325271 | TERMINAL AND OPERATING METHOD THEREOF - A method of controlling a mobile terminal, and which includes obtaining, via a camera of the mobile terminal, an image of a user; playing a video on a display unit of the mobile terminal; determining, via a controller of the mobile terminal, if the user is viewing the video being played based on the obtained image; storing, in a memory associated with the mobile terminal, video viewing information indicating when the user is viewing the video being played and when the user is not viewing the video being played for a specific playback section in an entire playback section of the video being played; receiving an input requesting the video viewing information be displayed; and displaying the video viewing information as a progressive bar on the display unit. | 2015-11-12 |
20150325272 | IN-MEMORY LIGHTWEIGHT COHERENCY - A system includes a plurality of host processors and a plurality of HMC devices configured as a distributed shared memory for the host processors. An HMC device includes a plurality of integrated circuit memory die including at least a first memory die arranged on top of a second memory die and at least a portion of the memory of the memory die is mapped to include at least a portion of a memory coherence directory; and a logic base die including at least one memory controller configured to manage three-dimensional (3D) access to memory of the plurality of memory die by at least one second device, and logic circuitry configured to determine memory coherence state information for data stored in the memory of the plurality of memory die, communicate information regarding the access to memory, and include the memory coherence information in the communicated information. | 2015-11-12 |
20150325273 | Discrete Three-Dimensional Vertical Memory - The present invention discloses a discrete three-dimensional vertical memory (3D-M | 2015-11-12 |
20150325274 | INPUT BUFFER AND MEMORY DEVICE INCLUDING THE SAME - An input buffer includes a first buffer, a feedback circuit and a second buffer circuit. The feedback circuit includes a feedback resistor and a feedback inverter. The first buffer may be configured to output an amplification signal to an output node of the first buffer based on an input signal. The feedback circuit connected to the output node of the first buffer may be configured to control the amplification signal. The second buffer circuit may be configured to output a buffer output signal by buffering the amplification signal. The feedback resistor may receive the amplification signal from the output node of the first buffer and provide a feedback signal to a feedback node. The feedback inverter is connected between the feedback node and the output node. The feedback inverter may be configured to control the amplification signal based on the feedback signal. | 2015-11-12 |
20150325275 | MEMORY GENERATING METHOD OF MEMORY COMPILER AND GENERATED MEMORY - A memory includes a logic controller, a word line driver, a boost circuit, plural capacitor circuits, plural memory cores, plural selectors, and plural output drivers. The logic controller generates a word line enabling signal and a boost enabling signal. The word line driver receives the word line enabling signal. The boost circuit receives the boost enabling signal. The plural capacitor circuits are connected between the boost circuit and the word line driver. Each of the plural memory cores is connected with the word line driver through plural word lines. The plural selectors are connected with the corresponding memory cores. The plural output drivers are connected with the corresponding selectors. The number of the plural memory cores is positively correlated with the number of the plural capacitor circuits. | 2015-11-12 |
20150325276 | BIPOLAR LOGIC GATES ON MOS-BASED MEMORY CHIPS - A system for using selectable-delay bipolar logic circuitry within the address decoder of a MOS-based memory includes a MOS-based memory, which includes an array of a plurality of memory cells configured to store data; an address decoder including bipolar logic circuitry, where the address decoder is configured to accept a word including a plurality of bits and access the array of memory cells using the word; where the bipolar logic circuitry includes a plurality of bipolar transistor devices, where at least one bipolar transistor device has an adjustable gate bias and is configured to accept an input, wherein the gate bias is adjusted based on the input, where the gate bias determines a selectable gate delay. | 2015-11-12 |
20150325277 | CHANNEL SKEWING - Methods and systems for channel skewing are described. One or more methods for channel skewing includes providing a number of groups of data signals to a memory component, each of the number of groups corresponding to a respective channel, and adjusting a phase of a group of data signals corresponding to at least one of the number of channels such that the group of data signals are skewed with respect to a group of data signals corresponding to at least one of the other respective channels. | 2015-11-12 |
20150325278 | VOLTAGE-CONTROLLED SOLID-STATE MAGNETIC DEVICES - Systems, methods, and apparatus are provided for tuning a functional property of a device. The device includes a layer of a dielectric material disposed over and forming an interface with a layer of an electrically conductive material. The dielectric material layer includes at least one ionic species having a high ion mobility. The electrically conductive material is configured such that a potential difference applied to the device can cause the at least one ionic species to migrate reversibly across the interface into or out of the electrically conductive material layer. | 2015-11-12 |
20150325279 | High-Speed Compare Operation Using Magnetic Tunnel Junction Elements Including Two Different Anti-Ferromagnetic Layers - A match-in-place-type compare operation utilizes a string of Magnetic Tunnel Junction (MTJ) elements including storage layers and sense layers having different anti-ferromagnetic structures respectively having higher and lower blocking temperatures. Confidential data is written into the storage layers of the MTJ elements by heating the elements above the higher blocking temperature, and then orienting the storage and sense layers in first storage magnetization directions using field lines. The elements are then cooled to an intermediate temperature between the higher and lower blocking temperatures, and the field lines are turned off, setting the sense layers to preliminary storage magnetization directions opposite to the first directions. During a pre-compare phase, an input logic pattern is written into the sense layers by heating to the intermediate temperature. During a compare operation, with the field lines turned off, resistance of the MTJ string is detected by passing a read current through the string. | 2015-11-12 |
20150325280 | NON-VOLATILE MEMORY VALIDITY - An embodiment provides a method, including: reading validity timing information written to a non-volatile memory device; and determining validity of the non-volatile memory device using the validity timing information read from the non-volatile memory device. Other aspects are described and claimed. | 2015-11-12 |
20150325281 | METHOD FOR TRAINING A CONTROL SIGNAL BASED ON A STROBE SIGNAL IN A MEMORY MODULE - A memory controller transmits a control signal to a memory module, where the memory controller continuously transmits a clock signal to the memory module. The memory controller determines adjustments to the control signal with respect to the clock signal, by iteratively analyzing a strobe signal. | 2015-11-12 |
20150325282 | MEMORY DEVICE AND ELECTRONIC DEVICE - To provide a memory device with low power consumption. The memory device includes a sense amplifier, bit lines, memory cells, and first transistors. The bit lines are provided over a layer where the sense amplifier is provided. The memory cells are provided over a layer where the bit lines are provided. The memory cell includes a second transistor and a capacitor. The sense amplifier and the bit lines are electrically connected to each other through the first transistors. The sense amplifier may include at least one layer of a conductor. | 2015-11-12 |
20150325283 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device including: a memory cell array including a plurality of memory cells disposed in a matrix; and a peripheral circuit adjacent to the memory cell array. Each of the memory cells includes: a capacitive element including a lower electrode having a cylinder shape extending in a direction perpendicular to a principal surface of a substrate; and a switch transistor provided between the capacitive element and a bit line, turning on/off of the switch transistor being controlled based on a potential of a word line. The peripheral circuit includes a signal line that is adjacent to the lower electrode in a horizontal direction parallel to the principal surface and is supplied with a fixed potential, or a pair of signal lines respectively supplied with complementary potentials. | 2015-11-12 |
20150325284 | SEMICONDUCTOR APPARATUS CAPABLE OF PREVENTING REFRESH ERROR AND MEMORY SYSTEM USING THE SAME - A semiconductor apparatus includes a plurality of memory banks configured to perform a refresh operation in response to an address count value and row active signals; a refresh control block configured to update refresh bank informations which define a bank designated to perform the refresh operation in response to a refresh command and bank addresses, and activate a count control signal in response to the refresh bank informations; and a counter configured to change the address count value in response to activation of the count control signal. | 2015-11-12 |
20150325285 | Semiconductor Device - This invention provides a semiconductor device with high speed operation and reduced size. A circuit includes a circuit including a memory circuit and a circuit including a logic circuit; thus, the circuit functions as a memory device having a function of storing data and a function of performing logic operation. The circuit can output, in addition to data stored in the circuit, data corresponding to a result of logic operation performed using data stored in the circuit as an input signal. The circuit can directly obtain a result of logic operation from the circuit, and thus, the frequency of input/output of a signal performed between the circuit and the circuit can be reduced. | 2015-11-12 |
20150325286 | 8T BASED SRAM CELL AND RELATED METHOD - Various embodiments include memory devices and related methods. An embodiment includes circuitry including: a first inverter having a first inverter storage node, the first inverter cross-coupled to a second inverter having a second inverter storage node, wherein each of the first inverter and the second inverter has a reverse bit line controlled feedback transistor coupled between an pull-down transistor and a pull-up transistor, and wherein each pull-down transistor is further coupled to a ground; a first signal line coupled with the reverse bit line controlled feedback transistor of the second inverter; a second signal line coupled with the reverse bit line controlled feedback transistor of the first inverter; a first access transistor coupled with the first inverter storage node, the first signal line, and a third signal line; and a second access transistor coupled with the second inverter storage node, the second signal line, and the third signal line. | 2015-11-12 |
20150325287 | MEMORY ARRAY AND METHOD OF OPERATING THE SAME - A memory array includes an array of memory cells. The memory array further includes at least two read tracking cells in a read tracking column. The memory array further includes a read tracking circuit coupled to the at least two read tracking cells, wherein the read tracking circuit is configured to generate a global tracking result signal based on outputs from the at least two read tracking cells. The memory array further includes memory control circuitry, wherein the memory control circuitry is configured to reset a memory clock based on the global tracking result signal. | 2015-11-12 |
20150325288 | APPARATUSES AND METHODS FOR PERFORMING MULTIPLE MEMORY OPERATIONS - The disclosed technology relates to a memory device configured to perform multiple access operations in response to a single command received through a memory controller and a method of performing the multiple access operations. In one aspect, the memory device includes a memory array comprising a plurality of memory cells and a memory controller. The memory controller is configured to receive a single command which specifies a plurality of memory access operations to be performed on the memory array. The memory controller is further configured to cause the specified plurality of memory access operations to be performed on the memory array. | 2015-11-12 |
20150325289 | APPARATUSES AND METHODS FOR BI-DIRECTIONAL ACCESS OF CROSS-POINT ARRAYS - The disclosed technology generally relates to apparatuses and methods of operating the same, and more particularly to cross point memory arrays and methods of accessing memory cells in a cross point memory array. In one aspect, an apparatus comprises a memory array. The apparatus further comprises a memory controller configured to cause an access operation, where the access operation includes application of a first bias across a memory cell of the memory array for a selection phase of the access operation and application of a second bias, lower in magnitude than the first bias, across the memory cell for an access phase of the access operation. The memory controller is further configured to cause a direction of current flowing through the memory cell to be reversed between the selection phase and the access phase. | 2015-11-12 |
20150325290 | DATA OPERATIONS IN NON-VOLATILE MEMORY - A method includes receiving an in-place refresh command to refresh data at a particular location in a non-volatile memory. The method also includes re-writing the data into the particular location of the non-volatile memory to refresh the data at the particular location in response to the in-place refresh command. | 2015-11-12 |
20150325291 | REFRESH OF A MEMORY AREA OF A NON-VOLATILE MEMORY UNIT - A method for performing a refresh of a first memory area of a non-volatile memory unit includes overwriting at least one additional memory area of the non-volatile memory unit with a memory content from the first memory area, adding a reference to the at least one additional memory area to a memory address area corresponding to the memory content and removing a reference to the first memory area from the memory address area corresponding to the memory content, overwriting the first memory area with the memory content from the at least one additional memory area, and subsequently replacing the reference in the memory address area with the reference to the first memory area. | 2015-11-12 |
20150325292 | THREE DIMENSIONAL NON-VOLATILE STORAGE WITH CONNECTED WORD LINES - A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. | 2015-11-12 |
20150325293 | PROGRAM-DISTURB DECOUPLING FOR ADJACENT WORDLINES OF A MEMORY DEVICE - Subject matter disclosed herein relates to memory operations regarding programming bits into a memory array. | 2015-11-12 |
20150325294 | RESISTIVE MEMORY AND ASSOCIATED OPERATION METHOD - A resistive memory includes a resistive memory cell, a main transistor and an auxiliary transistor. The drain of the main transistor and the drain of the auxiliary transistor are coupled to one end of the resistive memory cell. When the resistive memory cell is programmed, the main transistor is turned on and the auxiliary transistor is turned off. When the resistive memory cell is erased, the main transistor and the auxiliary transistor are turned on. | 2015-11-12 |
20150325295 | DEVICES AND METHODS TO PROGRAM A MEMORY CELL - Subject matter disclosed herein relates to memory devices and, more particularly, to programming a memory cell. | 2015-11-12 |
20150325296 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device according to an embodiment comprises: a memory cell array including a plurality of memory cells provided one at each of intersections of a plurality of first lines and a plurality of second lines and each storing data by a data storing state of a filament; and a control circuit configured to execute a write sequence that writes data to the memory cell, the write sequence including: a setting operation that applies a setting pulse having a first polarity to the memory cell; and a removing operation that applies a removing pulse having a second polarity opposite to the first polarity to the memory cell; and the control circuit, during execution of the write sequence, is configured to repeatedly execute the setting operation until the memory cell attains a desired data storing state, and then to execute the removing operation. | 2015-11-12 |
20150325297 | EFFICIENT REPROGRAMMING METHOD FOR TIGHTENING A THRESHOLD VOLTAGE DISTRIBUTION IN A MEMORY DEVICE - Techniques are provided for programming memory cells while reducing the effects of detrapping which cause a downshift in the threshold voltage distribution. Detrapping is particularly problematic for charge-trapping memory cells such as in a 3D stacked non-volatile memory device. During programming, a temporary lockout mode is provided for memory cells which pass a verify test. During a checkpoint program-verify iteration, all memory cells of a target data state are subject to the verify test. The memory cells in the temporary lockout mode are therefore subject to the verify test a second time. Memory cells that fail the verify test in the checkpoint program-verify iteration are programmed further. A normal or slow programming mode is used for a memory cell depending on whether it had reached the temporary lockout mode. Threshold voltage distributions are narrowed by reprogramming some of the memory cells. | 2015-11-12 |
20150325298 | MEMORY ACCESS TECHNIQUES FOR A MEMORY HAVING A THREE-DIMENSIONAL MEMORY CONFIGURATION - A data storage device includes a memory having a three-dimensional (3D) memory configuration. A method includes writing first data at a first physical page that is disposed within the memory at a first distance from a substrate of the memory. The first data is written at the first physical page using a first write technique. The method further includes writing second data at a second physical page that is disposed within the memory at a second distance from the substrate. The second distance is greater than the first distance. The second data is written at the second physical page using a second write technique that is different than the first write technique. | 2015-11-12 |
20150325299 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND WRITING METHOD THEREOF - A non-volatile semiconductor memory device utilized to implement the writing of data by adding a predetermined voltage for assigning a word line to a non-volatile memory cell includes a control process or generating and outputting control data implementing a program code for writing data including a word line assignment command and voltage source assignment data, a writing controller decoding the control data and generating a control signal of the word line assignment command and a control signal of the voltage source assignment data, a voltage generation circuit generating several voltages for writing data, and a switch circuit selecting a voltage, corresponding to voltage source assignment data, among several voltages, according to the control signal of the word line assignment command and the control signal of voltage source assignment data and outputting the selected voltage to the word line corresponding to the word line assignment command. | 2015-11-12 |
20150325300 | System And Method To Reducing Disturbances During Programming Of Flash Memory Cells - An improved control gate decoding design for reducing disturbances during the programming of flash memory cells is disclosed. In one embodiment, a control gate line decoder is coupled to a first control gate line associated with a row of flash memory cells in a first sector and to a second control gate line associated with a row of flash memory cells in a second sector. | 2015-11-12 |
20150325301 | NONVOLATILE MEMORY DEVICE AND ERASING METHOD THEREOF - According to example embodiments, a nonvolatile memory device includes a lower filling insulating layer covering a peripheral logic structure on a substrate, a horizontal semiconductor layer on the lower filling insulating layer, and a three-dimensional memory cell array including a plurality of memory blocks on the horizontal semiconductor layer. The horizontal semiconductor layer includes a plurality of doped regions spaced apart from each other in a first direction and a plurality of well regions between the doped regions. Each of the memory blocks includes sub-blocks on corresponding ones of the well regions. The non-volatile memory device is configured to perform an erase operation in units of the sub-blocks. The non-volatile memory device is configured to independently apply an erase voltage to a selected one of the well regions during the erase operation. | 2015-11-12 |
20150325302 | NON-VOLATILE REGISTER AND NON-VOLATILE SHIFT REGISTER - Non-Volatile Register (NVR) and Non-Volatile Shift Register (NVSR) devices are disclosed. The innovative NVR and NVSR devices of the invention can rapidly load the stored non-volatile data in non-volatile memory elements into their correspondent static memory elements for fast and constant referencing in digital circuitry. According to the invention, the loading process from non-volatile memory to static memory is a direct process without going through the conventional procedures of accessing the non-volatile memory, sensing from the non-volatile memory, and loading into the digital registers and shift registers. | 2015-11-12 |
20150325303 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes adjacent first and second blocks of memory cells, wherein all the memory cells in each block are erased collectively and each of the blocks includes a plurality of stacks of memory cells above a semiconductor substrate, a dummy cell region including a plurality of stacks of dummy cells above the semiconductor substrate, a source line contact electrically connected to an upper wiring layer and through which a voltage is applied to a source line of the memory cells, and a substrate contact electrically connected to the upper wiring layer and through which a voltage is applied to the semiconductor substrate. The source line contact is disposed between the first and second blocks, and the substrate contact is separated from any of the stacks of memory cells by at least one stack of dummy cells. | 2015-11-12 |
20150325304 | METHOD OF PROVIDING AN OPERATING VOLTAGE IN A MEMORY DEVICE AND A MEMORY CONTROLLER FOR THE MEMORY DEVICE - A method of providing an operating voltage in a memory device includes applying a read voltage to a selected word line while applying a first pass voltage to at least one unselected word line among word lines adjacent to the selected word line; and while applying a second pass voltage to the remaining unselected word lines (other than the at least one unselected word line to which the first pass voltage is applied). The level of the first pass voltage is higher than the level of the second pass voltage. The level of the first pass voltage may be set based on the level of the read voltage. | 2015-11-12 |
20150325305 | POWER SUPPLY SLEW RATE DETECTOR - In some embodiments, a power supply slew rate detector may include a filter circuit having a capacitive element operably coupled to a power supply output provided to a flash memory circuit and a resistive element operably coupled to the capacitive element and to ground, and a Schmitt trigger including an input operably coupled to a node between the capacitive element and the resistive element, the Schmitt trigger further including an output configured to indicate a slew rate of the power supply output. | 2015-11-12 |
20150325306 | SEMICONDUCTOR MEMORY DEVICE AND A READING METHOD THEREOF - A semiconductor memory device may include a common source line controller configured to provide a channel current to a cell string via a common source line during a read operation and a page buffer configured to detect data stored in a selected memory cell by detecting a current of the bit line when the channel current is provided. The page buffer may selectively bias the bit line to maintain a voltage of the bit line to be the same as or higher than a reference voltage. | 2015-11-12 |
20150325307 | METHOD FOR SETTING A FLASH MEMORY FOR HTOL TESTING - A method for setting voltages in a flash memory for high temperature operating life (HTOL) testing is provided. The flash memory includes a substrate, a source, and a control gate. The method includes adjusting the voltages that are applied to the source, the control gate, and the substrate, such that there is no voltage difference between the control gate and the source, and no voltage difference between the control gate and the substrate. Specifically, adjusting the voltages includes setting the voltage that is applied to the source to a ground voltage, setting the voltage that is applied to the control gate to the ground voltage, and setting the voltage that is applied to the substrate to a power supply voltage. | 2015-11-12 |
20150325308 | METHOD AND APPARATUS FOR CONCURRENT TEST OF FLASH MEMORY CORES - An apparatus for concurrent test of a set of flash memory banks apparatus includes a memory data path (MDP) module coupled to a test controller. The MDP module includes a test control module configured to generate a concurrent control signal that configures the set of flash memory banks to be tested simultaneously; and a set of comparators, that generates a first comparator output in response to the concurrent control signal and an input from the set of flash memory banks. A reduction logic is configured to generate a reduction logic output that combines a status of the comparator outputs to be compressed. A control logic is configured for selective programming across different flash bits of the set of flash memory banks. A fail flag is configured to generate one of an output value ‘0’ if there is a mismatch in data read from the set of flash memory banks in any access, and an output value 1 if there is no mismatch in data read in any access. | 2015-11-12 |
20150325309 | MEMORY APPARATUS, SYSTEMS, AND METHODS - Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed aggressor memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation. Additional apparatus, systems, and methods are provided. | 2015-11-12 |
20150325310 | DIELECTRIC-BASED MEMORY CELLS HAVING MULTI-LEVEL ONE-TIME PROGRAMMABLE AND BI-LEVEL REWRITEABLE OPERATING MODES AND METHODS OF FORMING THE SAME - A method of programming a memory cell is provided. The memory cell includes a memory element having a first conductive material layer, a first dielectric material layer above the first conductive material layer, a second conductive material layer above the first dielectric material layer, a second dielectric material layer above the second conductive material layer, and a third conductive material layer above the second dielectric material layer. One or both of the first and second conductive material layers comprises a stack of a metal material layer and a highly doped semiconductor material layer. The memory cell has a first memory state upon fabrication corresponding to a first read current. The method includes applying a first programming pulse to the memory cell with a first current limit. The first programming pulse programs the memory cell to a second memory state that corresponds to a second read current greater than the first read current. | 2015-11-12 |
20150325311 | LOW-POWER PULSE WIDTH ENCODING SCHEME AND COUNTER-LESS SHIFT REGISTER THAT MAY BE EMPLOYED THEREWITH - A method of decoding, an encoded signal includes steps of receiving the encoded signal, creating a decoding signal by delaying the encoded signal by a predetermined amount of time Δ, sampling the encoded signal using the decoding signal, and determining a value of each of a plurality of decoded bits represented by the encoded signal based on the sampling. Also, a method of operating a shift register wherein the shift register has an initialization state wherein a first binary symbol is stored in a first position and a second binary symbol different than the first binary symbol is stored in each of one or more intermediate positions and a last position. The method includes determining that the shift register is full responsive to detecting that the first binary symbol has been stored in either one of the intermediate positions or the last position. | 2015-11-12 |
20150325312 | SHIFT REGISTER, SEMICONDUCTOR DEVICE, DISPLAY DEVICE, AND ELECTRONIC DEVICE - The invention provides a semiconductor device and a shift register, in which low noise is caused in a non-selection period and a transistor is not always on. First to fourth transistors are provided. One of a source and a drain of the first transistor is connected to a first wire, the other of the source and the drain thereof is connected to a gate electrode of the second transistor, and a gate electrode thereof is connected to a fifth wire. One of a source and a drain of the second transistor is connected to a third wire and the other of the source and the drain thereof is connected to a sixth wire. One of a source and a drain of the third transistor is connected to a second wire, the other of the source and the drain thereof is connected to the gate electrode of the second transistor, and a gate electrode thereof is connected to a fourth wire. One of a source and a drain of the fourth transistor is connected to the second wire, the other of the source and the drain thereof is connected to the sixth wire, and a gate electrode thereof is connected to the fourth wire. | 2015-11-12 |
20150325313 | ASSIST CIRCUITS FOR SRAM TESTING - Assist circuits for SRAM memory tests allow voltage scaling in low-power SRAMs. Word line level reduction (WLR) and negative bit line (NBL) boost assist techniques improve read stability and write margin of SRAM core-cells, respectively, when the memory operates at a lowered supply voltage. Assist circuits are activated at particular points in the memory cell circuit. The assist circuits are selectively activated for modifying the voltage along particular circuit elements to identify the potential defects that might be otherwise masked until substantially large. A March test invokes elements for activating the assist circuits to identify defects and indicate functional fault models (FFMs) associated with the defects. | 2015-11-12 |
20150325314 | At-Speed Test of Memory Arrays Using Scan - A method and apparatus for conducting at-speed testing of a memory array in an integrated circuit (IC) is disclosed. In one embodiment, an IC includes a memory array and a plurality of input circuits coupled to provide input signals into the memory array. Each of the plurality of input circuits includes an input flip-flop having a data output coupled to a corresponding input of the memory array, selection circuitry configured to select a data path to a data input of the input flip-flop and a data path shift register coupled to control a state of a selection signal provided to the selection circuitry, wherein the data path shift register includes a plurality of multiplexers. When operating the IC in a test mode, the plurality of input circuits is configured to provide input signals into the memory array at an operational clock speed of the IC. | 2015-11-12 |
20150325315 | PRIORITIZED REPAIR OF DATA STORAGE FAILURES - Embodiments are directed towards managing data storage that may experience a data failure. If a repair event is associated with a data storage failure, a new repair task may be generated and added to a task list. A priority value for each repair task in the task list may be determined based in part on the mean-time-to-data-loss (MTTDL) value associated with each repair task in the task list such that a lower MTTDL may indicate a higher priority value over a lower MTTDL. One or more repair tasks may be promoted to become active repair tasks based on the priority value the repair tasks such that the promoted repair tasks have a higher priority that than other repair tasks in the task list, if any. Each active repair task may be executed to repair one or more associated the storage failures. | 2015-11-12 |
20150325316 | REPAIR CIRCUIT AND FUSE CIRCUIT - A repair circuit includes first and second fuse circuits, a determination circuit and an output circuit. The first fuse circuit includes a first fuse and is configured to generate a first master signal indicating whether the first fuse has been programmed. The second fuse circuit includes second fuses and is configured to generate a first address indicating whether each of the second fuses has been programmed. The determination circuit is configured to generate a detection signal based on the first master signal and the first address. The detection signal indicates whether a negative program operation has been performed on the second fuse circuit. The output circuit is configured to generate a second master signal based on the first master signal and the detection signal and generate a repair address corresponding to a defective input address based on the first address and the detection signal. | 2015-11-12 |
20150325317 | NUCLEAR REACTOR - A nuclear reactor comprising a housing having disposed therein an active region that contains a bundle of rod-type fuel elements enclosed in a tubular shell and submerged in a primary coolant that circulates between the active region and at least one heat exchanger. In order to reduce the level of pressure of gaseous fission fragments accumulating below the fuel element shell and to enable the most uniform possible distribution of the velocity field of the primary coolant at the inlet to the active part of the fuel elements, said fuel elements are provided in their upper parts with active portions, which are filled with fuel, and hollow working portions, which are situated below said active portions. | 2015-11-12 |
20150325318 | FAIL-SAFE CONTROL ROD DRIVE SYSTEM FOR NUCLEAR REACTOR - A control rod drive system (CRDS) for use in a nuclear reactor. In one embodiment, the system generally includes a drive rod mechanically coupled to a control rod drive mechanism (CRDM) operable to linearly raise and lower the drive rod along a vertical axis, a rod cluster control assembly (RCCA) comprising a plurality of control rods insertable into a nuclear fuel core, and a drive rod extension (DRE) releasably coupled at opposing ends to the drive rod and RCCA. The CRDM includes an electromagnet which operates to couple the CRDM to DRE. In the event of a power loss or SCRAM, the CRDM may be configured to remotely uncouple the RCCA from the DRE without releasing or dropping the drive rod which remains engaged with, the CRDM and in position. | 2015-11-12 |
20150325319 | NOZZLE REPAIR METHOD AND NUCLEAR REACTOR VESSEL - A nozzle repair method and a nuclear reactor vessel include: removing a trepanning portion ( | 2015-11-12 |
20150325320 | METHOD FOR STORING RADIOCONTAMINATED WASTE MATTER AND CONTAINER THEREFOR - A method for securely and safely storing radiocontaminated waste matter and a container therefor are provided. | 2015-11-12 |
20150325321 | TRANSPORTATION CONTAINER - The present invention provides a radiation-shielding container for a radiopharmaceutical that allows or a product fluid to be dispensed from a base component thereof. | 2015-11-12 |
20150325322 | X-RAY ANTI-SCATTER GRID - An X-ray anti-scatter grid assembly includes a boron-nitride substrate and X-ray absorbing septa coupled to the boron-nitride substrate. | 2015-11-12 |