46th week of 2015 patent applcation highlights part 56 |
Patent application number | Title | Published |
20150325423 | SYSTEMS AND METHODS FOR ANALYZING AN EXTRACTED SAMPLE - The invention generally relates to systems for analyzing a sample and methods of use thereof. In certain aspects, the invention provides systems that include an ionization probe and a mass analyzer. The probe includes a hollow body that has a distal tip. The probe also includes a substrate that is at least partially disposed within the body and positioned prior to the distal tip so that sample extracted from the substrate flows into the body prior to exiting the distal tip. The probe also includes an electrode that operably interacts with sample extracted from the substrate. | 2015-11-12 |
20150325424 | Method of Assessing Vacuum Conditions in a Mass Spectrometer - A method is proposed for assessing the vacuum conditions in a mass spectrometer ( | 2015-11-12 |
20150325425 | Multi-Electrode Ion Trap - This invention relates generally to multi-reflection electrostatic systems, and more particularly to improvements in and relating to the Orbitrap electrostatic ion trap. A method of operating an electrostatic ion trapping device having an array of electrodes operable to mimic a single electrode is proposed, the method comprising determining three or more different voltages that, when applied to respective electrodes of the plurality of electrodes, generate an electrostatic trapping field that approximates the field that would be generated by applying a voltage to the single electrode, and applying the three or more so determined voltages to the respective electrodes. Further improvements lie in measuring a plurality of features from peaks with different intensities from one or more collected mass spectra to derive characteristics, and using the measured characteristics to improve the voltages to be applied to the plurality of electrodes. | 2015-11-12 |
20150325426 | Lighting Device - A lighting device includes: a casing having an inlet that introduces external air at one side and an outlet that discharges the introduced air through the inlet at the other side; a fan located within the casing to flow external air from an inlet direction to an outlet direction; an inlet cover that blocks at least an upper area of the inlet to prevent external air from being directly introduced into the inlet; and an air flow channel that communicates the inlet and the outside, wherein the air flow channel includes: two contracting flow channels having a reducing sectional area advancing in an advancing direction of air; and two expanding flow channels that communicate with the contracting flow channels and that have an increasing sectional area advancing in an advancing direction of air, wherein in a connection portion of the contracting flow channel and the expanding flow channel, the advancing direction of air is changed. | 2015-11-12 |
20150325427 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS - Provided are: forming an oxycarbonitride film, an oxycarbide film or an oxide film on a substrate by alternately performing a specific number of times: forming a first layer containing the specific element, nitrogen and carbon, on the substrate, by alternately performing a specific number of times, supplying a first source containing the specific element and a halogen-group to the substrate in a processing chamber, and supplying a second source containing the specific element and an amino-group to the substrate in the processing chamber; and forming a second layer by oxidizing the first layer by supplying an oxygen-containing gas, and an oxygen-containing gas and a hydrogen-containing gas to the substrate in the processing chamber. | 2015-11-12 |
20150325428 | NITRIDE SEMICONDUCTOR WAFER, NITRIDE SEMICONDUCTOR ELEMENT, AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR WAFER - A nitride semiconductor wafer includes a silicon substrate, a first layer, a second layer, a third layer, a fourth layer, a fifth layer, and a sixth layer. The first layer is provided on the silicon substrate. The second layer is provided on the first layer. The third layer is provided on the second layer. The fourth layer is provided on the third layer. The fifth layer is provided on the fourth layer. The sixth layer is provided on the fifth layer. A composition ratio x4 of the fourth layer decreases in a first direction from the third layer toward the fifth layer. A maximum value of the composition ratio x4 is not more than a composition ratio of the third layer. A minimum value of the composition ratio x4 is not less than a composition ratio of the fifth layer. | 2015-11-12 |
20150325429 | DRY SEPARATION APPARATUS, NOZZLE FOR GENERATING HIGH-SPEED PARTICLE BEAM FOR DRY SEPARATION, AND DRY SEPARATION METHOD USING HIGH-SPEED PARTICLE BEAM - A dry separation method is a dry separation method for ashing a photoresist, including a spraying and separating step of spraying sublimation particles on the photoresist and separating the photoresist. A dry separation apparatus is a dry separation apparatus for ashing a photoresist, including a nozzle for generating a high-speed particle beam that includes sublimation particles. The nozzle generates ultra-high speed uniform nanoparticles by passing therethrough a particle generation gas including carbon dioxide, and includes an expanding portion having a shape so that the cross sectional area thereof becomes wider toward a discharge side of the nozzle. The expanding portion sequentially includes a first expanding portion and a second expanding portion, and an average expansion angle of the second expanding portion is bigger than an expansion angle of the first expanding portion. | 2015-11-12 |
20150325430 | HIGH THROUGHPUT SEMICONDUCTOR DEPOSITION SYSTEM - A reactor for growing or depositing semiconductor films or devices. The reactor may be designed for inline production of III-V materials grown by hydride vapor phase epitaxy (HVPE). The operating principles of the HVPE reactor can be used to provide a completely or partially inline reactor for many different materials. An exemplary design of the reactor is shown in the attached drawings. In some instances, all or many of the pieces of the reactor formed of quartz, such as welded quartz tubing, while other reactors are made from metal with appropriate corrosion resistant coatings such as quartz or other materials, e.g., corrosion resistant material, or stainless steel tubing or pipes may be used with a corrosion resistant material useful with HVPE-type reactants and gases. Using HVPE in the reactor allows use of lower-cost precursors at higher deposition rates such as in the range of 1 to 5 μm/minute. | 2015-11-12 |
20150325431 | PHOTOSENSITIVE RESIN COMPOSITION, METHOD FOR PRODUCING PATTERNED CURED FILM, SEMICONDUCTOR ELEMENT AND ELECTRONIC DEVICE - Disclosed is a photosensitive resin composition comprising (A) an alkali-soluble resin having a structural unit represented by the following formula (1), (B) a compound that generates an acid by light, (C) a thermal crosslinking agent, and (D) an acryl resin having a structural unit represented by the following formula (2): | 2015-11-12 |
20150325432 | FILM FORMING METHOD, FILM FORMING APPARATUS AND RECORDING MEDIUM - A film forming method in which in a state in which a target substrate is loaded on a loading table body of a loading table installed in a processing container and an interior of the processing container is evacuated, a film forming material gas is supplied into the processing container while heating the target substrate with a heater installed in the loading table body, to be thermally decomposed or reacted on a surface of the target substrate to form a predetermined film on the target substrate, includes introducing a heat transfer gas containing an H | 2015-11-12 |
20150325433 | SEMICONDUCTOR WAFER COMPOSED OF SILICON AND METHOD FOR PRODUCING SAME - Monocrystalline silicon semiconductor wafers have a front side and a rear side, and a denuded zone which extends from the front side to the rear side as far as a depth which between a center and an edge of the semiconductor wafer on average is not less than 8 μm and not more than 18 μm, and having a region adjoining the denuded zone having BMDs whose density at a distance of 30 μm from the front side is not less than 2×10 | 2015-11-12 |
20150325434 | Substrate Processing Apparatus, Method of Manufacturing Semiconductor Device and Non-Transitory Computer-Readable Recording Medium - A high quality thin film is formed by forming a layer in which remaining residues are suppressed for each cycle. When a substrate sequentially passes through a first processing region, a second processing region, and a third processing region by rotating a substrate placement unit, a first layer is formed on the substrate while the substrate passes through the first processing region, a second layer is formed by reacting plasma of a reactive gas with the first layer while the substrate passes through the second processing region, and the second layer is modified by plasma of a modifying gas while the substrate passes through the third processing region. | 2015-11-12 |
20150325435 | PECVD DEPOSITION OF SMOOTH SILICON FILMS - Smooth silicon films having low compressive stress and smooth tensile silicon films are deposited by plasma enhanced chemical vapor deposition (PECVD) using a process gas comprising a silicon-containing precursor (e.g., silane), argon, and a second gas, such as helium, hydrogen, or a combination of helium and hydrogen. Doped smooth silicon films and smooth silicon germanium films can be obtained by adding a source of dopant or a germanium-containing precursor to the process gas. In some embodiments dual frequency plasma comprising high frequency (HF) and low frequency (LF) components is used during deposition, resulting in improved film roughness. The films are characterized by roughness (Ra) of less than about 7 Å, such as less than about 5 Å as measured by atomic force microscopy (AFM), and a compressive stress of less than about 500 MPa in absolute value. In some embodiments smooth tensile silicon films are obtained. | 2015-11-12 |
20150325436 | SEMICONDUCTOR DEVICES INCLUDING AN ELECTRICALLY-DECOUPLED FIN AND METHODS OF FORMING THE SAME - Semiconductor devices including a fin and method of forming the semiconductor devices are provided herein. In an embodiment, a method of forming a semiconductor device includes forming a fin overlying a semiconductor substrate. The fin is formed by epitaxially-growing a semiconductor material over the semiconductor substrate, and the fin has a first portion that is proximal to the semiconductor substrate and a second portion that is spaced from the semiconductor substrate by the first portion. A gate structure is formed over the fin and the semiconductor substrate. The first portion of the fin is etched to form a gap between the second portion and the semiconductor substrate. | 2015-11-12 |
20150325437 | METHOD FOR MANUFACTURING COMPOUND SEMICONDUCTOR SENSITIVE FILM BASED ON DISPLACEMENT REACTION-THERMAL OXIDATION METHOD - The present disclosure provides a method for preparing compound semiconductor sensitive film based on a displacement reaction-thermal oxidation method, the method comprising: growing a layer of Zn on a high temperature-resistant substrate; submerging the substrate on which the layer of Zn has been grown into ionic solution of soluble salt of Cu, such that Cu ions in the solution are displaced so as to separate Cu nano-particles out on a surface of the layer of Zn; and performing a thermal oxidation process on the layer of Zn to whose surface Cu nano-particles are adhered, such that the Cu nano-particles are oxidized into CuO nano-particles, so as to obtain a ZnO gas sensitive film that is doped with CuO nano-particles. The above preparing method has the following advantages: good filming quality, simplified preparation process, low cost and easy to control. | 2015-11-12 |
20150325438 | PRECURSOR SOLUTION FOR FORMING METAL CHALCOGENIDE FILM - A chalcogen element can be effectively dissolved in a non-explosive hydrazine-based solvent by the aid of sodium in a non-explosive hydrazine-based solvent. Therefore, a precursor solution for forming a metal chalcogenide film containing as a solvent a non-explosive hydrazine-based solvent which is less poisonous than hydrazine and which is free of explosiveness is provided. A metal chacogenide thin film may be formed employing the metal chalcogenide precursor solution. | 2015-11-12 |
20150325439 | GROWING CRYSTALLINE SEMICONDUCTOR OXIDE THIN FILMS ON A SUBSTRATE AT A LOW TEMPERATURE USING MICROWAVE RADIATION - A method for growing crystalline semiconductor oxide thin films. A substrate is coated with a conducting oxide (e.g., indium tin oxide). The coated substrate is immersed in a growth solution, such as a solution of a titanium-based sol-gel precursor combined with tetraethylene glycol. The coated substrate and the growth solution are heated in a microwave reactor via microwave radiation. Film growth of crystalline semiconductor oxide thin films (e.g., titanium dioxide thin films) are then catalyzed by microwave interaction with the conducting oxide on the substrate. Such a process enables crystalline semiconductor oxide thin films to be grown on a flexible or heat-sensitive substrate (e.g., plastic) using a low temperature in a fast and inexpensive manner. | 2015-11-12 |
20150325440 | Method for Forming a Semiconductor Device and Semiconductor Device - A method for forming a semiconductor device includes depositing an epitaxial layer on a semiconductor substrate, forming an oxygen diffusion region within the epitaxial layer by oxygen diffusion from the semiconductor substrate into a part of the epitaxial layer and tempering at least the oxygen diffusion region of the epitaxial layer at a temperature between 400° C. and 480° C. for more than 15 minutes. | 2015-11-12 |
20150325441 | SEMICONDUCTOR FABRICATION METHOD - A semiconductor fabrication method is provided. A substrate having thereon a base layer, a hard mask layer, and a core layer is prepared. A resist pattern is transferred to the core layer, thereby forming a core pattern. The core pattern is subjected to a post-clean process. Thereafter, a spacer layer is deposited on the core pattern. The spacer layer is etched to form spacer pattern on each sidewall of the core pattern. The core pattern is then removed. The spacer pattern is transferred to the underlying hard mask layer and the base layer. | 2015-11-12 |
20150325442 | Formulations of Solutions and Processes for Forming a Substrate Including a Dopant - Formulations of solutions and processes are described to form a substrate including a dopant. In particular implementations, the dopant can include arsenic (As) or phosphorus (P). In an embodiment, a dopant solution is provided that includes a solvent and a dopant-containing molecule. In a particular embodiment, the solvent of the dopant solution can have a flashpoint that is at least 55° C. In some cases, the dopant-containing molecule can have a molecular weight that is no greater than about 300 g/mol. In other instances, a ratio of a concentration of a dopant-containing molecule relative to a concentration of a contaminant is no greater than about 1×10 | 2015-11-12 |
20150325443 | SPALLING WITH LASER-DEFINED SPALL EDGE REGIONS - Laser ablation can be used to form a trench within at least a blanket layer of a stressor layer that is atop a base substrate. A non-ablated portion of the stressor layer has an edge that defines the edge of the material layer region to be spalled. Laser ablation can also be used to form a trench within a blanket material stack including at least a plating seed layer. A stressor layer is formed on the non-ablated portions of the material stack and one portion of the stressor layer has an edge that defines the edge of the material layer region to be spalled. Laser ablation can be further used to form a trench that extends through a blanket stressor layer and into the base substrate itself. The trench has an edge that defines the edge of the material layer region to be spalled. | 2015-11-12 |
20150325444 | METHOD FOR PRODUCING AN SGT-INCLUDING SEMICONDUCTOR DEVICE - A method for producing an SGT-including semiconductor device includes forming a gate insulating layer on an outer periphery of a Si pillar, forming a gate conductor layer on the gate insulating layer, and forming an oxide layer on the gate conductor layer. Then a hydrogen fluoride ion diffusion layer containing moisture is formed so as to make contact with the oxide layer and lie at an intermediate position of the Si pillar. A part of the oxide film in contact with the hydrogen fluoride ion diffusion layer is etched with hydrogen fluoride ions generated from hydrogen fluoride gas supplied to the hydrogen fluoride ion diffusion layer and an opening is thereby formed on the outer periphery of the Si pillar. | 2015-11-12 |
20150325445 | REDUCED SILICON GOUGING DURING OXIDE SPACER FORMATION - An improved method for fabricating a semiconductor device is provided to decrease substrate gouging during oxide spacer formation. The method includes: forming a gate structure on a substrate; depositing an oxide layer along the sidewalls of the gate structure and on the substrate; removing some of the oxide layer to define oxide spacers along sidewalls of the gate structure; and performing an isotropic etch process to remove a residual portion of the oxide layer. | 2015-11-12 |
20150325446 | SELECTIVE COBALT DEPOSITION ON COPPER SURFACES - Embodiments of the invention provide processes to selectively form a cobalt layer on a copper surface over exposed dielectric surfaces. In one embodiment, a method for capping a copper surface on a substrate is provided which includes positioning a substrate within a processing chamber, wherein the substrate contains a contaminated copper surface and a dielectric surface, exposing the contaminated copper surface to a reducing agent while forming a copper surface during a pre-treatment process, exposing the substrate to a cobalt precursor gas to selectively form a cobalt capping layer over the copper surface while leaving exposed the dielectric surface during a vapor deposition process, and depositing a dielectric barrier layer over the cobalt capping layer and the dielectric surface. In another embodiment, a deposition-treatment cycle includes performing the vapor deposition process and subsequently a post-treatment process, which deposition-treatment cycle may be repeated to form multiple cobalt capping layers. | 2015-11-12 |
20150325447 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SUBSTRATE PROCESSING APPARATUS - Provided is a technique of adjusting a work function. A method of manufacturing a semiconductor device includes forming a film having a predetermined thickness and containing a first metal element, carbon and nitrogen on a substrate by: (a) forming a first layer containing the first metal element and carbon by supplying a metal-containing gas containing the first metal element and a carbon-containing gas to the substrate M times and (b) forming a second layer containing the first metal element, carbon and nitrogen by supplying a nitrogen-containing gas to the substrate having the first layer formed thereon N times to nitride the first layer, wherein M and N are selected in a manner that a work function of the film has a predetermined value (where M and N are natural numbers). | 2015-11-12 |
20150325448 | ETCHING METHOD, SUBSTRATE PROCESSING METHOD, PATTERN FORMING METHOD, METHOD FOR MANUFACTURING SEMICONDUCTOR ELEMENT, AND SEMICONDUCTOR ELEMENT - A fluorocarbon layer is formed on a silicon substrate that is a to-be-processed substrate (step A). A resist layer is formed on the thus-formed fluorocarbon layer (step B). Then, the resist layer is patterned into a predetermined shape by exposing the resist layer to light by means of a photoresist layer (step C). The fluorocarbon layer is etched using the resist layer, which has been patterned into a predetermined shape, as a mask (step D). Next, the resist layer served as a mask is removed (step E). After that, the silicon substrate is etched using the remained fluorocarbon layer as a mask (step F). Since the fluorocarbon layer by itself functions as an antireflective film and a harm mask, the reliability of processing can be improved, while reducing the cost. | 2015-11-12 |
20150325449 | SUBSTRATE TREATMENT METHOD - A substrate treatment method includes the steps of: supporting a substrate with a support member; arranging an extension surface such that the extension surface laterally surrounds one major surface of the substrate supported by the support member and extends continuously to the major surface of the substrate supported by the support member; rotating the substrate supported by the support member; and etching the substrate by supplying an etching liquid onto the major surface of the substrate supported by the support member, wherein the extension surface has higher affinity for the etching liquid than the major surface of the substrate supported by the support member. | 2015-11-12 |
20150325450 | REWORK AND STRIPPING OF COMPLEX PATTERNING LAYERS USING CHEMICAL MECHANICAL POLISHING - A method utilizing a chemical mechanical polishing process to remove a patterned material stack comprising at least one pattern transfer layer and a template layer during a rework process or during a post pattern transfer cleaning process is provided. The pattern in the patterned material stack is formed by pattern transfer of a directed self-assembly pattern generated from microphase separation of a self-assembly material. | 2015-11-12 |
20150325451 | MULTI-LAYER POLISHING PAD FOR CMP - The invention is directed to a multi-layer polishing pad for chemical-mechanical polishing comprising a top layer, a middle layer and a bottom layer, wherein the top layer and bottom layer are joined together by the middle layer, and without the use of an adhesive. The invention is also directed to a multi-layer polishing pad comprising an optically transmissive region, wherein the layers of the multi-layer polishing pad are joined together without the use of an adhesive. | 2015-11-12 |
20150325452 | PLANARIZATION PROCESS - A planarization process, the process including performing first sputtering on a material layer, with an area of the material layer which has a relatively low loading condition for sputtering shielded by a first shielding layer, removing the first shielding layer, and performing second sputtering on the material layer to planarize the material layer. | 2015-11-12 |
20150325453 | METHOD OF FORMING SEMICONDUCTOR DEVICE - A method of forming a semiconductor device is provided. A material layer, a first flowing material layer and a first mask layer are sequentially formed on a substrate. A first etching process is performed by using the first mask layer as a mask, so as to form a first opening in the material layer. The first mask layer and the first flowing material layer are removed. A filler layer is formed in the first opening. A second flowing material layer is formed on the material layer and the filler layer. A second mask layer is formed on the second flowing material layer. A second etching process is performed by using the second mask layer as a mask, so as to form a second opening in the material layer. | 2015-11-12 |
20150325454 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - One method includes sequentially forming an insulating film and a first material film on a semiconductor substrate, forming on the first material film a mask film having a rectangular first opening, and dry-etching the first material film using the mask film as a mask to form an ellipsoidal second opening having its shorter side aligned in a first direction of the first material film. Forming the mask film includes forming a second material film having a side surface that faces the first direction of the first opening, and a third material film having side surfaces facing a second direction of the first opening, and the thickness of the third material film is greater than the thickness of the second material film. | 2015-11-12 |
20150325455 | SEMICONDUCTOR MANUFACTURING METHOD AND SEMICONDUCTOR MANUFACTURING APPARATUS - In a semiconductor manufacturing method for performing thermal treatment of a substrate with plasma while moving the substrate on which devices are formed relatively to a plasma generating apparatus which generates the plasma by allowing electromagnetic fields to act on a plasma gas, a second surface of the substrate is irradiated with the plasma of the plasma generating apparatus in a state where the second surface of the substrate which is the opposite side of a first surface of the substrate on which the devices are formed faces the plasma generating apparatus. | 2015-11-12 |
20150325456 | METHOD FOR CLEANING BASE, HEAT PROCESS METHOD FOR SEMICONDUCTOR WAFER, AND METHOD FOR MANUFACTURING SOLID-STATE IMAGE CAPTURING APPARATUS - A method for cleaning a base for supporting an object to process in an apparatus configured to perform a heat process, the method comprising a first step of forming an oxide film on the base including silicon carbide, by subjecting the base to a heat process in a gas atmosphere including oxygen, and a second step of, after the first step, subjecting the base to a heat process in a gas atmosphere including steam, wherein the first step is performed for 10 hours at a temperature of 1000° C. or more. | 2015-11-12 |
20150325457 | Method of Packaging Semiconductor Devices and Apparatus for Performing the Same - Provided are an apparatus and method of packaging semiconductor devices mounted on a flexible substrate having a longitudinally extending tape shape and on which packaging areas are defined along the extending direction thereof. The flexible substrate is transferred through a packaging module. An empty area, on which a semiconductor device is not mounted, is detected by a camera from among the packaging areas. Heat dissipation paint composition is applied on at least one semiconductor device located in a processing region of the packaging module by a screen printing process. Thus, a heat dissipation layer configured to package the semiconductor device is formed. Here, operations of the packaging module are controlled by a control unit so that the packaging process is omitted with respect to the empty area. | 2015-11-12 |
20150325458 | METHOD AND SYSTEM TO IMPROVE DRYING OF FLEXIBLE NANO-STRUCTURES - Disclosed herein are methods and systems for processing of nano-structures. In particular, disclosed herein are methods for processing nano-structures during semiconductor manufacturing, including nano-structures of drying high-aspect ratios. Also disclosed are systems for implementing the methods disclosed herein. | 2015-11-12 |
20150325459 | PITCH MULTIPLICATION SPACERS AND METHODS OF FORMING THE SAME - Spacers in a pitch multiplication process are formed without performing a spacer etch. Rather, the mandrels are formed over a substrate and then the sides of the mandrels are reacted, e.g., in an oxidization, nitridation, or silicidation step, to form a material that can be selectively removed relative to the unreacted portions of the mandrel. The unreacted portions are selectively removed to leave a pattern of free-standing spacers. The free-standing spacers can serve as a mask for subsequent processing steps, such as etching the substrate. | 2015-11-12 |
20150325460 | ETCHING CHAMBER AND METHOD OF MANUFACTURING SUBSTRATE - An etching chamber includes a chamber body including a flow channel and an opening mounted the substrate to be etched and the opening communicating with the flow channel and a sealing member provided in the periphery of the opening and configured to close a gap between the substrate and the chamber body when the substrate is mounted in the opening, wherein the sealing member includes a first groove provided on an upper surface of the sealing member which comes into abutment with the substrate when the substrate is mounted in the opening, a second groove provided on a sealing member bottom surface on a side opposite from the upper surface of the sealing member, and at least one communicating hole communicating with the first groove and the second groove. | 2015-11-12 |
20150325461 | Method of Packaging Semiconductor Devices and Apparatus for Performing the Same - Provided is a method of packaging semiconductor devices mounted on a flexible substrate having a longitudinally extending tape shape and including packaging areas arranged along the extending direction thereof. An empty area, on which a semiconductor device is not mounted, is detected from among the packaging areas. When the empty area is detected, a heat dissipation paint composition is applied on the semiconductor devices mounted on the remaining packaging areas except for the empty area to form first heat dissipation layers. When the empty is not detected, the heat dissipation paint composition is applied on the semiconductor devices mounted on the packaging areas to form second heat dissipation layers. Here, the first dissipation layers are formed by a potting process, and the second heat dissipation layers are formed by a screen printing process. | 2015-11-12 |
20150325462 | WAFER CARRIER - A wafer carrier | 2015-11-12 |
20150325463 | ATTACHING APPARATUS - An attaching apparatus, a substrate and a support that can be uniformly attached through an adhesive layer. The attaching apparatus is equipped with a set plate and a press plate formed of ceramics. The set plate and the press plate have a flatness of 1.0 μm or less when not pressed. | 2015-11-12 |
20150325464 | SYSTEM AND APPARATUS FOR HOLDING A SUBSTRATE OVER WIDE TEMPERATURE RANGE - An apparatus to support a substrate may include a base, a clamp portion to apply a clamping voltage to the substrate, and a displacement assembly configured to hold the clamp portion and base together in a first operating position, and to move the clamp portion with respect to the base from the first operating position to a second operating position, wherein the clamp portion and base are separate from one another in the second operating position. | 2015-11-12 |
20150325465 | SUPPORTING MEMBER SEPARATION METHOD - A supporting member separation method for separating a laminate which is formed by laminating a substrate and a support plate through an adhesive layer and in which a release layer is provided on at least a part of the peripheral portion on the surface of the side of the substrate facing the support plate or the peripheral portion on the surface of the side of the support plate facing the substrate, the method including reducing the adhesive force of at least a part of the release layer which is provided on the peripheral portion of the substrate or the support, and fixing a part in the substrate and the support plate and separating the support plate from the substrate by applying a force to another part, after the preliminary treatment. | 2015-11-12 |
20150325466 | SUBSTRATE SUPPORTING APPARATUS - A substrate supporting apparatus includes a rotatable chuck, a first mass flow controller, a second mass flow controller, a plurality of locating pins and guiding pillars, and a motor in which the rotatable chuck defines a plurality of first injecting ports and second injecting ports, the first injecting ports are connected with a first gas passage for supplying gas to the substrate and sucking the substrate by Bernoulli effect, the second injecting ports are connected with a second gas passage for supplying gas to the substrate and lifting the substrate, the first and the second mass flow controllers are respectively installed on the first and the second gas passages, the plurality of locating pins and guiding pillars are disposed at the top surface of the rotatable chuck and every guiding pillar protrudes to form a holding portion, and the motor is used for rotating the rotatable chuck. | 2015-11-12 |
20150325467 | METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING BARRIER LAYERS FOR INTERCONNECT STRUCTURES - Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a barrier layer overlying a metal line of a metallization layer above a semiconductor substrate using an atomic layer deposition (ALD) process and a physical vapor deposition (PVD) process. A liner-forming material is deposited overlying the barrier layer to form a liner. A conductive metal is deposited overlying the liner. | 2015-11-12 |
20150325468 | METHOD FOR PREPARING MATERIAL ON INSULATOR BASED ON ENHANCED ADSORPTION - Provided is a method for preparing a material on an insulator based on enhanced adsorption. In the method: first, a single crystal film having a doped superlattice structure, an intermediate layer, a buffer layer and a top layer film are epitaxially grown in succession on a first substrate; then, low dosage ion implantation is performed on the structure on which the top layer film is formed, so that ions are implanted above an upper surface or below a lower surface of the single crystal film having a doped superlattice structure; next, a second substrate having an insulation layer is bonded to the structure on which ion implantation has already been performed, and an annealing treatment is performed, so that a microscopic crack is produced at the single crystal film having a doped superlattice structure to achieve atomic-scale stripping. The effective stripping of bonding wafers is achieved by means of enhanced adsorption. The stripped surface is smooth and has a low roughness, and the quality of the crystal of the top layer film is high. | 2015-11-12 |
20150325469 | Trench Formation using Rounded Hard Mask - A method embodiment includes forming a hard mask over a dielectric layer, patterning the hard mask to form an opening, forming a passivation layer on sidewalls of the opening, and forming a trench in the dielectric layer by extending the opening into the dielectric layer using an etching process. The sidewalls of the opening are etched to form a rounded profile in the hard mask and a substantially perpendicular profile in the dielectric layer. | 2015-11-12 |
20150325470 | Sublithographic Kelvin Structure Patterned With DSA - In one aspect, a DSA-based method for forming a Kelvin-testable structure includes the following steps. A guide pattern is formed on a substrate which defines i) multiple pad regions of the Kelvin-testable structure and ii) a region interconnecting two of the pad regions on the substrate. A self-assembly material is deposited onto the substrate and is annealed at a temperature/duration sufficient to cause it to undergo self-assembly to form a self-assembled pattern on the substrate, wherein the self-assembly is directed by the guide pattern such that the self-assembled material in the region interconnecting the two pad regions forms multiple straight lines. A pattern of the self-assembled material is transferred to the substrate forming multiple lines in the substrate, wherein the pattern of the self-assembled material is configured such that only a given one of the lines is a continuous line between the two pad regions on the substrate. | 2015-11-12 |
20150325471 | Device And Methods For Small Trench Patterning - A semiconductor device and methods for small trench patterning are disclosed. The device includes a plurality of gate structures, and an etch buffer layer. The etch buffer layer includes an overhang component disposed on the upper portion of the gate structures with an edge that extends laterally. The width between the edges of adjacent overhang components is narrower than the width between adjacent gate structures. | 2015-11-12 |
20150325472 | ALIGNMENT TO MULTIPLE LAYERS - A method of aligning a new pattern to more than one previously defined pattern during the manufacture of an integrated circuit. A method of aligning a photolighography pattern reticle to a first previously defined pattern in a first direction and also aligning the photolithography pattern reticle to a second previously defined pattern in a second direction. A method of aligning a photolighography pattern reticle to two previously defined patterns in the same direction. | 2015-11-12 |
20150325473 | INTEGRATED CIRCUITS WITH METAL-TITANIUM OXIDE CONTACTS AND FABRICATION METHODS - Devices and methods for forming semiconductor devices with metal-titanium oxide contacts are provided. One intermediate semiconductor device includes, for instance: a substrate, at least one field-effect transistor disposed on the substrate, a first contact region positioned over at least a first portion of the at least one field-effect transistor between a spacer and an interlayer dielectric, and a second contact region positioned over at least a second portion of the at least one field-effect transistor between a spacer and an interlayer dielectric. One method includes, for instance: obtaining an intermediate semiconductor device and forming at least one contact on the intermediate semiconductor device. | 2015-11-12 |
20150325474 | Self-Aligned Barrier and Capping Layers For Interconnects - An interconnect structure for integrated circuits for copper wires in integrated circuits and methods for making the same are provided. Mn, Cr, or V containing layer forms a barrier against copper diffusing out of the wires, thereby protecting the insulator from premature breakdown, and protecting transistors from degradation by copper. The Mn, Cr, or V containing layer also promotes strong adhesion between copper and insulators, thus preserving the mechanical integrity of the devices during manufacture and use, as well as protecting against failure by electromigration of the copper during use of the devices and protecting the copper from corrosion by oxygen or water from its surroundings. In forming such integrated circuits, certain embodiments of the invention provide methods to selectively deposit Mn, Cr, V, or Co on the copper surfaces while reducing or even preventing deposition of Mn, Cr, V, or Co on insulator surfaces. Catalytic deposition of copper using a Mn, Cr, or V containing precursor and an iodine or bromine containing precursor is also provided. | 2015-11-12 |
20150325475 | METHODS OF PREPARING TUNGSTEN AND TUNGSTEN NITRIDE THIN FILMS USING TUNGSTEN CHLORIDE PRECURSOR - Methods for forming tungsten film using fluorine-free tungsten precursors such as tungsten chlorides are provided. Methods involve depositing a tungsten nucleation layer by exposing a substrate to a reducing agent such as diborane (B | 2015-11-12 |
20150325476 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device of an embodiment includes: a substrate on which a semiconductor circuit is formed; an interlayer insulating film in which a contact hole is formed on the substrate; a catalyst metal film on a side wall of the contact hole; catalyst metal particles on a bottom of the contact hole; graphene on the catalyst metal film; and carbon nanotubes, which penetrates the contact hole, on the catalyst metal particles. | 2015-11-12 |
20150325477 | SUPER CONFORMAL METAL PLATING FROM COMPLEXED ELECTROLYTES - A method for at least partially filling a feature on a workpiece generally includes obtaining a workpiece including a feature; and depositing a first layer in the feature, wherein the chemistry for depositing the first layer has a pH in the range of about 6 to about 13, and includes a metal complexing agent and at least one organic or inorganic additive selected from the group consisting of accelerator, suppressor, and leveler. | 2015-11-12 |
20150325478 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE FABRICATED BY THE METHOD - A method of fabricating a semiconductor device includes stacking an etch target layer, a first mask layer, and a second mask layer on a first surface of a substrate. A plurality of first spacer lines are formed parallel to each other and a first spacer pad line on the second mask layer is formed. A third mask pad in contact with at least the first spacer pad line on the second mask layer is formed. The second mask layer and the first mask layer are etched to form one or more first mask lines, a first mask preliminary pad, and second mask patterns. Second spacer lines are respectively formed covering sidewalls of the first mask preliminary pad and the first mask lines. First mask pads are formed. The etch target layer is etched to form conductive lines and conductive pads connected to the conductive lines. | 2015-11-12 |
20150325479 | METHOD FOR FORMING SELF-ALIGNED CONTACTS/VIAS WITH HIGH CORNER SELECTIVITY - A method of etching self-aligned contact/via features in a low-k dielectric layer disposed below a hardmask, which is disposed below a planarization layer. At least one cycle is provided, where each cycle comprises thinning the planarization layer, forming a deposition layer on the hardmask and planarization layer; and etching the low-k dielectric layer masked by the deposition layer. | 2015-11-12 |
20150325480 | WAFER PROCESSING METHOD - A wafer has a substrate and a laminated layer formed on the substrate. The laminated layer includes low-permittivity insulating films. The laminated layer forms a plurality of crossing division lines and a plurality of devices formed in separate regions defined by the division lines. The processing method includes a cut groove forming step of cutting the substrate of the wafer along each division line by using a first cutting blade having a first thickness, thereby forming a cut groove having a depth smaller than the thickness of the substrate, so that a first uncut portion of the substrate is formed below the cut groove, and a dividing step of dividing the first uncut portion and the laminated layer along each division line by using a second cutting blade having a second thickness smaller than the first thickness or by etching after performing the cut groove forming step. | 2015-11-12 |
20150325481 | CMOS IMPLEMENTATION OF GERMANIUM AND III-V NANOWIRES AND NANORIBBONS IN GATE-ALL-AROUND ARCHITECTURE - Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area. | 2015-11-12 |
20150325482 | INTEGRATED CIRCUITS HAVING IMPROVED GATE STRUCTURES AND METHODS FOR FABRICATING SAME - Integrated circuits with improved gate structures and methods for fabricating integrated circuits with improved gate structures are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with fin structures. A gate-forming material is deposited over the semiconductor substrate and fin structures. The method includes performing a first etch process to etch the gate-forming material to form a gate line having a first side and a second side. The first side and second side of the gate line are bounded with material. The method includes performing a second etch process to etch a portion of the gate line bound by the material to separate the gate line into adjacent gate structures and to define a tip-to-tip distance between the adjacent gate structures. | 2015-11-12 |
20150325483 | FORMATION OF METAL RESISTOR AND E-FUSE - Embodiments of present invention provide a method of forming metal resistor. The method includes forming a first and a second structure on top of a semiconductor substrate in a replacement-metal-gate process to have, respectively, a sacrificial gate and spacers adjacent to sidewalls of the sacrificial gate; covering the second structure with an etch-stop mask; replacing the sacrificial gate of the first structure with a replacement metal gate; removing the etch-stop mask to expose the sacrificial gate of the second structure; forming a silicide in the second structure as a metal resistor; and forming contacts to the silicide. In one embodiment, forming the silicide includes siliciding a top portion of the sacrificial gate of the second structure to form the metal resistor. In another embodiment, forming the silicide includes removing the sacrificial gate of the second structure to expose and silicide a channel region underneath thereof. | 2015-11-12 |
20150325484 | METAL-SEMICONDUCTOR CONTACT STRUCTURE WITH DOPED INTERLAYER - Disclosed herein is a method of forming a metal-to-semiconductor contact with a doped metal oxide interlayer. An insulating layer is formed on a top surface of a semiconductor substrate with target region at the top surface of the semiconductor substrate. An opening is etched through the insulating layer with the opening exposing a top surface of a portion of the target region. A doped metal oxide interlayer is formed in the opening and contacts the top surface of the target region. The remainder of the opening is filled with a metal plug, the doped metal oxide interlayer disposed between the metal plug and the substrate. The doped metal oxide interlayer is formed from one of tin oxide, titanium oxide or zinc oxide and is doped with fluorine. | 2015-11-12 |
20150325485 | Vertical Power MOSFET and Methods of Forming the Same - A device includes a semiconductor layer of a first conductivity type, and a first and a second body region over the semiconductor layer, wherein the first and the second body regions are of a second conductivity type opposite the first conductivity type. A doped semiconductor region of the first conductivity type is disposed between and contacting the first and the second body regions. A gate dielectric layer is disposed over the first and the second body regions and the doped semiconductor region. A first and a second gate electrode are disposed over the gate dielectric layer, and overlapping the first and the second body regions, respectively. The first and the second gate electrodes are physically separated from each other by a space, and are electrically interconnected. The space between the first and the second gate electrodes overlaps the doped semiconductor region. The device further includes a MOS containing device. | 2015-11-12 |
20150325486 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - Provided are a semiconductor device having a high breakdown voltage and attaining the restraint of the action of a parasite bipolar transistor, and a method for producing the device. A high-breakdown-voltage p-channel-type transistor included in the semiconductor device has a first n-type semiconductor layer arranged in a semiconductor substrate and at a main-surface-side (upside) of a p-type region in the semiconductor substrate, and a local n-type buried region arranged just below a first p-type dopant region to contact the first n-type semiconductor layer. | 2015-11-12 |
20150325487 | METHOD FOR THE FORMATION OF FIN STRUCTURES FOR FINFET DEVICES - On a first semiconductor material substrate, an overlying sacrificial layer formed of a second semiconductor material is deposited. In a first region, a first semiconductor material region is formed over the sacrificial layer. In a second region, a second semiconductor material region is formed over the sacrificial layer. The first semiconductor material region is patterned to define a first FinFET fin. The second semiconductor material region is patterned to define a second FinFET fin. The fins are each covered with a cap and sidewall spacer. The sacrificial layer formed of the second semiconductor material is then selectively removed to form an opening below each of the first and second FinFET fins (with those fins being supported by the sidewall spacers). The openings below each of the fins are then filled with a dielectric material that serves to isolate the semiconductive materials of the fins from the substrate. | 2015-11-12 |
20150325488 | VAPOR PHASE GROWTH METHOD AND VAPOR PHASE GROWTH APPARATUS - A vapor phase growth method of growing a film on a substrate by supplying material gases to the substrate while heating the substrate with a heating unit according to an embodiment, the method includes: measuring a temperature of the substrate with a radiation thermometer; executing a temperature feedback control to control an output of the heating unit to cause a measurement value of the radiation thermometer to have a set value when a film is not grown on the substrate; and executing a constant output control to maintain an output of the heating unit constant when a film causing thin-film interference in a wavelength measured by the radiation thermometer is grown on the substrate. | 2015-11-12 |
20150325489 | LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - The light-emitting device has a plurality of light-emitting elements that is mounted on one or more wiring patterns on a substrate. A new light-emitting element that replaces a defective element is mounted on the same wiring pattern on which the defective element is mounted. The defective element or a trace that remains alter removal of the defective element is sealed by a same sealing member by which the new light-emitting element is sealed. | 2015-11-12 |
20150325490 | APPARATUS FOR AND METHOD OF PROCESSING SUBSTRATE - Provided are an apparatus for and a method of processing a substrate. The substrate processing apparatus includes a substrate processing unit to process a substrate using a processing solution containing a mixture of first and second sources; a source supplying part to supply the first and second sources to the substrate processing unit; at least one analyzer to measure a concentration of the second source in the processing solution or a pH value of the processing solution and adjust a measurement reference value of the second source in the processing solution using a standard solution, in which the first and second sources are mixed to have a predetermined concentration or pH value; and a standard solution supplying part to prepare the standard solution using the first and second sources to be supplied from the source supplying part and to supply the standard solution to the at least one analyzer. | 2015-11-12 |
20150325491 | FLEXIBLE MICROELECTRONIC SYSTEMS AND METHODS OF FABRICATING THE SAME - Microelectronic systems encapsulated in a stretchable/flexible material, which is skin/bio-compatible and able to withstand environmental conditions. In one embodiment of the present description, the microelectronic system includes a microelectronic device that is substantially encapsulated in a non-permeable encapsulant, such as, butyl rubbers, ethylene propylene rubbers, fluoropolymer elastomers, or combinations thereof. In another embodiment, the microelectronic system includes a microelectronic device that is substantially encapsulated in a permeable encapsulant, such as polydimethylsiloxane, wherein a non-permeable encapsulant substantially encapsulates the permeable encapsulant. | 2015-11-12 |
20150325492 | SEMICONDUCTOR PACKAGE - A semiconductor package comprises an integrated device, a front side of a material A and a back side of a material B opposite to the front side. Side walls link the front side and the back side. Each side wall is coated with a coating material to at least 80% of its area, wherein the coating material is different from the material A and different from the material B. | 2015-11-12 |
20150325493 | SEMICONDUCTOR DEVICE HAVING A SEMICONDUCTOR MODULE AND A SECURED COOLING BODY - A semiconductor device includes a semiconductor module having a heat conductive portion formed of metal and also having a molded resin having a surface at which the heat conductive portion is exposed, a cooling body secured to the semiconductor module by means of bonding material, and heat conductive material formed between and thermally coupling the heat conductive portion and the cooling body. | 2015-11-12 |
20150325494 | POWER SEMICONDUCTOR MODULE WITH SWITCHING DEVICE AND ASSEMBLY - A power semiconductor module and an arrangement including it. The module includes a housing, a switching device having a substrate connected to the housing, a connecting device, load connection devices and a pressure device movable relative to the housing. The substrate has a first central passage and conductor tracks which are electrically insulated from one another. A power semiconductor component sits on a conductor track. The connecting device has two main surfaces and an electrically conductive film. The pressure device has a pressure body with a second passage, in alignment with the first passage and a first recess. A pressure element projects out of the recess, and presses onto a section of the second main surface. This section is within the surface of the component projects normal to the substrate. The first and second passages receive a fastener which force-fittingly fastens the module to the cooling device. | 2015-11-12 |
20150325495 | ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME, AND SUBSTRATE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: a silicon substrate that includes a heat release mechanism formed on a rear surface thereof; and an element layer that includes a transistor element and is formed on a front surface of the silicon substrate, the heat release mechanism including: a carbon material being a high heat-conducting material such as a CNT that is higher in heat conductivity than the silicon substrate and is formed in a plurality of first holes formed in the rear surface of the silicon substrate; and a carbon material being a heat-conductive film such as a multilayer graphene film that is thermally connected to the CNT in a manner to cover a rear surface side of the silicon substrate. This configuration provides a carbon material-embedded silicon substrate realizing very efficient heat release with a relatively simple configuration to obtain a highly-reliable electronic device. | 2015-11-12 |
20150325496 | INTEGRATED DEVICE COMPRISING WIRES AS VIAS IN AN ENCAPSULATION LAYER - Some novel features pertain to an integrated device that includes a substrate, a first die coupled to the substrate, a first encapsulation layer coupled to the substrate and the first die, and a second encapsulation layer in the first encapsulation layer. The second encapsulation layer includes a set of wires configured to operate as vias. In some implementations, the integrated device includes a set of vias in the first encapsulation layer. In some implementations, the integrated device further includes a second die coupled to the substrate. In some implementations, the second encapsulation layer is positioned between the first die and the second die. In some implementations, the integrated device further includes a cavity in the first encapsulation layer, where the second encapsulation layer is positioned in the cavity. In some implementations, the cavity has a wall that is non-vertical. In some implementations, at least one of the wires is non-vertical. | 2015-11-12 |
20150325497 | 3D CHIP-ON-WAFER-ON-SUBSTRATE STRUCTURE WITH VIA LAST PROCESS - Disclosed herein is a package having a first redistribution layer (RDL) disposed on a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate. The first RDL is bonded to the second RDL. The package further includes an insulating film disposed over the second RDL and around the first RDL and the first semiconductor substrate. A conductive element is disposed in the first RDL. A via extends from a top surface of the insulating film, through the first semiconductor substrate to the conductive element, and a spacer is disposed between the first semiconductor substrate and the via. The spacer extends through the first semiconductor substrate. | 2015-11-12 |
20150325498 | LOW-STRESS VIAS - A component can include a substrate having a front surface and a rear surface remote therefrom, an opening extending from the rear surface towards the front surface, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/° C. The opening can define an inner surface between the front and rear surfaces. The conductive via can include a first metal layer overlying the inner surface and a second metal region overlying the first metal layer and electrically coupled to the first metal layer. The second metal region can have a CTE greater than a CTE of the first metal layer. The conductive via can have an effective CTE across a diameter of the conductive via that is less than 80% of the CTE of the second metal region. | 2015-11-12 |
20150325499 | ELECTRONIC SUBSTRATE - An electronic substrate includes: an electronic element provided on a first face of a semiconductor substrate having a through hole; a passive element provided on a second face of the semiconductor substrate; a first part of an interconnection pattern provided on the second face of the semiconductor substrate; an insulating layer provided on the second face of the semiconductor substrate; and a second part of the interconnection pattern provided on the insulating layer. | 2015-11-12 |
20150325500 | ULTRA-THIN SEMICONDUCTOR DEVICE AND PREPARATION METHOD THEREOF - A small and ultra-thin power semiconductor device and a preparation method are disclosed. The device includes a chip mounting unit with a plurality of pads with a plate arranged on top surface of each pad; a semiconductor chip flipped and attached on the chip mounting unit, where the electrodes at the front of the chip are electrically connected to the pads; a plastic packaging body covering the chip mounting units and the chip, where the top surface of the plate and the back surface of the chip are exposed out from top surface of the plastic packaging body and the bottom surfaces of the pads are exposed out of the bottom surface of the plastic packaging body; a plurality of top metal segments arranged on the top surface of the plastic packaging body and electrically connected to the top surface of each plate and the back surface of the chip. | 2015-11-12 |
20150325501 | Cantilevered Leadframe Support Structure for Magnetic Wireless Transfer Between Integrated Circuit Dies - A coupling device provides galvanic isolation using a leadframe that is configured to support two integrated circuit chips in a coplanar manner. Each chip contains an inductive coupling coil. The lead frame includes a set of bond pads for attaching bond wires to couple to the two integrated circuit chips. Two separated die attach pads support the two chips. Each die attach pad is configured to support one of the two integrated circuit chips with a plurality of cantilevered fingers. | 2015-11-12 |
20150325502 | SEMICONDUCTOR DEVICE WITH STEP PORTION HAVING SHEAR SURFACES - A semiconductor device includes a source electrode pad formed to a front surface of a semiconductor chip and a metal clip (metal plate) to which a lead is electrically connected. The metal clip includes a chip-connecting portion electrically connected to the source electrode pad via a conductive bonding material, a lead-connecting portion electrically connected to the lead via a conductive bonding material, and an intermediate portion positioned between the chip-connecting portion and the lead-connecting portion. Further, between the intermediate portion and the chip-connecting portion, a step portion, which has shear surfaces disposed to face each other, is provided interposing a joining portion. | 2015-11-12 |
20150325503 | Method of singularizing packages and leadframe - A method of singularizing a matrix array of packages is provided, wherein the method comprises providing a matrix array of packages, wherein the matrix array is formed on a leadframe; cutting predefined leads of the leadframe by a punching process; and singularizing the packages of the matrix array of packages by a sawing process. | 2015-11-12 |
20150325504 | SEMICONDUCTOR DEVICE - A semiconductor device is provided with a semiconductor element, a main lead on which the semiconductor element is disposed, and a resin package that covers the semiconductor element and the main lead. A notch that is recessed toward the center of the main lead in plan view as seen in the thickness direction of the semiconductor element is formed in the main lead. | 2015-11-12 |
20150325505 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a functional block unit, external terminals and, and an external resin sealing body. The functional block unit includes an internal resin sealing body having an edge and an opposite edgeb. The edge side of the internal resin sealing body covers a first end of an internal terminal, but does not cover a second end of the internal terminal. The edge side of the internal resin sealing body covers a first end of an internal terminal, but does not cover a second end of the internal terminal. The external resin sealing body covers the root portion and a portion of the middle portion of the external terminal, but does not cover the terminal portion of the external terminal. The functional block unit and the external terminals and are integrally connected together and sealed by the external resin sealing body. | 2015-11-12 |
20150325506 | SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF - There is provided a technology enabling the improvement of the reliability of a semiconductor device manufactured by physically fixing separately formed chip mounting portion and lead frame. A feature of an embodiment resides in that, a second junction portion formed in a suspension lead is fitted into a first junction portion formed in a chip mounting portion, thereby to physically fix the chip mounting portion and the suspension lead. Specifically, the first junction portion is formed of a concave part disposed in the surface of the chip mounting portion. The second junction portion forms a part of the suspension lead. | 2015-11-12 |
20150325507 | CONDUCTIVE CONNECTIONS, STRUCTURES WITH SUCH CONNECTIONS, AND METHODS OF MANUFACTURE - A solder connection may be surrounded by a solder locking layer ( | 2015-11-12 |
20150325508 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF AND CARRIER STRUCTURE - A carrier structure is provided, which includes: a metal oxide plate having opposite first and second surfaces and a plurality of through holes penetrating the first and second surfaces; a plurality of conductive portions formed in the through holes, respectively; and a plurality of conductive pads formed on the first surface of the metal oxide plate, wherein each of the conductive pads is correspondingly positioned on and in contact with a plurality of the conductive portions so as to be electrically connected to the plurality of the conductive portions. By replacing a conventional silicon interposer with the metal oxide plate, the present invention eliminates the need to form through silicon vias as required in the prior art and therefore simplifies the fabrication process. | 2015-11-12 |
20150325509 | SUBSTRATE BLOCK FOR PoP PACKAGE - A substrate block is provided that has an increased width. The substrate block comprises two substrate bars, and the substrate bars each comprise a substrate and a plurality of filled vias through the substrate. The substrate block may be used to manufacture package substrates, and these package substrate may be incorporated into a PoP structure. The package substrate includes a carrier having a plurality of vertical interconnections and a bar coupled to the vertical interconnections. | 2015-11-12 |
20150325510 | CHIP ELECTRONIC COMPONENT AND METHOD OF MANUFACTURING THE SAME - A chip electronic component may be capable of improving connectivity between internal coils formed on upper and lower surfaces of an insulating substrate and preventing loss of inductance due to the areas of via pads by decreasing sizes of the outermost via electrodes and decreasing sizes of the via pad. | 2015-11-12 |
20150325511 | SEMICONDUCTOR PACKAGES AND METHODS OF PACKAGING SEMICONDUCTOR DEVICES - Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a package substrate having first and second major surfaces. The package substrate includes a base substrate having a mold material and a plurality of interconnect structures including via contacts extending through the first to the second major surface of the package substrate. A die having conductive contacts on its first or second surface is provided. The conductive contacts of the die are electrically coupled to the interconnect structures. A cap is formed over the package substrate to encapsulate the die. | 2015-11-12 |
20150325512 | MULTI-DIE, HIGH CURRENT WAFER LEVEL PACKAGE - Wafer-level package semiconductor devices for high-current applications are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar. The wafer-level package device also includes an integrated circuit chip device (e.g., small die) configured upon the integrated circuit chip (e.g., large die). In the wafer-level package device, the height of the integrated circuit chip device is less than the height of the pillar and/or less than the combined height of the pillar and the one or more solder contacts. | 2015-11-12 |
20150325513 | Slot-Shielded Coplanar Strip-line Compatible with CMOS Processes - A strip-line includes a ground plane extending through a plurality of dielectric layers over a substrate; a signal line over the substrate and on a side of the ground plane; a first plurality of metal strips under the signal line and in a first metal layer, wherein the first plurality of metal strips is parallel to each other, and is spaced apart from each other by spaces; and a second plurality of metal strips under the signal line and in a second metal layer over the first metal layer. The second plurality of metal strips vertically overlaps the spaces. The first plurality of metal strips is electrically coupled to the second plurality of metal strips through the ground plane, and no via physically contacts the first plurality of metal strips and the second plurality of metal strips. | 2015-11-12 |
20150325514 | HIGH DENSITY SRAM ARRAY DESIGN WITH SKIPPED, INTER-LAYER CONDUCTIVE CONTACTS - A static random access memory (SRAM) cell includes a first conductive layer including a wordline landing pad extending into a neighboring memory cell in an adjacent row of a memory array. The wordline landing pad in the first conductive layer is electrically isolated from all gate contacts of the neighboring memory cell. The SRAM cell also includes a second conductive layer including a wordline coupled to the wordline landing pad in the first conductive layer. The SRAM cell further includes a first via coupling a gate contact of a pass transistor gate in the SRAM cell to the wordline landing pad in the first conductive layer. The SRAM cell also includes a second via coupling the wordline landing pad and the wordline of the second conductive layer. | 2015-11-12 |
20150325515 | VIA MATERIAL SELECTION AND PROCESSING - Semiconductor interconnects and methods for making semiconductor interconnects. An interconnect may include a first via of a first conductive material between a first conductive interconnect layer and a first middle of line (MOL) interconnect layer. The first MOL interconnect layer is on a first level. The first via is fabricated with a single damascene process. Such a semiconductor interconnect also includes a second via of a second conductive material between the first conductive interconnect layer and a second MOL interconnect layer. The second MOL interconnect layer is on a second level. The second via is fabricated with a dual damascene process. The first conductive material is different than the second conductive material. | 2015-11-12 |
20150325516 | CORELESS PACKAGING SUBSTRATE, POP STRUCTURE, AND METHODS FOR FABRICATING THE SAME - A method for fabricating a coreless packaging substrate is provided, which includes: forming a dielectric layer on a conductive plate having a plurality of conductive pads; forming a circuit layer on the dielectric layer and forming in the dielectric layer a plurality of conductive vias that electrically connect the circuit layer and the conductive pads; and removing a portion of the conductive plate so as to cause the remaining portion of the conductive plate to form a plurality of conductive elements, thereby dispensing with a core layer and reducing the material and fabrication cost. | 2015-11-12 |
20150325517 | Structure And Method For A High-K Transformer With Capacitive Coupling - The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having an integrated circuit (IC) device; an interconnect structure disposed on the semiconductor substrate and coupled with the IC device; and a transformer disposed on the semiconductor substrate and integrated in the interconnect structure. The transformer includes a first conductive feature; a second conductive feature inductively coupled with the first conductive feature; a third conductive feature electrically connected to the first conductive feature; and a fourth conductive feature electrically connected to the second conductive feature. The third and fourth conductive features are designed and configured to be capacitively coupled to increase a coupling coefficient of the transformer. | 2015-11-12 |
20150325518 | SEMICONDUCTOR DEVICE HAVING FUSE PATTERN - A semiconductor device has improved reliability by preventing a fuse cut through a repair process from being electrically reconnected by electrochemical migration. The semiconductor device includes a substrate, a fuse including a first fuse pattern and a second fuse pattern formed at the same level on the substrate, the first fuse pattern and the second fuse pattern being spaced a first width apart from each other such that a gap in the fuse is disposed at a first location between the first fuse pattern and the second fuse pattern, and a first insulation layer formed on the first fuse pattern and the second fuse pattern, the first insulation layer including an opening above the first location and having a second width smaller than the first width. | 2015-11-12 |
20150325519 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SUCH SEMICONDUCTOR DEVICE - The invention relates to a semiconductor device comprising: i) a substrate ( | 2015-11-12 |
20150325520 | 3D CHIP-ON-WAFER-ON-SUBSTRATE STRUCTURE WITH VIA LAST PROCESS - Disclosed herein is a package comprising a first redistribution layer (RDL) disposed on a first side of a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate, wherein the first RDL is bonded to the second RDL. First conductive elements are disposed in the first RDL and the second RDL. First vias extend from one or more of the first conductive elements through the first semiconductor substrate to a second side of the first semiconductor substrate opposite the first side. First spacers are interposed between the first semiconductor substrate and the first vias and each extend from a respective one of the first conductive elements through the first semiconductor substrate. | 2015-11-12 |
20150325521 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR CHIP - The present invention is applicable to a semiconductor device having a plurality of chips being stacked with a TSV structure in which adjacent ones of the chips are connected to each other via a plurality of through electrodes. Each of the chips includes a plurality of TSV array portions provided so as to correspond to a plurality of channels. The TSV array portions include a TSV array portion that contributes to an input and an output depending upon the number of the chips being stacked, and a pass-through TSV array portion that is not connected to an input/output circuit. | 2015-11-12 |
20150325522 | INTERCONNECT STRUCTURE AND MANUFACTURING METHOD THEREOF - A method for manufacturing a semiconductor comprises: providing a substrate; forming an opening in a dielectric layer disposed over the substrate; providing a target with a first type atoms; ionizing the first type atoms provided from the target; providing a bias to the substrate for controlling the moving paths of the ionized first type atoms thereby directing the ionized first type atoms in the opening; and forming a first conductive structure from bottom of the opening with the ionized first type atoms under a pre-determined frequency and a pre-determined pressure. | 2015-11-12 |