46th week of 2012 patent applcation highlights part 20 |
Patent application number | Title | Published |
20120286794 | System and Method for Monitoring and Balancing Voltage of Individual Battery Cells within a Battery Pack - Systems and methods for a scalable battery controller are disclosed. In one example, a circuit board coupled to a battery cell stack is designed to be configurable to monitor and balance battery cells of battery cell stacks that may vary depending on battery pack requirements. Further, the battery pack control module may configure software instructions in response to a voltage at a battery cell stack. | 2012-11-15 |
20120286795 | METHODS, SYSTEMS, AND APPARATUS FOR DETECTING LIGHT AND ACOUSTIC WAVES - A sensor includes a sensor head including an acoustic detector configured to receive light from a first light source and to reflect the light upon incidence of acoustic waves. The sensor also includes at least one optical fiber and at least one fluorescent material within at least one of the sensor head and the at least one optical fiber. The at least one fluorescent material is configured to receive light from a second light source external to the sensor and emit visible light in response to the light received from the second light source. | 2012-11-15 |
20120286796 | ACTIVE 2-DIMENSIONAL ARRAY STRUCTURE FOR PARALLEL TESTING - A structure and method is provided for testing a 2-dimensional array of electrical devices, such as a 2-dimensional array in the first metal level (M1) of an electronic structure. The method for testing the 2-dimensional array provides a parallel test approach. The test structure provides a plurality of test pad structures to implement the parallel test approach. The test pad structures may include field effect transistors. | 2012-11-15 |
20120286797 | ELECTROMAGNETIC WAVE MEASUREMENT DEVICE, MEASUREMENT METHOD, AND RECORDING MEDIUM - According to the present invention, an electromagnetic wave measurement device includes an electromagnetic wave output device, an electromagnetic wave detector and a measurement unit. The electromagnetic wave output device outputs an electromagnetic wave having a frequency equal to or more than 0.01 [THz] and equal to or less than 100 [THz] toward a device under test including at least two layers, and the electromagnetic wave detector detects reflected electromagnetic waves which are the electromagnetic waves reflected by the respective at least two layers. The measurement unit measures the device under test based on one or both of extreme values of electric fields of the respective reflected electromagnetic waves and a time difference between timings in which the electric fields of the respective reflected electromagnetic waves take the extreme values. | 2012-11-15 |
20120286798 | Methods of Testing a Connection Between Speakers and a Power Amplifier and Devices Therefor - The present disclosure provides methods and devices for testing a connection between speakers and a power amplifier. The disclosed methods and devices solve a problem that, upon a connection test for a power amplifier which has a booster power source, when a midpoint potential of the power amplifier and the voltage of the speaker connection terminal are compared, and it is determined that short-circuiting occurs on a ground side when the potential of the speaker connection terminal is lower than the midpoint potential, a wrong test is conducted if a midpoint potential is higher than a battery voltage. | 2012-11-15 |
20120286799 | TEST FIXTURE FOR RF TESTING - A test fixture for performing RF testing. The test fixture includes a base plate configured to support an electronic device. The base plate defines a grid of grooves. The base plate further defines a cut-out configured to receiving an antenna in one or more positions. The test fixture further includes markers indicating positioning of the electronic device on the base plate. | 2012-11-15 |
20120286800 | CAPACITANCE SENSOR WITH SENSOR CAPACITANCE COMPENSATION - A capacitance sensing circuit may include a switching circuit configured to generate a sensor current by charging and discharging a capacitive sensor electrode, and a current mirror that generates a mirror current based on the sensor current. Based on the mirror current, a measurement circuit generates an output signal representative of a capacitance of the capacitive sensor electrode. | 2012-11-15 |
20120286801 | MANUFACTURING METHOD, SWITCHING APPARATUS, TRANSMISSION LINE SWITCHING APPARATUS, AND TEST APPARATUS - An actuator is manufactured that includes piezoelectric film that does not suffer physical damage. Provided is a manufacturing method comprising first insulating layer deposition of depositing a first insulating layer on a substrate using an insulating material; first annealing of annealing the first insulating layer; first electrode layer deposition of depositing a first electrode layer on the first insulating layer using a conductive material; first piezoelectric film deposition of depositing a first piezoelectric film on the first electrode layer by applying a sol-gel material on the first electrode layer and annealing the sol-gel material; second electrode layer deposition of depositing a second electrode layer on the first piezoelectric film using a conductive material; second insulating layer deposition of depositing a second insulating layer on the second electrode layer using an insulating material; and second annealing of annealing the second insulating layer. | 2012-11-15 |
20120286802 | Sensor Electronics for a Plurality of Sensor Elements and Method for Determining a Position of an Object at The Sensor Elements - An electronic circuit with a plurality of connections for a plurality of sensor elements is provided, wherein the electronic circuit is configured to detect, with at least one multiplexing method, the presence of an object in at least one observation area of the sensor elements and to distinguish between the sensor elements. Also a method for determining the position of at least one object situated in at least one observation area of sensor elements relative to the sensor elements is provided, whereby with a multiplexing method an electric variable for each sensor element is detected, which is indicative for the presence of the object in the respective observation area. | 2012-11-15 |
20120286803 | Sensor - The invention relates to an electrochemical sensor integrated on a substrate, the electrochemical sensor comprising: a field effect transistor integrated on the substrate and having a source, gate and drain connections, said gate of the field effect transistor comprising: a sensing gate conductively coupled to a sensing electrode; and a bias gate, wherein the sensing gate is capacitively coupled to the bias gate and the bias gate is capacitively coupled to the substrate. | 2012-11-15 |
20120286804 | SENSOR DEVICE - A sensor device includes a first electrode, a second electrode and a functional element. The first electrode includes a porous body having a connecting hole where adjacent holes communicate with each other with the porous body being in at least the vicinity of a surface of the first electrode. The second electrode is spaced apart from the first electrode. The functional element is configured to measure a difference in electric potential between the first electrode and the second electrode. The sensor device is configured to measure a state of a site to be measured based on the difference in electric potential as measured by the functional element. | 2012-11-15 |
20120286805 | LOADING STATE DETERMINER, LOAD ASSEMBLY, POWER SUPPLY CIRCUIT AND METHOD FOR DETERMINING A LOADING STATE OF AN ELECTRIC POWER SOURCE - A loading state determiner for determining a loading state of an electric power source including a source impedance includes a voltage drop determination circuit which is implemented to provide, based on a detection of an instantaneous current provided under load by the power source to a load, an electric quantity describing a voltage drop at a source impedance of the power source. Further, the loading state determiner includes an evaluation circuit which is implemented to obtain, based on electric quantity describing the voltage drop at the source impedance of the power source and an electric quantity describing a terminal voltage of the power source, a load state signal carrying information on an instantaneous relation between the terminal voltage of the power source and a no-load voltage of the power source. | 2012-11-15 |
20120286806 | Measuring Bulk Lifetime - A substrate is electromagnetically coupled into an inductance-capacitance resonant circuit formed from (i) a member comprising a ferromagnetic material, (ii) an inductor and (iii) the substrate. The substrate is illuminated for a first time period X to cause photoconduction in the substrate. Decay in conductivity of the substrate is monitored for a second time period Y. The ratio of X to Y is greater than 1:10. Bulk lifetime of the substrate is determined from the decay. | 2012-11-15 |
20120286807 | ELECTRONIC CIRCUIT AND METHOD FOR DETERMINING AN IMPEDANCE - An electronic circuit is arranged in an external programming device and is used for contactless programming of a circuit to be programmed. The electronic circuit has a series resonant circuit that includes a transmitter coil and a capacitor. The transmitter coil of the series resonant circuit is used for inductive coupling to a receiver coil in the circuit to be programmed. For the purpose of evaluating the impedance that actually exists in the circuit to be programmed, there is provided a device for determining the value of the impedance from a phase difference between the control voltage of the series resonant circuit and the capacitor voltage of the series resonant circuit. | 2012-11-15 |
20120286808 | SYSTEM FOR LOCATING AND IDENTIFYING AT LEAST TWO SEPARATE ITEMS - A system for locating and identifying at least two separate items, for example packaging, includes a capacitive first sensor detecting a first measuring region at a first position of a sensor device, for example a sensor film on a shelf bottom for packaging, a capacitive second sensor detecting a second measuring region at a second position, differing from the first position, of the sensor device, an electrically conductive first mark of a first item in the measuring region of one sensor, an electrically conductive second mark of a second item in the measuring region of the other sensor, and an evaluation device evaluating signals from the sensors, the signals caused or changed by electrical conductivity of the marks. Items can be capacitively detected and information obtained can be used to improve warehousing. The sensors and the marks can be produced quickly and cost-effectively by printing processes or film transfer. | 2012-11-15 |
20120286809 | Circuit Arrangement for Determining a Capacitance of a Number of Capacitive Sensor Elements - A circuit arrangement for determining a capacitance of a number n of capacitive sensor elements (SE | 2012-11-15 |
20120286810 | FLUID QUALITY SENSOR - An object of the present invention is to accurately detect concentrations of mixtures in a fluid. An internal electrode | 2012-11-15 |
20120286811 | CAPACITANCE DIFFERENCE DETECTING METHOD - A capacitance difference detecting method, comprising: (a) utilizing a voltage control unit to cooperate with a first capacitor to be detected and a second capacitor to be detected to generate a first voltage and a second voltage; and (b) computing a capacitance difference between the first capacitor to be detected and the second capacitor to be detected according to the first voltage, the second voltage and a parameter of the voltage control unit. | 2012-11-15 |
20120286812 | CAPACITANCE DIFFERENCE DETECTING CIRCUIT - A capacitance difference detecting circuit, which comprises: a control circuit, for generating a control signal according to a first voltage and a second voltage; a first capacitor to be detected; a second capacitor to be detected; a voltage control unit, for cooperating with the first capacitor to be detected and the second capacitor to be detected, according to the control signal, to generate the first voltage and the second voltage; and a computing device, for computing a capacitance difference between the first capacitor to be detected and the second capacitor to be detected according to the first voltage, the second voltage and a parameter of the voltage control unit. | 2012-11-15 |
20120286813 | WINDSHIELD MOISTURE DETECTOR - A system, controller, and method for detecting moisture on a windshield that uses an isolated electrode coupled to a windshield. The isolated electrode is configured to exhibit an electrical impedance indicative of moisture present on a surface the windshield. The controller is configured to determine an electrode impedance value corresponding to the electrical impedance exhibited by the isolated electrode for detecting moisture on the windshield. By using an isolated electrode, the system is simpler and less expensive than other systems that have at least one electrode providing a return path for another electrode. Also, a way to use the isolated electrode for both detecting moisture on the windshield, and heating the windshield is described. | 2012-11-15 |
20120286814 | 3D IC Testing Apparatus - A three dimensional (3D) integrated circuit (IC) testing apparatus comprises a plurality of connection devices. When a device under test (DUT) such as an interposer or a 3D IC formed by a plurality of 3D dies operates in a testing mode, the 3D IC testing apparatus is coupled to the DUT via a variety of interface channels such as probes. The connection devices and a variety of through silicon vias (TSVs) in the DUT form a TSV chain so that a electrical characteristic test of the variety of TSVs can be tested all at once. | 2012-11-15 |
20120286815 | Inspection Device Applying Probe Contact for Signal Transmission - An inspection device applying probe contact for signal transmission includes an inspection panel board; a probe base disposed on the inspection panel board and having a plurality of probes; a receiving moldboard disposed on the inspection panel board and including a fillister for receiving inspected portable electronic apparatus, and an open slot allocated facing the plurality of probes of the probe base, thereby enabling the plurality of probes to contact with corresponding signal terminals of the portable electronic apparatus; and a clamp unit disposed on the inspection panel board and consisting of an adjustable rod and a clamp block allocated at one end of the adjustable rod, the adjustable rod adjusting position of the clamp block, thereby clamping and properly positioning the portable electronic apparatus in the receiving moldboard. | 2012-11-15 |
20120286816 | PROBES WITH HIGH CURRENT CARRYING CAPABILITY AND LASER MACHINING METHODS - The present invention is a probe having a distal end made of one material, a tip and a portion disposed between the distal end and the tip that is a different second material. The probe is laser machined manufactured using a nanosecond or picosecond laser. | 2012-11-15 |
20120286817 | PROBE HEAD ASSEMBLIES, COMPONENTS THEREOF, TEST SYSTEMS INCLUDING THE SAME, AND METHODS OF OPERATING THE SAME - Probe head assemblies, components of probe head assemblies, test systems including the probe head assemblies and/or components thereof, and methods of operating the same. The probe head assemblies are configured to convey a plurality of test signals to and/or from a device under test and include a space transformer, a contacting assembly, and a riser that spatially separates the space transformer from the contacting assembly and conveys the plurality of test signals between the space transformer and the contacting assembly. The contacting assembly may include a frame that defines an aperture and has a coefficient of thermal expansion that is within a threshold difference of that of the device under test, a flexible dielectric body that is attached to the frame, maintained in tension by the frame, and extends across the aperture, and a plurality of conductive probes. The plurality of conductive probes may include a dual-faceted probe tip. | 2012-11-15 |
20120286818 | ASSEMBLY FOR OPTICAL BACKSIDE FAILURE ANALYSIS OF WIRE-BONDED DEVICE DURING ELECTRICAL TESTING - Systems, methods, devices, and computer program products are described for allowing optical backside failure analysis of a wire-bonded semiconductor device concurrent with electrical testing of the device. For example, a semiconductor device is prepared and mounted in the optical testing subsystem, such that a circuit region of the device is exposed to an optical testing environment, and an analog to the original array of the device is presented via the optical testing subsystem as a derived array. The electrical testing subsystem converts the derived array to a test array, and presents the test array in a way that is physically and electrically compatible with a test socket of an electrical testing environment. By coupling the electrical testing subsystem with the optical testing subsystem, a pin-to-pin coupling may be effectuated between the test array of the test socket and bonding locations on the device corresponding to the device's original array. | 2012-11-15 |
20120286819 | MOS TEST STRUCTURE, METHOD FOR FORMING MOS TEST STRUCTURE AND METHOD FOR PERFORMING WAFER ACCEPTANCE TEST - A MOS test structure is disclosed. A scribe line region is disposed on a substrate which has a first side and a second side opposite to the first side. An epitaxial layer is disposed on the first side, the doping well is disposed on the epitaxial layer and the doping region is disposed on the doping well. A trench gate of a first depth is disposed in the doping region, in the doping well and in the scribe line region. A conductive material fills the test via which has a second depth and an isolation covering the inner wall of the test via and is disposed in the doping region, in the doping well, in the epitaxial layer and in the scribe line region, to electrically connect to the epitaxial layer so that the test via is capable of testing the epitaxial layer and the substrate together. | 2012-11-15 |
20120286820 | METHODS TO DETECT A SINGLE POINT OF FAILURE - A method of detecting a single point of failure includes: placing a portion of a machine being monitored by a plurality of monitoring devices in a first position; causing the portion to cycle to a second position during a first cycle; measuring a component of electrical power provided by a first power supply unit while the portion cycles during the first cycle; returning the portion to the first position; causing the portion to cycle to the second position during a second cycle; measuring the component of electrical power provided by a second power supply during the second cycle; determining that an amount of the component of electrical power provided during either the first or second cycle is equal to or less than a minimum value; and generating an alarm. | 2012-11-15 |
20120286821 | SYSTEMS AND METHODS FOR CONFIGURING AN SOPC WITHOUT A NEED TO USE AN EXTERNAL MEMORY - Systems and techniques for configuration of a system on a programmable chip (SOPC) are described. By configuring the SOPC, during power-up, with a voltage input instead of with a flash memory or another non-volatile memory, the systems and techniques may save cost and board space. | 2012-11-15 |
20120286822 | AUTOMATED METAL PATTERN GENERATION FOR INTEGRATED CIRUCITS - An integrated circuit fabricated by a mask set including a mask to generate a metal pattern defined by CAD software, the metal pattern generation method including: reading a binary data set, the data points in the set uniquely matched to a plurality of fixed metal tabs; and selecting a metal tab from a first set of selectable metal tabs for a first data value, or a second set of selectable metal tabs for a second data value for each of the fixed metal tabs; wherein a first set metal tab and a second set metal tab couples each said fixed metal tab to first and second voltages respectively. | 2012-11-15 |
20120286823 | SEMICONDUCTOR DEVICE - A semiconductor device in which an input terminal is electrically connected to a first terminal of a first transmission gate; a second terminal of the first transmission gate is electrically connected to a first terminal of a first inverter and a second terminal of a functional circuit; a second terminal of the first inverter and a first terminal of the functional circuit are electrically connected to a first terminal of a second transmission gate; a second terminal of the second transmission gate is electrically connected to a first terminal of a second inverter and a second terminal of a clocked inverter; a second terminal of the second inverter and a first terminal of the clocked inverter are electrically connected to an output terminal; and the functional circuit includes a data holding portion between a transistor with small off-state current and a capacitor. | 2012-11-15 |
20120286824 | Supplying a clock signal and a gated clock signal to synchronous elements - A clock gating circuitry unit for supplying either a clock signal or a predetermined gated value to a plurality of synchronous elements within an integrated circuit is disclosed. The clock gating circuitry is configured to receive a clock signal and to output an output signal comprising either the clock signal or the predetermined gated value. The clock gating circuitry unit receives a clock signal, a clock enable signal having either an enable value indicating the plurality of synchronous elements to are currently functional and are to be clocked, or a disable value indicating the plurality of synchronous elements are currently not required and are not to be clocked, and a power mode signal having either a low power value indicating entry to a low power mode in which at least a portion of the plurality of synchronous elements are powered to retain data and are not clocked and at least a further portion of the plurality of synchronous elements are powered down, or a functional mode value indicating the plurality of synchronous elements are to be powered. The clock gating unit has logic circuitry that is configured in response to the clock enable signal having the enable value and to the low power mode signal having the functional mode value to output the clock signal and in response to at least one of the clock enable signal having the disable value and the low power mode signal having the low power value to output the predetermined gated value. | 2012-11-15 |
20120286825 | Method and Device for Monitoring a Frequency Signal - A method for monitoring a frequency signal provided within a unit is disclosed. The method comprises a step of receiving one or more binary signal levels of a cycle signal (CLK) or a control signal (CS) from a communication interface (CLK, CS, MOSI, MISO), wherein the communication interface (CLK, CS, MOSI, MISO) is designed to transfer information according to a communication protocol. The method further comprises a step of providing the frequency signal in the unit and comparing the frequency signal to a temporal sequence of signal levels of the cycle signal (CLK) received by the communication interface (CLK, CS, MOSI, MISO) in order to obtain a comparison result or controlling a counter by the control signal (CS) and the frequency signal in order to obtain a counter status. Finally, the method according to the disclosure comprises a step of recognizing a predetermined quality of the frequency signal if the comparison result fulfills a predetermined criterion or if the counter status lies within a predetermined value range in order to monitor by the recognized quality of the frequency signal. | 2012-11-15 |
20120286826 | Switching Power Converter Input Voltage Approximate Zero Crossing Determination - In at least one embodiment, the controller senses a leading edge, phase cut AC input voltage value to a switching power converter during a cycle of the AC input voltage. The controller senses the voltage value at a time prior to a zero crossing of the AC input voltage and utilizes the voltage value to determine the approximate zero crossing. In at least one embodiment, by determining an approximate zero crossing of the AC input voltage, the controller is unaffected by any disturbances of the dimmer that could otherwise make detecting the zero crossing problematic. In at least one embodiment, the controller approximates the AC input voltage using a function that estimates a waveform of the AC input voltage and determines the approximate zero crossing of the AC input voltage from the approximation of the AC input voltage. | 2012-11-15 |
20120286827 | VOLTAGE-TO-CURRENT CONVERTER CIRCUIT - A voltage-to-current converter circuit has a differential input unit, and is provided with an input offset voltage, wherein the temperature characteristics of the differential input unit and input offset voltage are substantially flat. A current is supplied wherein a second fixed current having positive temperature characteristics is added to a first fixed current having flat characteristics as a bias current to the differential input unit, to balance the temperature characteristics of the differential input unit and the temperature characteristics of the bias current, thus causing the differential input unit transconductance temperature characteristics to be substantially zero (e.g., substantially flat). | 2012-11-15 |
20120286828 | Apparatus and Method for Introducing a Controllable Delay to an Input Signal - An apparatus including a first electrode portion configured to inject charge carriers; a second electrode portion configured to collect charge carriers and provide an output signal; a third electrode portion configured to collect charge carriers and provide an output signal; a monolithic semiconductor, providing a first channel for the transport of injected charge carriers between the first electrode portion and the second electrode portion and providing a second channel for the transport of injected charge carriers between the first electrode portion and the third electrode portion, wherein the first channel is configured such that a charge carrier injected at the first electrode portion will reach the second electrode portion via the first channel after a first transport time and the second channel is configured such that a charge carrier injected at the first electrode portion will reach the third electrode portion via the second channel after a second transport time greater than the first transport time; and at least one gate electrode coupled to the monolithic semiconductor configured to enable switching a route for charge carrier transport between at least the first channel and the second channel. | 2012-11-15 |
20120286829 | SEMICONDUCTOR DEVICE AND DRIVING CIRCUIT - A high breakdown voltage semiconductor device includes: an n | 2012-11-15 |
20120286830 | Clock Generation System - A clock generation system for generating first and second clock signals at slightly different clock frequencies comprising a clock signal generator providing the first clock signal, frequency dividers dividing the clock frequencies by integers to produce auxiliary signals, a timer for measuring a first time lag between first signal edges of the auxiliary signals and a second time lag between second signal edges of the auxiliary signals, a comparator device for providing an error signal by comparing the difference between the measured time lags with a predetermined time value, and a voltage-controlled oscillator controlled in dependent on the error signal to generate the second clock signal. | 2012-11-15 |
20120286831 | CIRCUIT AND METHOD FOR GENERATING A CLOCK SIGNAL - A circuit comprises a frequency divider coupled to receive an oscillating signal generated by an oscillator and a division ratio and configured to divide the oscillating signal by the division ratio into a clock signal; a temperature compensation circuit configured to measure a temperature of the oscillator and generate a division ratio to be provided to the frequency divider and a first value on the basis of the measured temperature; and a control system configured to control connection between a calibration element and the oscillator based on the first value and the oscillating signal of the oscillator. | 2012-11-15 |
20120286832 | Data Synchronization Circuit - The invention concerns a circuit comprising: a first circuit block ( | 2012-11-15 |
20120286833 | Power-On Reset Circuit - An integrated circuit provides a power on reset signal with respect to a supply voltage level supplying the electronic device. The integrated circuit comprises a bias current generating stage having a first current mirror and an output stage having first, second and third series connected MOS transistors. A connection between the second MOS transistor and the third MOS transistor forms a POR output node. A gate of the second MOS transistor and a gate of the third MOS transistor are coupled to each other and to the first current mirror. This allows a current through the third MOS transistor when the supply voltage is higher than a first MOS transistor threshold and a current through the second MOS transistor only when the supply voltage is greater than or equal to the sum of the first MOS transistor threshold and a second MOS transistor threshold voltage. | 2012-11-15 |
20120286834 | PHASE LOCKED LOOP - A phase locked loop is provided. The phase locked loop includes a detector, a controlled oscillator and a filtering unit coupled between the detector and the controlled oscillator. The detector generates a phase difference signal according to a reference frequency and an oscillation signal. The controlled oscillator generates the oscillation signal according to a filtered signal. The filtering unit filters the phase difference signal to generate the filtered signal, and the filtering unit has a high frequency filter of which a pole is greater than the reference frequency and less than a frequency of the oscillation signal. | 2012-11-15 |
20120286835 | PLL CIRCUIT - A PLL circuit includes: a frequency division section; a phase detector configured to detect the phase difference between a reference clock signal and an output signal of the frequency division section; a loop filter configured to filter an output signal of the phase detector and output the result as a digital value; a selector configured to select either the digital value or a fixed value; a digitally controlled oscillator configured to oscillate at a frequency corresponding to the value selected by the selector; and a control section configured to instruct the selector to select the fixed value until receiving a start signal, and after receiving the start signal, instruct the selector to select the digital value, and the frequency division section to start output, at timing of an edge of the reference clock signal. | 2012-11-15 |
20120286836 | Built-in Self-test Circuit for Voltage Controlled Oscillators - A built-in self-test circuit for testing a voltage controlled oscillator comprises a voltage controlled oscillator, a buffer having an input coupled to an output of the voltage controlled oscillator and a radio frequency peak detector coupled to the output of the buffer. The radio frequency peak detector is configured to receive an ac signal from the voltage controlled oscillator and generate a dc value proportional to the ac signal at an output of the radio frequency peak detector. Furthermore, the output of the radio frequency peak detector generates a dc value proportional to an amplitude of the ac signal from the voltage controlled oscillator when the voltage controlled oscillator functions correctly. On the other hand, the output of the radio frequency peak detector is at zero volts when the voltage controlled oscillator fails to generate an ac signal. | 2012-11-15 |
20120286837 | SEMICONDUCTOR INTEGRATED CIRCUIT - According to one embodiment, a semiconductor integrated circuit is provided, which has mounted thereto a flip-flop circuit including a latch portion that takes and holds input data based upon a clock signal, and a clock portion that inputs the clock signal to the latch portion, wherein an active region of the flip-flop circuit is divided in such a manner that the width of the active region is secured, and each of the active regions has uniform width. | 2012-11-15 |
20120286838 | DELAY LINE CIRCUIT AND PHASE INTERPOLATION MODULE THEREOF - A phase interpolation module comprising a first, second, and third phase interpolation units is proposed. Each of the first, second, and third phase interpolation units comprises a first through third inverters, a first and second resistors, wherein the first resistor is coupled between an output end of the first inverter and an input end of the third inverter, and the second resistor is coupled between an output end of the second inverter and the input end of the third inverter. The first and second inverters of the first phase interpolation unit receive a first signal, the first and second inverters of the third phase interpolation unit receive a second signal, and the first and second inverters of the second phase interpolation unit respectively receive the first and second signals. | 2012-11-15 |
20120286839 | Systems and Methods for a Continuous, Linear, 360-Degree Analog Phase Shifter - Embodiments of the invention may be directed to a continuous analog phase shifter for radio frequency (RF) signals, which can be integrated on a CMOS process or another compatible process where inherent process-dependent passive components such as inductors and capacitors may have low quality factors. Insertion loss degradation for a given amount of phase shift may be compensated by using an active compensation circuit/device that smartly controls negative resistance generated from the compensation circuit/device to cancel out finite resistance of a network, leading to very small insertion loss variation. According to an example aspect of the invention, improved phase linearity and increased phase shift for a given size may be obtained by incorporating the compensation circuit/device. Thus, example analog phase shifters in accordance with example embodiments of the invention may have one or more of low insertion loss variation, small size, and good phase linearity over more than a 360 degree phase shift. | 2012-11-15 |
20120286840 | DELAY GENERATOR - A delay generator comprises: a current source for supplying a current; a first delay portion, connected to the current source, comprising at least a plurality of inverters and a first capacitor having a first capacitance; and a second delay portion, connected to the current source, comprising at least a plurality of inverters and a second capacitor having a second capacitance, wherein the first capacitance is the same as the second capacitance, wherein the first delay portion generates a first delay by discharging of the first capacitor, wherein the second delay portion generates a second delay by charging of the second capacitor, and wherein the total delay generated by the delay generator is obtained by summation of the first delay and the second delay. | 2012-11-15 |
20120286841 | PULSE GENERATOR HAVING AN EFFICIENT FRACTIONAL VOLTAGE CONVERTER AND METHOD OF USE - Disclosed are systems and methods which provide voltage conversion in increments less than integer multiples of a power supply (e.g., battery) voltage. A representative embodiment provides power supply voltage multipliers in a binary ladder distribution to provide a desired number of output voltage steps using a relatively uncomplicated circuit design. By using different sources in various combinations and/or by “stacking” different sources in various ways, the voltage multiplier circuit may be used to provide desired voltages. In order to minimize the number of components used in a voltage converter of an embodiment, a capacitive voltage converter circuit uses one or more storage capacitors in place of pump capacitors in a voltage generation cycle. Also, certain embodiments do not operate to generate an output voltage until the time that voltage is needed. | 2012-11-15 |
20120286842 | PULSE GENERATOR AND METHOD OF DISPOSING PULSE GENERATOR - The semiconductor switching device of a switch circuit is disposed in an environment having a relatively low temperature, and a transformer is disposed in an environment having a relatively high temperature. A conduction path extends from a first DC input terminal to a second DC input terminal. An inductor is inserted in a section from a first branch to a second branch in the conduction path, and the switch circuit is inserted in a portion other than the section of the conduction path. A first transmission wire of a transmission line electrically connects the first branch and a first input terminal of a primary winding to each other. A second transmission wire of the transmission line electrically connects the second branch and a second input terminal of the primary winding to each other. The excitation inductance of the primary winding is higher than the excitation inductance of the inductor. | 2012-11-15 |
20120286843 | PROTECTION CIRCUIT - A P-channel MOS transistor MP | 2012-11-15 |
20120286844 | METHOD AND APPARATUS FOR CONTROLLING DEVICE IN ELECTRONIC EQUIPMENT - A method and apparatus for controlling a device in electronic equipment having a plurality of devices are provided. The apparatus includes a power supply for supplying power, a slave device including a driving circuit operated according to the supplied power for transmitting and receiving data to and from another device, a switching circuit for connecting the driving circuit to a ground terminal when the switching circuit is turned-on and for opening the driving circuit from the ground terminal when the switching circuit is turned-off, and a host device for transmitting a control signal for turning-on the switching circuit when driving the slave device and for turning-off the switching circuit when not driving the slave device. When the device is not driven, the switching circuit may open a driving circuit from a ground terminal, thereby cutting-off leakage of an electric current through the device. | 2012-11-15 |
20120286845 | CONSTANT VGS ANALOG SWITCH - Apparatus and methods for a switch circuit to provide a substantially constant gate-to source voltage to a passgate are provided. In an example, a switch circuit includes a summing circuit having an output configured to couple to the gate of a passgate, the summing circuit can be configured to maintain a substantially constant voltage between the gate and the source of the pass gate. | 2012-11-15 |
20120286846 | SWITCHING CIRCUIT - A switching circuit employs switches operating at low on resistance and high off capacitance. In connection with various example embodiments, a switching circuit selectively couples a communication port to one of two or more internal circuits based upon a type of input at the communication port. A sensor circuit senses the type of the input and, based upon the sensed input type, actuates one or more switches in the switching circuit. | 2012-11-15 |
20120286847 | TOUCH INTERFACE DEVICE AND METHOD FOR APPLYING CONTROLLABLE SHEAR FORCES TO A HUMAN APPENDAGE - A touch interface device includes a touch surface, an actuator, and an electrode. The actuator is coupled with the touch surface and is configured to move the touch surface in one or more directions. The electrode is coupled with the touch surface and is configured to impart a normal electrostatic force on one or more appendages of a human operator that engage the touch surface when an electric current is conveyed to the electrode. Movement of the touch surface by the actuator and the electrostatic force provided by the electrode are synchronized to control one or more of a magnitude or a direction of a shear force applied to the one or more appendages that engage the touch surface. | 2012-11-15 |
20120286848 | ELECTRONIC TRIMMING CIRCUIT - The trimming circuit includes a plurality of trimmable resistances that may be coupled among them, each resistance being connected in parallel to a respective fuse. The trimming circuit allows burning any number of fuses according to a fixed trimming sequence using only one or two dedicated pins because it includes an input diode-connected transistor and a plurality of trimming transistors of different sectional area, each connected to force current throughout a respective one of the shunt fuses and coupled to the input diode-connected transistor such to mirror the current flowing therethrough. The fuses of the trimming circuit may be burnt by applying a trimming voltage to the diode-connected input transistor with a voltage generator connected between a dedicated pin of the circuit and a terminal at a reference potential, such to force a current therethrough as long as the mirrored currents flowing throughout the fuses burn them. | 2012-11-15 |
20120286849 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE SYSTEM - A semiconductor apparatus includes: a plurality of electrical fuses; a rupture unit configured to rupture an electrical fuse in response to rupture information applicable to the plurality of electrical fuses, when a rupture enable signal is activated; a scan unit configured to output information on whether an each of the plurality of electrical fuses are ruptured or not, as scan information, when a scan enable signal is activated; and a shift register unit configured to receive an input signal in synchronization with a clock signal and store the input signal as the rupture information, and configured to receive the scan information and output the scan information as an output signal in synchronization with the clock signal. | 2012-11-15 |
20120286850 | Apparatus for storing a data value in a retention mode - Apparatus for storing a data value in the form of a master-slave latch supporting zig-zag power gating is described. A NAND gate | 2012-11-15 |
20120286851 | SEMICONDUCTOR DEVICE - A register circuit is provided which can hold data even after being powered off and which does not require a save operation and a return operation. In a register circuit including a plurality of register component circuits, a first transistor with small off-state current, and a second transistor with small off-state current, a data holding portion is connected to one of a source and a drain of the first transistor and one of a source and a drain of the second transistor. Since the first transistor and the second transistor have a small off-state current, electric charge does not leak from the data holding portion, and data is held by the data holding portion even after the register circuit is powered off. Thus, a save operation and a return operation are not required. | 2012-11-15 |
20120286852 | CHARGE-DISCHARGE DEVICE - A charge-discharge device has a current generating circuit, a charging circuit, a discharging circuit, and a signal processing circuit. The current generating circuit has a first transistor and a second transistor for generating a reference current. The charging circuit has a third transistor, coupled with the first transistor, for providing a charging current to a load according to the reference current. The discharging circuit has a fourth transistor, coupled with the second transistor, for providing a discharging current to the load according to the reference current. The signal processing circuit has a first input end coupled with the first and the second transistors, a second input end for coupling with the load, and an output end coupled with the first and the third transistors. The signal processing circuit amplifies the difference signal between the first end and the second input end to adjust the charging current and/or the discharging current. | 2012-11-15 |
20120286853 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a main circuit including a transistor, a pseudo-power supply line connected to a first power supply terminal of the main circuit, a first power supply line connected to the pseudo-power supply line via a first switch, a second power supply line connected to a second power supply terminal of the main circuit, a diode having a first end connected to the pseudo-power supply line and a second end connected to the first power supply line so that a potential difference between the pseudo-power supply line and the second power supply line is reduced in a conductive state, and a second switch having a first end connected to the pseudo-power supply line and a second end connected to the second power supply line. | 2012-11-15 |
20120286854 | High Voltage Ring Pump - A multi-stage device for boosting an input voltage is discussed. Each stage of the device comprises a stage of a ring oscillator and a charge pump. An oscillating signal, generated by the ring oscillator within the device, drives the charge pump in each stage of the device. The charge pumps of the stages are serially connected. A final stage of the multi-stage device is adapted to provide voltage to a load circuit. The multi-stage device is applicable for generation of different bias voltages from one or more source voltages. | 2012-11-15 |
20120286855 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device which can operate stably even in the case where a transistor thereof is a depletion transistor. The semiconductor device includes a first transistor for supplying a first potential to a first wiring, a second transistor for supplying a second potential to the first wiring, a third transistor for supplying a third potential at which the first transistor is turned on to a gate of the first transistor and stopping supplying the third potential, a fourth transistor for supplying the second potential to the gate of the first transistor, and a first circuit for generating a second signal obtained by offsetting a first signal. The second signal is input to a gate of the fourth transistor. The potential of a low level of the second signal is lower than the second potential. | 2012-11-15 |
20120286856 | PROGRAMMABLE NOISE FILTERING FOR BIAS KICKBACK DISTURBANCES - A system and method are disclosed for reducing the kickback disturbance in an electronic circuit. The system is based on the coupling of a programmable noise filter between bias blocks. In one embodiment the programmable noise filter includes capacitors, resisters and switches and forms a C-R-C circuit structure. By selecting the resistance and capacitance values and the status of the switches, the performance of the programmable noise filter is determined. Also disclosed is a system and method to reduce kickback disturbances comprising N+1 bias blocks, N programmable noise filters, and a bias reference generator, wherein N is equal to or greater than one. | 2012-11-15 |
20120286857 | SWITCHED CAPACITOR CIRCUIT WITH SWITCHING LOSS COMPENSATION MECHANISM AND COMPENSATION METHOD THEREOF - A switched capacitor circuit with switching loss compensation mechanism includes a resonant unit and a loss compensation unit. The resonant unit generates a resonant frequency and includes a capacitor switching unit for switching an output capacitor. The loss compensation unit is coupled to the resonant unit for providing loss compensation when the capacitor switching unit outputs different capacitance values. | 2012-11-15 |
20120286858 | Integrated circuit, method of generating a layout of an integrated circuit using standard cells, and a standard cell library providing such standard cells - An integrated circuit, a method of generating a layout of such an integrated circuit using standard cells, and a standard cell library providing such standard cells, are disclosed. The method of generating the layout comprises forming a plurality of rows, and populating each row with a plurality of standard cells chosen in dependence on the functional components required by the integrated circuit, each standard cell having its abutment area abutting the abutment area of at least one adjacent standard cell in the row. Within each row, each standard cell in that row is arranged to have a voltage connection area that is aligned with a common routing track, but with each standard cell having its voltage connection area configured so as not to extend across the entire width of the standard cell. Within each row, for each standard cell in the row, the voltage connection area of that standard cell is then connected to one of a plurality of voltage supplies having regards to a voltage requirement of the corresponding functional component defined by the standard cell, and independent of the voltage supply to which each adjacent cell in the row is connected. This provides a particularly flexible mechanism for placing standard cells during the layout operation, since standard cells that are required to run off the same voltage supply no longer need to be placed together. | 2012-11-15 |
20120286859 | INPUT COMMON MODE VOLTAGE COMPENSATION CIRCUIT - A voltage level shifter for a direct coupling of an external voltage source to a common mode of a circuit may include an amplifier, a voltage-controlled current source, a first and second resistors. A first input of the amplifier may be connected to the common mode. A second input of the amplifier may, via the first and second resistors, receive a voltage indicative of the external voltage source. The output of the amplifier may indicate a voltage difference between the first and second inputs. The voltage-controlled current source may be controlled by the voltage difference to supply a current to a common node of the first and second resistors so that the voltage difference between the first and second inputs may be minimized. | 2012-11-15 |
20120286860 | Systems and Methods for Minimizing Phase Deviation and/or Amplitude Modulation (AM)-to-Phase Modulation (PM) Conversion for Dynamic Range, Radio Frequency (RF) Non-Linear Amplifiers - Embodiments of the invention may provide systems and methods for minimizing phase deviation and/or amplitude modulation (AM)-to-phase modulation (PM) conversion for dynamic range, radio frequency (RF) non-linear amplifiers. In order to provide high dynamic range with reduced phase error, embodiments of the invention may utilize two separate paths for processing a signal. In particular, an input signal may be sampled and divided into each path. The first signal path may be used to shape a signal, and in particular, a voltage waveform at the load. The second signal path may be used for generating negative capacitances corresponding to the voltage waveform at the load. By combining the two signals at the load, a high-dynamic range, high-frequency, non-linear amplifier can be achieved that reduces phase error resulting from amplitude fluctuations with a relatively low unity-gain frequency (f | 2012-11-15 |
20120286861 | Doherty Amplifier and Method for Operation Thereof - An amplifier having a Doherty-type architecture and a method for operation thereof are provided. The amplifier comprises a main amplifier path comprising a main amplifier, an auxiliary amplifier path comprising an auxiliary amplifier, and an signal preparation unit configured to develop a main amplifier input signal for the main amplifier path and an auxiliary amplifier input signal for the auxiliary amplifier path based on an amplifier input that is to be amplified and a transition threshold associated with the amplifier input. By driving the main and auxiliary amplifiers as a function of the transition threshold, the gain of the Doherty-type amplifier may be increased. | 2012-11-15 |
20120286862 | Safety switching device for setting a safety-related device to a safe state - A safety switching device, with which a safety-related device, can be set into a safe state. The safety switching device has a microprocessor or microcontroller, which can set an electric drive to be protected into a safe state both if an emergency circuit breaker, protective door switch, and/or two-hand switch is activated and also if there is faulty operation of the safety-related device or electric drive. For this purpose, the microprocessor is implemented such that it can determine from at least one analog signal to be measured whether a predetermined parameter lies outside a predetermined operating range. In addition, the microprocessor can be a component of a safety device which is constructed for multiple-channel control of a safety-related electric drive. In this way, the safety switching device can respond to several safety functions independent of each other in order to set an electric drive into a safe state. | 2012-11-15 |
20120286863 | APPARATUS AND METHOD OF DIGITAL PREDISTORTION FOR POWER AMPLIFIERS WITH DYNAMIC NONLINEARITIES - Power amplifiers (PAs) using a Doherty or other power output level sensitive configuration have been employed for several years in telecommunications (as well as other applications) to take advantage of efficiency gains. For many of these applications, baseband signals are predistorted to compensate for nonlinearities in the PAs, but because there is a “switching event” in a Doherty-type amplifier (for example), the nonlinearities become dynamically varying. As a result, digital predistortion (DPD) becomes increasingly difficult to perform. Here, DPD modules are provided that adapt to changes in dynamically varying PAs based on a determination of the average power or other relevant metric prior to transmission. | 2012-11-15 |
20120286864 | Linearization in the Presence of Phase Variations - In one embodiment, a non-linear power amplifier generates an amplified output signal based on a pre-distorted signal generated by a digital pre-distorter based on an input signal. A feedback path generates a feedback waveform based on the amplified output signal. The feedback waveform is aligned in time with the input signal at the waveform level to identify a corresponding reference waveform. The feedback waveform and the corresponding reference waveform are both divided into a plurality of sub-waveforms. Each feedback sub-waveform is independently aligned in phase with its corresponding reference sub-waveform. The resulting plurality of phase-aligned feedback sub-waveforms are then combined to form a hybrid-aligned waveform that is compared to the reference waveform to adaptively update the digital pre-distorter. | 2012-11-15 |
20120286865 | Pre-Distortion Architecture for Compensating Non-Linear Effects - An input signal is pre-distorted to reduce distortion resulting from subsequent signal amplification. Frequency-dependent pre-distortion is preferably implemented in combination with frequency-independent pre-distortion, where the frequency-dependent pre-distortion is generated by expanding the derivative of a product of a pre-distortion function and the input signal and then relaxing constraints on the pre-distortion function and/or on frequency-dependent filtering associated with the frequency-dependent pre-distortion. In one implementation, four different frequency-dependent pre-distortion signals are generated for the expansion using up to four different pre-distortion functions and up to four different frequency-dependent filters. | 2012-11-15 |
20120286866 | AMPLIFIER PERFORMANCE STABILIZATION THROUGH PREPARATORY PHASE - A method and related systems for amplifier performance stabilization of a digitally predistorted RF power amplifier are disclosed. The characteristics of power amplifiers change as a function of temperature making adaptive digital predistortion highly problematic during initial application of an RF signal to a power amplifier. Embodiments disclose a method and systems in which the power amplifier is taken through a preparatory phase before the RF signal is applied to the power amplifier and the digital predistortion calculation starts. This is achieved by increasing the quiescent current of the power stages beyond nominal values for a rapid warm up and readjusting to its normal bias point when the radio frequency signal is applied and the digital predistortion is turned on. | 2012-11-15 |
20120286867 | AMPLIFIER APPARATUS, RADIO TRANSMITTING APPARATUS INCLUDING SAME, AND METHOD OF ADJUSTING GAIN OF AMPLIFIER APPARATUS - An object of the present invention is to provide an amplifier apparatus | 2012-11-15 |
20120286868 | CLASS D POWER AMPLIFIER - A class D power amplifier (PA) is provided. The PA generally comprises a driver, output capacitor, a matching network, and a cancellation circuit. The driver has an input, an output, and a parasitic capacitance, and the input of the driver is configured to receive complementary first and second radio frequency (RF) signals, where there is a free-fly interval between consecutive pulses from the first and second RF signals. The output capacitor and cancellation circuit are each coupled to the output of the driver such that the cancellation circuit provides harmonic restoration at least during the free-fly interval, and the matching network is coupled to the output capacitor. | 2012-11-15 |
20120286869 | CURRENT BUFFER - A current filtering current buffer amplifier includes: a first port and a second input port configured to be coupled to and receive input current; a first output port and a second output port configured to be coupled to and provide current to a load; a buffer configured to transfer the received input current to the first and second output ports as an output current, the buffer having an input impedance and an output impedance where the output impedance is higher than the input impedance, the buffer including first and second amplifiers, the first amplifier being a common mode feedback amplifier; and a filter coupled to the first and second input ports and coupled to the first and second amplifiers, the filter having a complex impedance and being configured to notch filter the received input current. | 2012-11-15 |
20120286870 | INTEGRATED CIRCUIT OF AN INTEGRATOR WITH ENHANCED STABILITY AND RELATED STABILIZATION METHOD - An integrated circuit integrator includes a first transconductance amplifier having a gain adjustable based upon a first control signal, and receives, as an input, a signal to be filtered, and generates, as an output, a corresponding amplified signal. The first transconductance amplifier includes an R-C output circuit to filter components from the amplified signal, and an output resistance being adjustable based upon a second control signal. A second transconductance amplifier is matched with the first transconductance amplifier, and has a gain adjustable based upon the first control signal, and a matched output resistance adjustable based upon the second control signal. A circuit is configured to force a reference current through the matched output resistance. An error correction circuit is coupled to the second transconductance amplifier and is configured to generate the second control signal so as to keep constant a voltage on an output of the second transconductance amplifier. | 2012-11-15 |
20120286871 | SEMICONDUCTOR DEVICE - To provide a semiconductor device with low power consumption, in a semiconductor device including a differential amplifier to which an input potential and a reference potential are input, a gain stage, and an output stage from which an output potential is output, a potential supplied from the gain stage can be held constant by providing the output stage with a transistor with low leakage current in an off state. As the transistor with low leakage current in an off state, a transistor including an oxide semiconductor layer and a channel formation region included in the oxide semiconductor layer is used. | 2012-11-15 |
20120286872 | METHOD AND APPARATUS FOR INCREASING THE EFFECTIVE RESOLUTION OF A SENSOR - Methods and devices for increasing a sensor resolution are disclosed. In one example, a two measurement process is used. A first measurement is used to effectively measure across a full range (e.g. 0 to 5 VDC) of the sensor. This first measurement may identify the current operating point of the sensor (e.g. 3.5 VDC). A second measurement may then be made to effectively measure across a sub-range of the sensor that encompasses the current operating point of the sensor (e.g. across a sub-range of 3.0 to 4.0 VDC for a current operating point of 3.5 VDC). The gain of the amplifier may be raised during the second measurement to produce a higher resolution measurement. In some cases, the first measurement may be used to determine an appropriate offset that may be applied so as to scale the amplifier to the desired sub-range of sensor that includes the current operating point of the sensor. In some cases, the two measurements may be used together to compute an effectively higher resolution measurement signal. In some cases, this may allow for a smaller and/or cheaper sensor to be used, while still achieving good results. | 2012-11-15 |
20120286873 | APPARATUS AND METHODS FOR BIASING POWER AMPLIFIERS - Apparatus and methods for biasing a power amplifier are disclosed. In one embodiment, a method of biasing a power amplifier includes shaping an enable signal using a time-dependent signal generator to generate a control current, amplifying the control current using a current amplifier to generate a correction current, and generating a bias current for a power amplifier using a primary biasing circuit. The primary biasing circuit is configured to use the correction current to correct for a variation in gain of the power amplifier when the power amplifier is enabled. | 2012-11-15 |
20120286874 | POSITIVE FEEDBACK COMMON GATE LOW NOISE AMPLIFIER - A Positive Feedback Common Gate Low Noise Amplifier (PFCGLNA) has positive feedback transistors and input transistors that are of the same conductivity type. Making the positive feedback and input transistors of the same conductivity type reduces sensitivity to process variations. Noise generated by the positive feedback transistors is used to cancel noise generated by the input transistors. In one embodiment, the PFCGLNA: 1) is tunable to have a substantially constant input impedance for any frequency in a wideband frequency range from 680 MHz to 980 MHz, and 2) has a noise figure less than 2.2 dB over the entire wideband frequency range. The input impedance of the PFCGLNA can be tuned to match a source that drives the PFCGLNA by setting a multi-bit digital control value supplied to a digitally-programmable tank load of the LNA. | 2012-11-15 |
20120286875 | SYSTEM PROVIDING SWITCHABLE IMPEDANCE TRANSFORMER MATCHING FOR POWER AMPLIFIERS - System providing switchable impedance transformer matching for power amplifiers. In an exemplary implementation, an amplifier providing switchable impedance matching includes an output inductor (L | 2012-11-15 |
20120286876 | MULTI-BAND POWER AMPLIFIER - Disclosed is a multi-band power amplifier capable of operating at multiple frequency bands. The multi-band power amplifier includes: a power amplification unit which amplifies an input signal; a matching network circuit which provides impedance matching between the power amplification unit and a load; and an auxiliary amplification unit which additionally supplies a certain magnitude of electric current to the load. | 2012-11-15 |
20120286877 | POWER AMPLIFIER - There is provided a power amplifier including an amplifying unit having at least two cascode amplifiers connected in parallel to amplify an input signal; and a bias supply unit supplying bias power to a common gate node of the two cascode amplifiers, and removing a signal of a pre-set frequency band corresponding to a baseband at the common gate node by controlling impedance of the common gate node. | 2012-11-15 |
20120286878 | APPARATUS AND METHODS FOR ELECTRONIC AMPLIFICATION - Apparatus and methods for electronic amplification are disclosed herein. In certain implementations, an amplifier is provided for amplifying a RF signal, and the amplifier includes a first transistor and a second transistor electrically connected in a Darlington configuration. The first and second transistors can be, for example, bipolar or field effect transistors and the first transistor can amplify an input signal and provide the amplified input signal to the second transistor. The first and second transistors are electrically connected to a power low node such as a ground node through first and second bias circuits, respectively. In certain implementations, the first transistor includes an inductor disposed in the path from the first transistor to the power low voltage. By including the inductor in the path from the first transistor to the ground node, the third order distortion of the amplifier can be improved. | 2012-11-15 |
20120286879 | Low Noise Oscillator - An oscillator for use in generating a signal having a desired frequency includes a first inductor element being electrically coupled from one end of a first capacitive element to a first voltage connection point, a second inductor element being electrically coupled from one end of a second capacitive element to a second voltage connection point, a third inductor element being electrically coupled from another end of the first capacitive element to the first voltage connection point, a fourth inductor element being electrically coupled from another end of the second capacitive element to the second voltage connection point. The first, second, third, and fourth inductor elements being configured such that a first conductive trace loop formed by the first and third inductor elements is interleaved with a second conductive trace loop formed by the second and fourth inductor elements such that said conductive trace loops are configured to operate in substantially a same magnetic field. A first drive circuit is electrically coupled to the first and second inductor elements forming a first resonance circuit with the first and second capacitive elements and a second drive circuit is electrically coupled to the third and fourth inductor elements forming a second resonance circuit with the first and second capacitive elements, such that the first and second drive circuits are mutually configured to establish and maintain a unified oscillation in the first and second resonance circuits at the desired frequency. | 2012-11-15 |
20120286880 | REFERENCE FREQUENCY GENERATING DEVICE - To provide a reference frequency generating device that can output a highly accurate reference frequency signal even if a reference signal becomes unable to be acquired. The reference frequency generating device includes a synchronization circuit, a temperature sensor, and a controller. The synchronization circuit controls a reference frequency signal outputted from a voltage controlled oscillator, by a control signal obtained based on a reference signal. The temperature detector detects a temperature of the voltage controlled oscillator being used. When the reference signal is unable to be acquired, the controller corrects a voltage controlled signal in consideration of a distortion in the aging characteristic of the voltage controlled oscillator based on a rate of change with time in a slope of the oscillator temperature, and generates a holdover control signal based on corrected contents to control the voltage controlled oscillator. | 2012-11-15 |
20120286881 | OSCILLATOR ARCHITECTURE HAVING FAST RESPONSE TIME WITH LOW CURRENT CONSUMPTION AND METHOD FOR OPERATING THE OSCILLATOR ARCHITECTURE - An oscillator architecture and a method for powering up/down the oscillator architecture are described. In one embodiment, an oscillator architecture includes a reference generator configured to generate reference signals and an in-phase/quadrature (IQ) oscillator configured to generate oscillation signals based on the reference signals. The reference generator includes a distributed start-up circuitry that includes multiple start-up circuits. The IQ oscillator includes at least one turbo comparator having a low power functional mode and a turbo functional mode. Other embodiments are also described. | 2012-11-15 |
20120286882 | ELECTRONIC CIRCUITRY - Electronic circuitry comprising operational circuits of active switching type requiring timing signals, and conductive means for distributing said timing signals to the operational circuits, wherein the timing signal distribution means includes a signal path that has different phases of a drive signal are supplied via active means at different positions about the signal path where that path exhibits endless electro-magnetic continuity without signal phase inversion or has interconnections with another signal path having different substantially unidirectional signal flow where there is no endless electromagnetic continuity between those signal paths and generally has non-linear associated circuit means where the signal path is of a transmission line nature. | 2012-11-15 |
20120286883 | SYNCHRONIZED OUTPUT OF MULTIPLE RING OSCILLATORS - A circuit for producing a synchronized output of multiple ring oscillators is disclosed. In one embodiment, the circuit includes a first ring oscillator configured to generate a first periodic signal and a second ring oscillator configured to generate a second periodic signal. The circuit may further include a selection unit coupled to receive the first periodic signal and the second periodic signal. The selection unit is configured to convey a first clock edge into each of the first and second ring oscillators responsive to a most recently received rising edge from one of the first and second periodic signals. The selection unit is further configured to convey a second clock edge into each of the first and second ring oscillators responsive to a most recently received falling edge from one of the first and second periodic signals, wherein the first and second clock edges are opposite in direction. | 2012-11-15 |
20120286884 | Micro-scale System to Provide Thermal Isolation and Electrical Communication Between Substrates - A microscale apparatus includes a microscale rigidized Parylene strap having a reinforcement structure extending from a first side of the strap, a first silicon substrate suspended by the microscale rigidized Parylene strap, the microscale rigidized Parylene strap conformally coupled to the first substrate, and a second substrate conformally coupled to the microscale rigidized Parylene strap to suspend the first silicon substrate through the microscale rigidized Parylene strap. | 2012-11-15 |
20120286885 | ATOMIC OSCILLATOR AND CONTROL METHOD OF ATOMIC OSCILLATOR - A method of controlling an atomic oscillator includes generating a resonant light pair in response to a center frequency signal and a sideband signal, and setting the sideband signal so that an electromagnetically induced transparency (EIT) phenomenon does not occur in a gas cell of the atomic oscillator. The method includes applying the resonant light pair to the gas cell and detecting an intensity level of light transmitted through the gas cell. While the sideband signal is set so that the EIT phenomenon is not occurring, the center frequency signal is varied until a minimum value of the intensity level is identified. A first frequency is calculated by subtracting a predetermined frequency offset from the center frequency at which the intensity level was equal to the minimum value. A center frequency of the resonant light pair is set to the first frequency for operation of the atomic oscillator. | 2012-11-15 |
20120286886 | Electromechanical Systems Oscillator with Piezoelectric Contour Mode Resonator for Multiple Frequency Generation - Electromechanical systems resonator structures, devices, circuits, and systems are disclosed. In one aspect, an oscillator includes an active component and a passive component connected in a feedback configuration. The passive component includes one or more contour mode resonators (CMR). A CMR includes a piezoelectric layer disposed between a first conductive layer and a second conductive layer. The conductive layers include an input electrode and an output electrode. The passive component is configured to output a first resonant frequency and a second resonant frequency, which is an odd integer harmonic of the first resonant frequency. The active component is configured to output a signal including the first resonant frequency and the second resonant frequency. This output signal can be a substantially square wave signal, which can serve as a clock in various applications. | 2012-11-15 |
20120286887 | PHASE LOCKED LOOP CIRCUIT HAVING A VOLTAGE CONTROLLED OSCILLATOR WITH IMPROVED BANDWIDTH - A voltage controlled oscillator includes a plurality of serially connected composite gain stages. A composite gain stage includes a transconductance stage and a transimpedance stage. The transconductance stage has first and second current paths from a first power supply voltage terminal to a second power supply voltage terminal. A first variable resistance is coupled between the first and second current paths. The transimpedance stage has a first inverter and a second inverter. The first inverter has an input terminal coupled to the output of the first current path and an output terminal. The second inverter has an input terminal coupled to the output of the second current path, and an output terminal. A second variable resistance is coupled between the input terminal and the output terminal of the first inverter, and a third variable resistance is coupled between the input terminal and the output terminal of the second inverter. | 2012-11-15 |
20120286888 | Switched Capacitor Array for Voltage Controlled Oscillator - A system comprises a voltage controlled oscillator comprising an inductor and a variable capacitor and a switched capacitor array connected in parallel with the variable capacitor. The switched capacitor array further comprises a plurality of capacitor banks wherein a thermometer code is employed to control each capacitor bank. In addition, the switched capacitor array provides N tuning steps for the oscillation frequency of the voltage controlled oscillator when the switched capacitor array is controlled by an n-bit thermometer code. | 2012-11-15 |
20120286889 | Systems and Methods for Wideband CMOS Voltage-Controlled Oscillators Using Reconfigurable Inductor Arrays - As wireless communication technology evolves, various transceivers become integrated into a single system, which implements a seamless connection to search available frequency bands and to provide wireless connections regardless of their wireless standards. One of the key technologies for seamless implementation is an ultra-wideband local oscillator, which can overcome the restriction of limited tuning range in typical RF local oscillators. Many RF oscillators incorporate LC-tuned oscillators because of their good noise performance while their tuning range is limited by fixed inductance and varied capacitance. The planar inductor fabricated on the CMOS process occupies a large area as well. By replacing the planar inductor with the array of bondwires, and including switches to provide proper impedance for the circuit to generate negative impedance, the tuning range of a CMOS voltage-controlled oscillator (VCO) is extended more than 100%, which number can not be achieved in a convention VCO. | 2012-11-15 |
20120286890 | TEMPERATURE-COMPENSATED OSCILLATOR AND ELECTRONIC DEVICE - A temperature-compensated oscillator includes a temperature sensor, a temperature compensation circuit, a voltage-controlled oscillation circuit adapted to output an oscillation signal on which temperature compensation is performed based on the temperature compensation voltage, an output circuit adapted to output an ON/OFF signal based on a relationship between variation of the detected-temperature voltage output by the temperature sensor and a reference voltage, a switch circuit adapted to supply the temperature compensation circuit with electrical power in response to the ON/OFF signal, and a sample-and-hold circuit adapted to be switched between a state of outputting the temperature compensation voltage to the voltage-controlled oscillation circuit while holding the temperature compensation voltage output by the temperature compensation circuit, and a state of outputting the temperature compensation voltage held to the voltage-controlled oscillation circuit while cutting the connection to the temperature compensation circuit in response to the ON/OFF signal. | 2012-11-15 |
20120286891 | MIXER CELL, MODULATOR AND METHOD - Embodiments provide a mixer cell, which is implemented to logically combine a data signal with an oscillator signal and a sign signal to obtain a mixer cell output signal based on the logical combination. Further embodiments provide a modulator with a plurality of mixer cells. | 2012-11-15 |
20120286892 | MEMS TUNABLE NOTCH FILTER FREQUENCY AUTOMATIC CONTROL LOOP SYSTEMS AND METHODS - Tunable notch filters and control loop systems and methods can include a tunable notch filter providing a stop band, a sensing circuit in communication with the tunable notch filter and adapted to determine a phase change between a reference signal and a signal reflected from the tunable notch filter, and a control loop in communication with the tunable notch filter and the sensing circuit, the control loop being operable to adjust the tunable notch filter to modify the phase change. | 2012-11-15 |
20120286893 | FILTER ARRAY FOR NARROWBAND AND WIDEBAND WAVEFORM OPERATION IN A COMMUNICATIONS RADIO - A communications radio has an IF stage with an associated filter array. The array includes at least one narrowband filter whose passband is less than 3 MHz, at least one wideband filter whose passband is 3 MHz or greater, a first switch with a common pole connected to an input terminal of the array, a second switch with a common pole connected to an output terminal of the array, a third switch whose common pole is operatively connected to the input terminal, and a fourth switch whose common pole is operatively connected to the output terminal. The first and the second switches cooperate to insert a selected filter between the first and second terminals. The third and the fourth switches cooperate to insert the filter array into either a receive signal path when the radio is in a receive mode, or a transmit signal path when in a transmit mode. | 2012-11-15 |