46th week of 2012 patent applcation highlights part 29 |
Patent application number | Title | Published |
20120287694 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - An embodiment is directed to a method of fabricating a semiconductor memory device, the method including preparing a substrate having a cell array region and a contact region, forming a thin film structure on the substrate, including forming sacrificial film patterns isolated horizontally by a lower isolation region, the lower isolation region traversing the cell array region and the contact region, and forming sacrificial films sequentially stacked on the sacrificial film patterns, and forming an opening that penetrates the thin film structure to expose the lower isolation region of the cell array region, the opening being restrictively formed in the cell array region. | 2012-11-15 |
20120287695 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a first wiring region and a second wiring region located adjacent to the first wiring region. First lines located in the first wiring region include a first portion, a first lead portion and first inclined portion. Second lines located in the second wiring region include a second portion, a second lead portion and a second inclined portion. The first and second portions are located in parallel with a same pitch, the first and second lead portions are located with a pitch which is larger than the pitch of the first and second portions, the first and second inclined portions extend the same direction at a predetermined angle. | 2012-11-15 |
20120287696 | STORAGE ELEMENT AND STORAGE DEVICE - A storage element includes a storage layer having a magnetization perpendicular to a layer surface and storing information according to a magnetization state of a magnetic material; a fixed magnetization layer having the magnetization as a reference of the information of the storage layer and perpendicular to the layer surface; an interlayer formed of a nonmagnetic material and interposed between the storage layer and the fixed magnetization layer; a coercive force enhancement layer adjacent to the storage layer, opposite to the interlayer, and formed of Cr, Ru, W, Si, or Mn; and a spin barrier layer formed of an oxide, adjacent to the coercive force enhancement layer, and opposite to the storage layer. The storage layer magnetization is reversed using spin torque magnetization reversal caused by a current in a lamination direction of a layer structure including the storage layer, the interlayer, and the fixed magnetization layer, thereby storing information | 2012-11-15 |
20120287697 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device crystallizes variable resistive element material layers arranged on side surfaces of multiple semiconductor layers in a stacked structure concurrently by applying a first current to any one of semiconductor layers in the stacked structure, and thereafter applies a second current to semiconductor layers other than a semiconductor layer to which the first current was applied. | 2012-11-15 |
20120287698 | Using a Bit Specific Reference Level to Read a Memory - A voltage derived from accessing a selected bit using one read current may be utilized to read a selected bit of an untriggered phase change memory after the read current is changed. As a result, different reference voltages may be used to sense the state of more resistive versus a less resistive selected cells. The resulting read. window or margin may be improved in some embodiments. | 2012-11-15 |
20120287699 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device selects one of a plurality of memory cells as a dummy memory cell. The dummy memory cell is connected to a bit line that is complementary to a bit line connected to a selected memory cell. This technique advantageously compensates capacitance of the bit line. The semiconductor memory device comprises a selected memory cell connected to a first bit line and a first word line, a dummy memory cell connected to a second bit line complementary to the first bit line and a second word line, and a sense amplifier connected to the first and second bit lines and configured to read data stored in the selected memory cell by simultaneously enablement of the first and second word lines. | 2012-11-15 |
20120287700 | GAIN CELL SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF - A memory cell including two transistors and one capacitor, which is known as a gain cell, is improved. One electrode of the capacitor is connected to a bit line, and the other electrode thereof is connected to a drain of a write transistor. A source of the write transistor is connected to a source line. As a result, for example, in the case where a stacked capacitor is used, the one electrode of the capacitor can be part of the bit line. Only one specific write transistor is turned on when a potential of the source line and a potential of the write bit line are set; thus, only one memory cell can be rewritten. | 2012-11-15 |
20120287701 | SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING SEMICONDUCTOR DEVICE - A memory device with low power consumption and a signal processing circuit including the memory device are provided. In a memory element including a phase-inversion element by which the phase of an input signal is inverted and the signal is output such as an inverter or a clocked inverter, a capacitor which holds data, and a switching element which controls storing and releasing of electric charge in the capacitor are provided. For example, one of electrodes of the capacitor is connected to an input terminal or an output terminal of the phase-inversion element, and the other electrode is connected to a switching element. The above memory element is used for a memory device such as a register or a cache memory in a signal processing circuit. | 2012-11-15 |
20120287702 | MEMORY CIRCUIT AND ELECTRONIC DEVICE - To provide a nonvolatile memory circuit having a novel structure. A first memory circuit, a second memory circuit, a first switch, a second switch, and a phase inverter circuit are included. The first memory circuit includes a first transistor formed using an oxide semiconductor film, a second transistor, a third transistor, and a capacitor. The first transistor formed using an oxide semiconductor film and the capacitor are used to form the nonvolatile memory circuit. Reductions in number of power supply lines and signal lines which are connected to the memory circuit and transistors used in the memory circuit allow a reduction in circuit scale of the nonvolatile memory circuit. | 2012-11-15 |
20120287703 | SEMICONDUCTOR DEVICE - When a CPU provided with a latch memory is operated, a constant storage method or an end storage method is selected depending on what is processed by the CPU; thus, the CPU provided with a latch memory has low power consumption. When the CPU provided with a latch memory is operated, in the case where the number of times of turning on and off the power source is high, a constant storage method is employed and in the case where the number of times of turning on and off the power source is low, an end storage method is employed. Whether a constant storage method or an end storage method is selected is determined based on the threshold value set depending on power consumption. | 2012-11-15 |
20120287704 | SPIN CURRENT GENERATOR FOR STT-MRAM OR OTHER SPINTRONICS APPLICATIONS - Spin current generators and systems and methods for employing spin current generators. A spin current generator may be configured to generate a spin current polarized in one direction, or a spin current selectively polarized in two directions. The spin current generator may by employed in spintronics applications, wherein a spin current is desired. | 2012-11-15 |
20120287705 | Spin-Torque Transfer Magneto-Resistive Memory Architecture - A method for operating a memory array device, includes initiating a write “0” state in the device, wherein the initiating the write “0” state includes inducing a first voltage in a word line of the device; and inducing a second voltage in a first bit line (BLT | 2012-11-15 |
20120287706 | ISOLATION DEVICE FREE MEMORY - An integrated circuit memory is based on isolation device free memory cells. The memory cells are passively coupled to bit lines and word lines. The memory cells include an anti-fuse element and an element of phase change material in series. A rupture filament through the anti-fuse layer acts as an electrode for the phase change element. Control circuitry is configured to apply bias arrangements for operation of the memory cells, including a first write bias arrangement to induce a volume of the higher resistivity phase in the phase change material establishing a first threshold for the selected memory cell below a read threshold, a second write bias arrangement to induce a larger volume of the higher resistivity phase in phase change material establishing a second threshold for the selected memory cell above the read threshold, and a read bias arrangement to apply the read threshold to the selected memory cell. | 2012-11-15 |
20120287707 | OPTOELECTRONIC MEMORY DEVICES - A structure. The structure includes a substrate, a resistive/reflective region on the substrate, and a light source/light detecting and/or a sens-amp circuit configured to ascertain a reflectance and/or resistance change in the resistive/reflective region. The resistive/reflective region includes a material having a characteristic of the material's reflectance and/or resistance being changed due to a phase change in the material. The resistive/reflective region is configured to respond, to an electric current through the resistive/reflective region and/or a laser beam projected on the resistive/reflective region, by the phase change in the material which causes a reflectance and/resistance change in the resistive/reflective region from a first reflectance and/or resistance value to a second reflectance and/or resistance value different from the first reflectance and/or resistance value. | 2012-11-15 |
20120287708 | SELECTION DEVICE FOR A SPIN-TORQUE TRANSFER MAGNETIC RANDOM ACCESS MEMORY - A spin-torque transfer magnetic random access memory (STT-MRAM) that includes a magnetic bit coupled between a first conductor line and a selection device. The selection device includes at least two transistors. The selection device is operative to (a) select the magnetic bit for a spin-torque transfer (STT) write operation when the at least two transistors are in a first state and (b) select the magnetic bit for a read operation when the at least two transistors are in a second state. The selection device may be implemented in silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) technology, and the transistors may include body ties. The selection device may also be radiation hardened. | 2012-11-15 |
20120287709 | NON VOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - In accordance with an embodiment, a non volatile semiconductor memory device includes a substrate, a first electrode, a functional film, and a second electrode. The first electrode is provided on the substrate. The functional film is located on the first electrode and serves as a storage medium. The second electrode is provided on the functional film or in the functional film, and has a convex curved upper surface. | 2012-11-15 |
20120287710 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE CAPABLE OF SPEEDING UP WRITE OPERATION - According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array, write circuit, memory unit, and voltage generation unit. A plurality of strings is arranged in the memory cell array, each of which includes a plurality of memory cells connected to word lines. The write circuit selects a first string selected as a sample from the memory cell array, and writes data to the memory cell. The memory unit holds, for each word line, the number of write operations to each memory cell of the first string. When data is written to each memory cell of a second string other than the first string, the voltage generation unit generates an initial write voltage based on the number of write operations, which corresponds to the selected word line and is read out from the memory unit. | 2012-11-15 |
20120287711 | FLASH MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME - A flash memory device includes a memory cell array, a temperature sensing unit, and a control unit. The memory cell array is configured to store a plurality of pieces of configuration data corresponding to respective temperature levels of the flash memory device, the pieces of configuration data indicative of respective operation parameter values of the flash memory device. The temperature sensing unit is configured to measure an ambient temperature of the flash memory device and to generate temperature level data. The a control unit is configured to receive the temperature level data from the temperature sensing unit, to read a piece of configuration data corresponding to the temperature level data from among the plurality of pieces of configuration data stored in the memory cell array, and to set operation parameters of the flash memory device according to an operation parameter value indicated by the read piece of configuration data. | 2012-11-15 |
20120287712 | SEMICONDUCTOR DEVICE - A semiconductor device including a logic circuit capable of decreasing a leakage current occurred during a standby state is provided. The semiconductor device includes a power supply portion for supplying a first operation voltage or a second operation voltage smaller than the first operation voltage; a P-type low-threshold transistor Tp for receiving the first or the second operation voltage from the power supply portion; and a N-type transistor Tn connected between the transistor Tp and a base potential. The transistors Tp, Tn construct a logic circuit. The power supply portion supplies the first operation voltage to the source of the transistor Tp in the enable state, and supplies the second operation voltage in a standby state. The second operation voltage is set so that voltage amplitude between gate and source of each transistor Tp, Tn is larger than the threshold value of the transistors Tp, Tn. | 2012-11-15 |
20120287713 | NONVOLATILE MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A nonvolatile memory device includes a plurality of memory blocks and a high voltage application unit configured to apply a high voltage to a word line of a memory block unselected from among the plurality of memory blocks and float the word line, during the erase operation. | 2012-11-15 |
20120287714 | INCREASED CAPACITY HETEROGENEOUS STORAGE ELEMENTS - Providing increased capacity in heterogeneous storage elements including a method for reading from memory. The method includes receiving a read word from a block of memory cells, where physical characteristics of the memory cells support different sets of data levels. The read word is separated into two or more virtual read vectors. For each of the virtual read vectors, the codebook that was utilized to generate the virtual read vector is identified and a partial read data vector is generated. The generating includes multiplying the virtual read vector by a matrix that represents the codebook. The partial read data vectors are combined into a read message and the read message is output. | 2012-11-15 |
20120287715 | Zero Cost NVM Cell Using High Voltage Devices in Analog Process - A non-volatile memory cell and array structure is disclosed situated within a high voltage region of an integrated circuit. The cell utilizes capacitive coupling based on an overlap between a gate and a drift region to impart a programming voltage. Programming is effectuated using a drain extension which can act to inject hot electrons. The cell can be operated as a one-time programmable (OTP) or multiple-time programmable (MTP) device. The fabrication of the cell relies on processing steps associated with high voltage devices, thus avoiding the need for additional masks, manufacturing steps, etc. | 2012-11-15 |
20120287716 | Using Channel-To-Channel Coupling To Compensate Floating Gate-To-Floating Gate Coupling In Programming Of Non-Volatile Memory - In a non-volatile storage system, during a verify operation, a verify voltage of a currently-sensed target data state is applied to a selected word line. A higher, nominal bit line voltage is used for the storage elements which have the currently-sensed target data state and a verify status of pass or no pass, a target data state lower than the currently-sensed target data state and a verify status of pass or no pass, or a target data state higher than the currently-sensed target data state and a verify status of pass. A lower bit line voltage is used for the storage elements which have the target data state higher than the currently-sensed target data state and a verify status of no pass, to enhance channel-to-channel coupling, as an offset to floating gate-to-floating gate coupling which is later caused by these storage elements. | 2012-11-15 |
20120287717 | FLASH MEMORY DEVICE AND ASSOCIATED CHARGE PUMP CIRCUIT - A charge pump circuit comprises a first booster set, a second booster group, and a detecting circuit. The first booster set receives a supply voltage and generates a first output voltage. The detecting circuit generates a detecting signal depending on the voltage level of the first output voltage. The second booster group receives the supply voltage and generates the first output voltage or a second output voltage according to the detecting signal. The second booster group is composed of a plurality of booster sets connected in parallel, wherein each booster set comprises a plurality of charge pump stages and a plurality of switch units. The number of serially-connected charge pump stages of each booster set in the second booster group is controlled by the plurality of switch units according to the stable voltage levels of the first and second output voltages. | 2012-11-15 |
20120287718 | PROGRAMMING MEMORY CELLS - Methods for programming, memory devices, and methods for reading are disclosed. One such method for programming a memory device (e.g., an SLC memory device) includes encoding a two level data stream to a three level stream prior to programming the memory. | 2012-11-15 |
20120287719 | FLASH MEMORY DEVICE HAVING SEED SELECTOR CIRCUIT - A flash memory device includes a memory cell array, a seed selector circuit, and a randomizing and de-randomizing circuit. The memory cell array includes memory cells forming multiple pages. The seed selector circuit stores seeds corresponding to the multiple pages, respectively. The randomizing and de-randomizing circuit randomizes data to be stored in a selected page. Each page has a corresponding seed and includes multiple sectors having corresponding sector offset values and seed values generated from the seed corresponding to the page. The seed selector circuit selects a seed value from the seed values of the selected page based on a sector offset value indicating a sector of the selected page to which a column offset value, input with an access request, belongs. The randomizing and de-randomizing circuit randomizes data to be stored in the selected page based on the seed value selected by the seed selector circuit. | 2012-11-15 |
20120287720 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME - A semiconductor memory device and a method of programming the same are provided which can improve the program accuracy by classifying cells depending on a program status of memory cells during a program operation to control a bit line program voltage. The method comprises classifying memory cells to be programmed based on program characteristics of the memory cells and sequentially providing word line program voltages having increasing voltage levels and bit line program voltages having decreasing voltage levels to the classified memory cells in a program operation, wherein differently classified two memory cells receive different bit line program voltages, respectively. | 2012-11-15 |
20120287721 | Programming Method for Nonvolatile Semiconductor Memory Device - A method for programming a plurality of memory cells of a nonvolatile semiconductor memory device comprises the steps of: sequentially performing a plurality of divide-by-2 operations on the plurality of memory cells; generating a plurality of reduced groups from the memory cells after each of the divide-by-2 operations is performed; sequentially programming the memory cells of each reduced group; generating a final group after a final divide-by-2 operation is performed; programming the memory cells of the final group; and verifying whether the memory cells of the final group are completely programmed. The memory cells of the final group are composed of all the memory cells of the nonvolatile semiconductor memory device and the verifying step is only performed after the step of programming the memory cells of the final group. | 2012-11-15 |
20120287722 | DYNAMIC DATA CACHES, DECODERS AND DECODING METHODS - Examples described include dynamic data caches (DDCs), decoders and decoding methods that may fit into a smaller width area. The DDCs, decoders and decoding method may be used in flash memory devices. A single column select line may be provided to select a plurality of cached bytes, while a second select line selects a byte of the selected plurality. The column select line may be routed parallel to bit lines carrying data, while the second select line may be routed perpendicular to the bit lines. | 2012-11-15 |
20120287723 | METHOD AND CIRCUIT TO DISCHARGE BIT LINES AFTER AN ERASE PULSE - Disclosed here in a method that comprises performing an erase operation on multiple cells in a memory device, the performing comprising applying an erase voltage to the multiple cells, bit lines coupled to the multiple cells being thereby charged up; and discharging the bit lines by coupling the bit lines to a discharging line through a DC path. | 2012-11-15 |
20120287724 | METHOD OF PROGRAMMING MEMORY AND MEMORY APPARATUS UTILIZING THE METHOD - A method of programming a memory is provided. The memory has a first cell, having a first S/D region and a second S/D region shared with a second cell. The second cell has a third S/D region opposite to the second S/D region. When programming the first cell, a first voltage is applied to a control gate of the first cell, a second voltage is applied to a control gate of the second cell to slightly turn on a channel of the second cell, a third and a fourth voltage are respectively applied to the first and the third S/D regions, and the second S/D region is floating. A carrier flows from the third S/D region to the first S/D region, and is injected into a charge storage layer of the first cell by source-side injection. | 2012-11-15 |
20120287725 | MEMORY CONTROLLER WITH SELECTIVE DATA TRANSMISSION DELAY - A DRAM controller component generates a timing signal and transmits, to a DRAM, (i) write data that requires a first time interval to propagate from the DRAM controller component to the DRAM and to be sampled by the DRAM on one or more edges of the timing signal, (ii) a clock signal that requires a second time interval to propagate from the DRAM controller component to the DRAM, and (iii) a write command, associated with the write data, to be sampled by the DRAM on one or more edges of the clock signal. The DRAM controller component includes series-coupled delay elements to generate respective incrementally delayed signals, and a multiplexer to select one of the delayed signals to time the transmission of the write data, such that transmission of the write data is delayed based on a difference between the first time interval and the second time interval. | 2012-11-15 |
20120287726 | ARCHITECTURE AND METHOD FOR MEMORY PROGRAMMING - Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon whether one or more of the data lines adjacent the data line are inhibited. In one such system, a connection circuit provides data corresponding to the inhibit status of a target data line to page buffers associated with data lines adjacent to the target data line. | 2012-11-15 |
20120287727 | DRAM REFRESH METHOD AND SYSTEM - A DRAM refresh method used with a memory system organized into rows of memory cells, each of which has an associated data retention time, with the system arranged to refresh predefined blocks of memory cells simultaneously. For each block of memory cells that are to be refreshed simultaneously, the minimum data retention time for the memory cells in the block is determined. Then, an asymmetric refresh sequence is created which specifies the order in which the blocks of memory cells are refreshed, such that the blocks having the shortest minimum data retention times are refreshed more often than the blocks having longer minimum data retention times. | 2012-11-15 |
20120287728 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device is provided relating to a test operation for a Low Power Double-Data-Rate (LPDDR) nonvolatile memory device. The nonvolatile memory device comprises a command decoder configured to decode a test mode signal in a test mode to output program and erasure signals into a memory, an address decoder configured to decode a command address inputted through an address pin in the test mode to output a cell array address into the memory, and an overlay window configured to store a data inputted through a data pin in the test mode. | 2012-11-15 |
20120287729 | SEMICONDUCTOR DEVICE - A semiconductor device includes a memory cell array including a plurality of memory array basic units, a first bus for transfer of address/control signals, including a first buffer circuit operating as a pipeline register, a second bus for bidirectional transfer of write/read data, including a second buffer circuit operating as a pipeline register, a first control circuit sequentially sending the address/control signals on the first bus, and a second control circuit sequentially sending/receiving write/read data on the second bus (FIG. | 2012-11-15 |
20120287730 | NON-VOLATILE MEMORY DEVICE AND SENSING METHOD THEREOF - A non-volatile memory device and a sensing method thereof are disclosed, which can sense multi-level data using resistance variation. The non-volatile memory device includes a cell array and a sensing unit. The cell array includes a plurality of unit cells where data is read out or written. The sensing unit compares a sensing voltage corresponding to data stored in the unit cell with a reference voltage, amplifies/outputs the compared result, measures a difference in discharge time where the sensing voltage is discharged in response to a resistance value of the unit cell during an activation period of a sensing enable signal after a bit line is precharged, and senses the data in response to the measured result. | 2012-11-15 |
20120287731 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes: a plurality of memory blocks; and a plurality of temperature sensors disposed adjacent to the respective memory blocks and configured to output a plurality of preliminary temperature sensing signals whose voltage levels are controlled in response to temperature change. A preliminary temperature sensing signal indicating the highest temperature among the plurality of preliminary temperature sensing signals is detected and used as a temperature sensing signal. | 2012-11-15 |
20120287732 | APPARATUS AND METHODS OF DRIVING SIGNAL - Apparatus and methods for driving a signal are disclosed. An example apparatus includes a pre-driver circuit and a driver circuit. The pre-driver circuit includes a step-down transistor and the driver circuit includes a pull-down transistor configured to be coupled to a reference voltage. In a first mode, the step-down transistor is configured to reduce a voltage provided to the pull-down transistor to less than a supply voltage, and in a second mode, the step-down transistor configured to provide the voltage of the supply voltage to the pull-down transistor. The pre-driver circuit of the example signal driver circuit may further include a step-up transistor configured to increase a voltage provided to a pull-up transistor of the driver circuit to greater than the reference voltage, and in the second mode, the step-up transistor configured to provide the voltage of the reference voltage to the pull-up transistor. | 2012-11-15 |
20120287733 | Memory circuitry with write boost and write assist - Memory circuitry | 2012-11-15 |
20120287734 | CONTINUOUS PROGRAMMING OF NON-VOLATILE MEMORY - A system connects a signal driver to a first control line that is connected to a first non-volatile storage element, charges the first control line while the signal driver is connected to the first control line, disconnects the signal driver from the first control line while the first control line remains charged from the signal driver, connects the signal driver to a second control line that is connected to a second non-volatile storage element, charges the second control line using the signal driver while the signal driver is connected to the second control line, and disconnects the signal driver from the second control line. The disconnecting of the signal driver from the first control line, the connecting the signal driver to the second control line and the charging of the second control line are performed without waiting for the first non-volatile storage element's program operation to complete. | 2012-11-15 |
20120287735 | CURRENT CONTROL CIRCUIT - A current control device is disclosed, which reduces a standby current of a semiconductor memory device and a turn-on current of a transistor. The current control device includes an input controller configured to combine a trigger signal and a set signal controlling a circuit operation status, and a drive unit configured to drive an output signal of the input controller, wherein the drive unit includes a current controller for selectively providing a ground voltage in response to an activation status of a pull-down driving signal. | 2012-11-15 |
20120287736 | SRAM Write Assist Apparatus - An SRAM write assist apparatus comprises a timer unit and a voltage divider. The voltage divider unit is configured to divide a voltage potential down to a lower level. The output of the voltage divider is connected to a memory cell in a write operation. The timer unit is configured to generate a pulse having a width inversely proportional to the voltage potential applied to a memory chip. Furthermore, the timer unit controls the period in which a lower voltage from the output of the voltage divider is applied to the memory cell. Moreover, external level and timing programmable signals can be used to further adjust the voltage divider's ratio and the pulse width from the timer unit. By employing the SRAM write assist apparatus, a memory chip can perform a reliable and fast write operation. | 2012-11-15 |
20120287737 | REPAIRING CIRCUIT FOR MEMORY CIRCUIT AND METHOD THEREOF AND MEMORY CIRCUIT USING THE SAME - A novelty repairing method and circuit are provided by the embodiments of the present invention, wherein the input/output (IO) compression manner can be used therein to reduce the access time during the chip probing 1 (CP1) test, and each redundant column selected line (RCSL) can be divided into several partial redundant column selected lines (P-RCSLs) which are respectively responsible for repairing the defects of the corresponding regions. Based upon the repairing method, the memory circuit can reduce the number of the RCSLs. Furthermore, a variable region dividing manner is applied therein, so as to increase the probability for repairing the defect of the memory circuit. | 2012-11-15 |
20120287738 | MEASURING DEVICE AND A MEASURING METHOD WITH HISTOGRAM FORMATION - A measuring device for the storage of test values and associated addresses provides a first storage region ( | 2012-11-15 |
20120287739 | CIRCUIT AND METHOD FOR CONTROLLING LEAKAGE CURRENT IN RANDOM ACCESS MEMORY DEVICES - A circuit for controlling leakage current in random access memory devices comprises a pre-charge equalization circuit. The pre-charge equalization circuit provides a pre-charge voltage to a pair of complementary bit lines of a memory cell of a random access memory device in accordance with a pre-charge signal. When the memory cell is in a self-refresh mode, the pre-charge signal is activated by a periodically triggered pre-charge request and also activated before and after the memory cell is self-refreshed. | 2012-11-15 |
20120287740 | SENSE AMPLIFIERS, MEMORIES, AND APPARATUSES AND METHODS FOR SENSING A DATA STATE OF A MEMORY CELL - Sense amplifiers, memories, and apparatuses and methods for sensing a data state of a memory cell are disclosed. An example apparatus includes a differential amplifier configured to amplify a voltage difference between voltages applied to first and second amplifier input nodes to provide an output. The example apparatus further includes first and second capacitances coupled to the first and second amplifier input nodes. A switch block coupled to the first and second capacitances is configured to couple during a first phase a reference input node to the first and second capacitances and to the first amplifier input node. The switch block is further configured to couple during the first phase an output of the amplifier to the second amplifier input node to establish a compensation condition. During a second phase, the switch block couples its input nodes to the first and second capacitances. | 2012-11-15 |
20120287741 | SEMICONDUCTOR STORAGE - An SRAM macro operates in a normal operation mode in which a plurality of memory-cell array blocks are accessible and in a low power mode in which bit lines in the memory-cell array blocks are left floating. When the SRAM macro returns from the low power mode to the normal operation mode, the bit lines in only memory-cell array blocks to be accessed among the plurality of memory-cell array blocks are precharged in sequence. This allows the peak of precharging current flowing into the SRAM macro to be dispersed. | 2012-11-15 |
20120287742 | CIRCUIT AND METHOD FOR OUTPUTTING REFRESH EXECUTION SIGNAL IN MEMORY DEVICE - A circuit for outputting a refresh execution signal to a memory cell of a memory device in an auto-refresh mode comprises a first frequency dividing unit, a first selection circuit, a second frequency dividing unit, and a second selection circuit. The first frequency dividing unit receives an auto-refresh signal from outside the memory device and generates a plurality of first divided signals. The first selection circuit generates a selection signal selected from the auto-refresh signal and the first divided signals. The second frequency dividing unit divides the frequency of the selection signal and generates a plurality of second divided signals. The second selection circuit generates the refresh execution signal from the selection signal and the second divided signals. | 2012-11-15 |
20120287743 | CLOCK HANDOFF CIRCUIT AND CLOCK HANDOFF METHOD - A clock handoff circuit outputting data in synchronism with a first clock input thereto as output data in synchronism with a second clock, includes: a dual port RAM capable of performing writing and reading independently of each other; a write address control section controlling write addresses of the dual port RAM in which the input data is written; a blank address detecting section detecting blank addresses among the write addresses in which the input data is not written; and a read address conversion section converting the write addresses of the dual port RAM excluding the blank address into read addresses from which the output data are read out. | 2012-11-15 |
20120287744 | MIXING SYSTEM COMPRISING AN EXTENSIONAL FLOW MIXER - The invention provides a mixing system comprising the following: A) at least one extensional flow mixer comprising: a generally open and hollow body having a contoured outer surface and having: a single entrance port and a single exit port; a means for compressing a bulk stream flowing through the generally open and hollow body in a direction of flow, and at least one injected additive stream introduced at the single entrance port in the direction of flow; and a means for broadening the bulk stream and the at least one injected additive stream, such that an interfacial area between the bulk stream and the at least one injected additive stream is increased as the bulk stream and the at least one injected additive stream flow through the generally open and hollow body in the direction of flow to promote mixing of the bulk stream and the at least one injected additive stream; B) a flow conductor having an axis and having a generally open and hollow flow mixer body cured therein; and C) a primary additive stream injector positioned at the entrance port of the generally open and hollow flow mixer body, wherein the primary additive stream injector injects an additive stream into the interior of the flow mixer in the direction of flow, when the bulk stream is flowing through the generally open and hollow flow mixer body, to allow for compression and broadening of the bulk stream and the additive stream together within the extensional flow mixer, to facilitate mixing of the bulk stream and the primary additive stream at an exit of the extensional flow mixer; and wherein the extensional flow mixer is followed by D) at least one helical static mixing element that is at least one half “flow conductor diameter (D | 2012-11-15 |
20120287745 | SYSTEM AND METHOD FOR AUTOMATICALLY ADJUSTING THE DOSAGE OF FEED PRODUCTS IN A LIVESTOCK FEED RECIPE - A system to adjust a predetermined dosage of main livestock feed products in a predetermined feed recipe, which includes one or more feed dosages, each indicative of a predetermined amount of a corresponding main feed product in said feed recipe. The system includes a memory for storing the recipe, a meteorological monitoring system suitable for determining one or more meteorological parameters in the storage areas of the feed products and a processing unit, configured to: determine a first value indicative of the humidity in each feed product as a function of meteorological parameters associated with the related storage area, determine a differential value indicative of the difference between the first value and a second value indicative of a reference humidity of said feed product, and adjust the feed dosage associated with each feed product in the recipe based on the differential value of humidity in the main feed product. | 2012-11-15 |
20120287746 | MANIFOLD FOR SOLVENT MIXING IN LIQUID CHROMATOGRAPHY SYSTEMS - Low-pressure mixing of fluids includes a pumping system having a pump and a fluidic inlet port through which fluid is introduced to the pump. A fluid proportioning system is in fluidic communication with the fluidic inlet port of the pumping system to deliver thereto a fluid stream comprised of multiple different fluids. The fluid proportioning system includes a manifold having a plurality of inlet ports, an outlet port connected by tubing to the fluidic inlet port of the pumping system, and an outlet conduit providing an internal fluidic passageway to the outlet port. Each inlet port is fluidically coupled to a fluid source to receive one of the different fluids and to the outlet conduit to deliver thereto the received fluid for delivery out of the manifold through the outlet port to the fluidic inlet port of the pumping system. | 2012-11-15 |
20120287747 | APPARATUS FOR MIXING - An Apparatus for mixing, comprising a tumble-blender adapted to receive and tumble a container to mix the contents of the container. The apparatus includes a drive means for driving a mixer of the container. The drive means is adapted to dock with the mixer when the container is received by the tumble-blender to enable operation of the mixer by the drive means. The drive is movably mounted, relative to the tumble-blender, to facilitate docking of the drive means with the mixer. | 2012-11-15 |
20120287748 | GYPSUM SLURRY MIXER - A gypsum slurry mixer includes a stationary part delimiting a mixing chamber including an upper part with a supply orifice, a lower part, a lateral part with an outlet orifice defining on the lateral part two end points and the outlet orifice is located within the angular sector formed by the centre of the stationary part and by the 2 points; a smooth movable part having an axis of rotation arranged in the stationary part; and an outlet system including a tubular element oriented tangentially to the stationary part along an axis of which the projection in a plane perpendicular to the axis of rotation is located within the sector formed by the acute angle between the projections, in the perpendicular plane, of the two tangents to the lateral part passing through the end points; and a collecting element. | 2012-11-15 |
20120287749 | INDUSTRIAL PROCESS MONITORING AND IMAGING - Exemplary embodiments include an apparatus for imaging a volume of material contained inside a vessel. The apparatus includes a plurality of synchronized acoustic sensors positioned at a periphery of an inner volume of the vessel. A processor combines the outputs of the acoustic sensors to identify at least one ambient noise source of the industrial process generating a noise field that illuminates an internal volume of the vessel and to provide an image of the material by temporal and spatial coherent processing of the transmission and reflection of the noise field generated by the noise source. | 2012-11-15 |
20120287750 | IMAGING APPARATUS - The invention relates to an imaging apparatus ( | 2012-11-15 |
20120287751 | METHOD AND SYSTEM OF A COMPOUND BUOY - A compound buoy. At least some of the illustrative embodiments are buoy systems that include: a surface buoy; a subsurface buoy comprising an elongated outer body; a connector disposed on the lower surface; and a winch having a line, the line coupled between the surface buoy and the subsurface buoy. The buoy system has first configuration in which the upper surface of the subsurface buoy abuts the surface buoy, the abutting relationship held by tension in the line, and the buoy system has a second configuration where a distance between the surface buoy and the subsurface is limited by a length of the line spooled off the winch. In operation, the subsurface buoy supports more of the subsurface load than the surface buoy. | 2012-11-15 |
20120287752 | COMPACT BROADBAND SOURCE AND METHOD - Method and marine acoustic source array for generating an acoustic wave in a body of water. The marine acoustic source array includes a first depth sub-array set of first acoustic source points configured to be provided at a first depth (z | 2012-11-15 |
20120287753 | SEISMIC CLOCK TIMING CORRECTION USING OCEAN ACOUSTIC WAVES - A method for identifying clock timing discrepancies in a plurality of clocks that are each associated with a seismic receiver, comprises the steps of collecting from at least a pair of receivers a data set corresponding to a selected time period, cross-correlating the data sets between at least one pair of receivers so as to produce cross-correlated data for positive, zero, and negative time lags, comparing the cross-correlated data for the positive and negative time lags to measure a timing asymmetry about the zero-lag time, and, for a receiver pair for which there is a non-zero timing asymmetry, using the asymmetry to identify a timing discrepancy between the clocks associated with that receiver pair. The each data set can be filtered so as to obtain data in a selected frequency range, which may avoid an active shot frequency. The data may be collected in the absence of active seismic shots. | 2012-11-15 |
20120287754 | Methods and Apparatus to Optimize Parameters in a Downhole Environment - Methods and apparatus to optimize parameters in a downhole environment are described. An example downhole tool includes a transmitter to transmit a signal into a subterranean formation and one or more receivers to receive at least a portion of the acoustic signal. The downhole tool also includes a processor configured to determine slownesses of different acoustic modes at a frequency of the signal received. Each of the slownesses is associated with a first parameter and a second parameter. The different acoustic modes have substantially different sensitivities to at least one of the first parameter or the second parameter. The processor to invert the determined slownesses of the different acoustic modes to determine an optimized value of the first parameter and an optimized value of the second parameter. | 2012-11-15 |
20120287755 | SEISMIC TRUE ESTIMATED WAVELET - The invention relates to processing seismic data that includes signals from at least two sources and typically three or four sources where source separation is necessary for geophysical analysis. Specifically, the present invention is a process for correcting data prior to inversion where the correction is provided to correct for the filtering effect of the earth. The earth is a non-homogenous seismic propagator that causes distortions of wavelets of seismic energy related to the source and receiver azimuth and offset that makes the identification of source specific data within the composite data harder to identify. Computing an earth response and correcting for the effects of the earth on the wavelets provides for more resolution and more clarity in the resulting data and better geophysical interpretation. | 2012-11-15 |
20120287756 | PIVOTING ULTRASONIC PROBE MOUNT AND METHODS FOR USE - A device for conducting ultrasonic inspections comprises a base. In addition, the device comprises a probe housing pivotally coupled to the base with a suspension system. Further, the device comprises an ultrasonic probe disposed within the probe housing and configured to transmit ultrasonic signals. The suspension system is configured to permit the probe housing to pivot relative to the base to transmit ultrasonic signals in a plurality of directions. | 2012-11-15 |
20120287757 | Forward Looking Seismics From Drill-Bit - Methods and instrumentation for detecting and representing at least one geologic formation in front of an operating drill-bit using the vibration noise generated by the operating drill-bit as a source, comprising at least one receive array comprising more than one receive vibration sensor elements, said at least one receive array are located in one or both of i) at least one receive well, and ii) submerged in water for sub-sea operation, and beam forming at least one receive signal from the signals from said more than one receive elements of said at least one receive array, and forming at least one reference signal representing the vibrations of the operating drill-bit, and correlating said at least one receive signal with said at least one reference signal with different correlation lags, and forming a seismic representation of the at least one geologic formation in front of the drill-bit through said correlating. | 2012-11-15 |
20120287758 | Pace Clock - The present invention relates to a pace clock and system for timing repetitive exercise, and more particularly to a pace clock and system for interval based training such as swim training to allow the swimmer predetermined periods of time to rest and recover after each individual swim within a particular set. A pace clock according to the present invention can display time in minutes and seconds; it can also display at least one additional digit which indicates the swim repeat number and/or cycle repeat number. The pace clock having a processing center, such as a micro-controller, to receive operation commands and workout plan from the master controller, such as computer and handheld device, through the transceiver. The master controller connecting with multiple pace clocks through RF or wired transceiver enables the coach to know the current status of the workout from multiple swimmers having their own workout plan. | 2012-11-15 |
20120287759 | STEPPING MOTOR CONTROL CIRCUIT AND ANALOGUE ELECTRONIC TIMEPIECE - A reverse rotation drive pulse includes a first pulse and a second pulse continuing from the first drive pulse and having a polarity opposite from that of the first drive pulse, a rotor is driven in the normal direction by the first pulse so that an axis of magnetic pole of the rotor rotates in the normal direction to a position beyond a notched potion nearest in the same direction, and then in the reverse direction by the second pulse to a position at which the same moves beyond the stable static position, and in the first segment and the second segment, a braking force with respect to the rotor is inhibited by connecting the detecting resistance of the coil in series and also the detection of rotation is performed. | 2012-11-15 |
20120287760 | STEPPING MOTOR CONTROL CIRCUIT AND ANALOG ELECTRONIC TIMEPIECE - A voltage detection circuit detects a voltage of a secondary cell that powers a stepping motor. A rotation detection circuit detects a rotation state of the stepping motor, and a control unit selects a main driving pulse for driving the stepping motor based on the detected rotation state from plural kinds of driving pulses having different energies. An analog display unit announces that the voltage of the secondary cell becomes a predetermined reference voltage when the voltage detection circuit detects that the voltage of the secondary cell becomes the predetermined reference voltage. When the control unit selects a predetermined main driving pulse before the voltage detection circuit detects that the voltage of the secondary cell becomes a current reference voltage, the control unit sets the reference voltage to the predetermined reference voltage higher than the current reference voltage. | 2012-11-15 |
20120287761 | SIGNALING DEVICE AND METHOD OF USE IN CARING FOR PETS - Devices having symbols or messages that are illuminated and darkened in accordance with a care-taking schedule for a pet, and methods for using the devices. | 2012-11-15 |
20120287762 | DIAL MODULE FOR A WATCH, AND WATCH INCLUDING SUCH A DIAL MODULE - Dial module for a clock provided with several pointers whose shafts can be driven by the clock mechanism, characterised in that the dial module ( | 2012-11-15 |
20120287763 | TIMEPIECE WITH INTERCHANGEABLE DISPLAY AND SOUNDS - The present disclosure pertains to a timepiece including at least one plate such that the at least one plate is associated with at least one sound. The timepiece includes a housing having a front opening. The at least one plate is supported by the housing such that the at least one plate is viewable through the front opening. A circuit establishing portion is disposed on each dial. A controller is adapted to be activated by the contact portion of the selected dial. The controller is programmed to transmit at least one sound corresponding with the at least one plate, each audible sound is transmitted at a predetermined time. | 2012-11-15 |
20120287764 | Disk With Embedded Flash Memory And Disc Drive - A disc has an outer section on which digital media can be recorded and a core in its center in which a flash memory is embedded with the core having a central hole and electrical contacts to the flash memory. A disc drive has a drive spindle that is to extend into the disc core central hole with one of the spindle or spindle hub having electrical contacts to engage with the core electrical contacts so that data can be written into and/or read from the core flash memory by electronic components of the drive. | 2012-11-15 |
20120287765 | OPTICAL HEAD AND OPTICAL DRIVE DEVICE - The present invention provides a unit and method for implementing an optical head and optical drive device whose configuration is simple, and which allows the generation of a track error signal in which no offset is caused to occur. The optical drive device includes a light source for emitting light beams, an objective lens for converging the light beams onto an optical disc, an optical-signal generation element for dividing the light beams into at least four regions by using a division line extending in the radial direction of the optical disc, and a division line extending in the track direction of the optical disc, the light beams being reflected by the optical disc, and an optical detector for receiving the light beams divided by the optical-signal generation element, wherein the up and down or right and left areas of the four regions are made different from each other. | 2012-11-15 |
20120287766 | OPTICAL PICKUP DEVICE AND OPTICAL DISC DEVICE - When performing recording/reproduction of information for a given recording layer of an optical disc having three recording layers, influences of reflected light from other recording layers are reduced or removed, thus making it possible to obtain a more stable RF signal or focus error signal. | 2012-11-15 |
20120287767 | DIFFRACTION GRATING, ABERRATION CORRECTION ELEMENT AND OPTICAL HEAD DEVICE - There is provided a diffraction grating including a convex portion and a concave portion which are used for lights having different wavelengths λ | 2012-11-15 |
20120287768 | Disk with Embedded Flash Memory and Disc Drive - A disc has an outer section on which digital media can be recorded and a core in its center in which a flash memory is embedded with the core having a central hole and electrical contacts to the flash memory. A disc drive has a drive spindle that is to extend into the disc core central hole with one of the spindle or spindle hub having electrical contacts to engage with the core electrical contacts so that data can be written into and/or read from the core flash memory by electronic components of the drive. | 2012-11-15 |
20120287769 | RESOURCE EFFICIENT ACOUSTIC ECHO CANCELLATION IN IP NETWORKS - System and methods provide acoustic echo monitoring and cancellation for real time media processing in an internet protocol (IP) media server in an IP network. An echo monitor is configured to selectively compare audio streams into and out of the IP media server through a selected port. The comparison determines an occurrence of an echo. An echo canceller in communication with the echo monitor is configured to respond to the determination by the echo monitor so as to remove the echo from at least one of the audio streams. A talk burst detector may be used to detect speech in at least one of the audio streams through the selected port. The echo monitor selectively compares the audio streams in response to a signal from the talk burst detector that indicates detection of speech. | 2012-11-15 |
20120287770 | WIRELESS COMMUNICATION TERMINAL APPARATUS, WIRELESS COMMUNICATION BASE STATION APPARATUS AND WIRELESS COMMUNICATION METHOD - Provided are a wireless communication terminal apparatus, a radio communication base station apparatus and a wireless communication method whereby the increase in the number of signaling bits can be suppressed, while the SRS capacity can be improved. RS type determining unit ( | 2012-11-15 |
20120287771 | OFDM GENERATION APPARATUS IN A MULTI-CARRIER DATA TRANSMISSION SYSTEM - OFDM generation apparatus and methods generating OFDM transmission signals from OFDM symbols, each including a plural OFDM subcarriers, for transmission in a multi-carrier data transmission system. In OFDM systems using the concept of Absolute OFDM and/or using Segmented OFDM common phase rotations of the OFDM subcarriers of the OFDM symbol with respect to adjacent OFDM symbols of the OFDM transmission signal generally appear. To avoid or compensate those common phase rotations, in the apparatus and method a selected mixing frequency is used for mixing the complex time-domain samples of the OFDM symbol from a baseband frequency up to a passband frequency by use of a mixing frequency to obtain the OFDM transmission signal, wherein the mixing frequency is selected such that common phase rotations of the OFDM subcarriers of the OFDM symbol with respect to adjacent OFDM symbols of the OFDM transmission signal are avoided or compensated after the mixing. | 2012-11-15 |
20120287772 | METHOD FOR PERFORMING SERIAL TRANSPORT COMMUNICATION, AND ASSOCIATED DEVICE - A method for performing serial transport communication is provided, where the method is utilized for performing communication between a plurality of devices, each of which provides a user with a plurality of wireless communication functions respectively complying with different wireless communication standards. The method includes: with regard to a first wireless communication function of the plurality of wireless communication functions, utilizing a serial transport protocol to perform communication between the plurality of devices through a transport bus; and with regard to a second wireless communication function of the plurality of wireless communication functions, utilizing the serial transport protocol to perform communication between the plurality of devices through the transport bus. An associated device is also provided. | 2012-11-15 |
20120287773 | Mechanism for alarm management of femto related systems to avoid alarm floods - A method of alarm management in a communications system having a number of Femto base stations ( | 2012-11-15 |
20120287774 | POWER AND CONNECTIVITY AWARE SWITCH - Systems, methods, and other embodiments associated with providing uninterrupted electrical power and data communications are described. One example method includes detecting primary electrical power loss to a network switch, and/or a loss of wired Internet connectivity to the network switch. The example method may also include controlling a backup power source to provide secondary electrical power to the network switch, and controlling a wireless access point to provide wireless Internet connectivity to the network switch. | 2012-11-15 |
20120287775 | AUTOMATIC RETRANSMISSION REQUEST CONTROL SYSTEM AND RETRANSMISSION METHOD IN MIMO-OFDM SYSTEM - An automatic retransmission request control system in an OFDM-MIMO communication system includes a retransmission mode selection part which selects a retransmission mode from among (a) a mode in which to transmit the data which are to be retransmitted, via the same antenna as in the previous transmission, while transmitting, at the same time, new data by use of an antenna via which no data retransmission is requested; (b) a mode in which to transmit the data, which are to be retransmitted, via an antenna via which no retransmission is requested, while transmitting new data via another antenna at the same time; (c) a mode in which to use STBC to retransmit the data via an antenna via which no retransmission is requested; and (d) a mode in which to use STBC to retransmit the data via all the available antennas. | 2012-11-15 |
20120287776 | NETWORK, NETWORK FAULT RECOVERY METHOD, AND NODE DEVICE - A ring network of a multicast label switch path scheme includes a plurality of nodes connected to form a ring. Further, a signal input to a first one of the nodes is branched to be transmitted in first and second different directions to a second and a third one of the nodes through a first working path and a second working path, respectively, in the ring network, the second one and the third one of the nodes defining end points of the first working path and the second working path, respectively, from the first one of the nodes, and a first backup path is set from the second one of the nodes to the first one of the nodes in the first direction, and a second back up path is set from the third one of the nodes to the first one of the nodes in the second direction. | 2012-11-15 |
20120287777 | DYNAMICALLY UPDATING ROUTING INFORMATION WHILE AVOIDING DEADLOCKS AND PRESERVING PACKET ORDER AFTER A LINK ERROR - A system for allowing dynamic changing of routing information of a network interconnect while avoiding deadlocks and preserving packet ordering. A network resiliency system detects when an error in the network interconnect occurs and dynamically generates new routing information for the routers that factors in the detected error. The network resiliency system then generates new routing information that factors in the failure. The network resiliency system then directs the network interconnect to enter a quiescent state in which no packets are transiting through the network interconnect. After the network interconnect enters the quiescent state, the network resiliency system directs the loading of the new routing information into the routing tables of the network interconnect and then directs the network interconnect to start injecting request packets into the network interconnect. | 2012-11-15 |
20120287778 | TRANSMISSION APPARATUS AND PATH SWITCHING METHOD - There is provided a transmission apparatus including a receiver unit configured to receive, from a network on a first layer, fault information regarding the network on the first layer, and a generator unit configured to generate, based on the fault information received by the receiver unit, switch information used to switch a transmission path of a network on a second layer higher than the first layer. | 2012-11-15 |
20120287779 | NETWORK AND FAULT RECOVERY METHOD - A ring network of a multicast label switch path scheme includes a transmitting node and receiving nodes connected to form a ring. A signal input to the transmitting node is branched to be transmitted in first and second different directions to first and second receiving nodes through first and second working paths, respectively, in the ring network. The first and second receiving nodes define terminal points of the first and second working paths, respectively, from the transmitting node. A first backup path is set from the first receiving node to the transmitting node, and a second backup path is set from the second receiving node to the transmitting node. The first backup path is in an opposite direction to the first working path and the second backup path is in an opposite direction to the second working path. | 2012-11-15 |
20120287780 | TUNING ROUTING METRICS TO REDUCE MAXIMUM LINK UTILIZATION AND/OR PROVIDE FAILURE RESILIENCY - A metric tuning technique optimizes the maximum link utilization of a set of links incrementally. Changes to the metric are constrained to be metric increases to divert routes from select links, thereby minimizing the number of changes required to achieve the optimization by avoiding the potential cascade of changes caused by attracting routes to a link. An interactive user interface is provided to allow a user to specify limits and constraints, and to select the sets of links to be addressed, including, for example, only the links that exceed a given link utilization threshold, the links having the highest link utilizations, the links having the highest failure effect, and so on. This incremental optimization technique is also used to optimize network resiliency by minimizing the network degradation caused by the failure of one or more links. | 2012-11-15 |
20120287781 | MOBILE VIRTUAL NETWORK OPERATOR MEDIATOR - The disclosed subject matter provides centralized carrier-side moderation for mobile virtual network operator support. The traffic stream received by a carrier from a radio area network can include carrier traffic, mobile virtual network operator traffic, or combinations thereof. Inspection of the traffic stream can allow the mobile virtual network operator traffic to be dynamically redirected to a mobile virtual network operator gateway. Redirection of traffic can be based on rules that can be provisioned by the carrier or the mobile virtual network operator. Further, the core-components of the mobile virtual network operator can be virtualized on the carrier-side to support deployment of a mobile virtual network operator. | 2012-11-15 |
20120287782 | PROGRAMMABLE AND HIGH PERFORMANCE SWITCH FOR DATA CENTER NETWORKS - This application describes routing packets from a source server to a plurality of ports of a switch. The switch is programmed by the control server and is used to direct incoming data packets to one or more ports of the switch in a manner that reduces congestion of incoming data packets to a destination server. Further, the control server queries congestion information from the switch, and then sends congestion notification back to the source server to either increase or decrease the amount of data being sent to the destination server. | 2012-11-15 |
20120287783 | LOAD BALANCING METHOD FOR A WIRELESS COMMUNICATION SYSTEM - A load balancing method for a wireless communication system, which has a backbone network, more than one Access Point connected to the backbone network and more than one client. In the method, the client transmits a Probe Request message to the more than one Access Point; the Access Point monitors its load. If the Access Point is under an overload situation, it transmits a Probe Response message to the client by the minimum transmitting power. If the Access Point is under normal load situation, it transmits a Probe Response message to the client by normal transmitting power. The client preferentially chooses the Access Point under normal load situation to access based on the signal strength of the received Probe Respond message. The method thus provides the client with a priority of the Access Points, wherein the Access Point under an overload situation has a lower priority. | 2012-11-15 |
20120287784 | SYSTEM AND METHOD FOR INTEGRATED QUALITY OF SERVICE IN A WIRELESS NETWORK ENVIRONMENT - A method is provided in one example embodiment and includes receiving a request for a service flow over a wireless link, where the request specifies resource requirements; dynamically reserving bandwidth for the resource requirements in a backhaul link; and mapping a packet received over the wireless link to the backhaul link based on an identification element associated with the packet and the service flow. | 2012-11-15 |
20120287785 | DATA TRAFFIC HANDLING IN A DISTRIBUTED FABRIC PROTOCOL (DFP) SWITCHING NETWORK ARCHITECTURE - A switching network includes an upper tier having a master switch and a lower tier including a plurality of lower tier entities. The master switch, which has a plurality of ports each coupled to a respective lower tier entity, implements on each of the ports a plurality of virtual ports each corresponding to a respective one of a plurality of remote physical interfaces (RPIs) at the lower tier entity coupled to that port. Data traffic communicated between the master switch and RPIs is queued within virtual ports that correspond to the RPIs with which the data traffic is communicated. The master switch applies data handling to the data traffic in accordance with a control policy based at least upon the virtual port in which the data traffic is queued, such that the master switch applies different policies to data traffic queued to two virtual ports on the same port of the master switch. | 2012-11-15 |
20120287786 | PRIORITY BASED FLOW CONTROL IN A DISTRIBUTED FABRIC PROTOCOL (DFP) SWITCHING NETWORK ARCHITECTURE - A switching network includes an upper tier and a lower tier including a plurality of lower tier entities. A master switch in the upper tier, which has a plurality of ports each coupled to a respective lower tier entity, implements on each of the ports a plurality of virtual ports each corresponding to a respective one of a plurality of remote physical interfaces (RPIs) at the lower tier entity coupled to that port. Data traffic communicated between the master switch and RPIs is queued within virtual ports that correspond to the RPIs on lower tier entities with which the data traffic is communicated. The master switch enforces priority-based flow control (PFC) on data traffic of a given virtual port by transmitting, to a lower tier entity on which a corresponding RPI resides, a PFC data frame specifying priorities for at least two different classes of data traffic communicated by the particular RPI. | 2012-11-15 |
20120287787 | PRIORITY BASED FLOW CONTROL IN A DISTRIBUTED FABRIC PROTOCOL (DFP) SWITCHING NETWORK ARCHITECTURE - A switching network includes an upper tier and a lower tier including a plurality of lower tier entities. A master switch in the upper tier, which has a plurality of ports each coupled to a respective lower tier entity, implements on each of the ports a plurality of virtual ports each corresponding to a respective one of a plurality of remote physical interfaces (RPIs) at the lower tier entity coupled to that port. Data traffic communicated between the master switch and RPIs is queued within virtual ports that correspond to the RPIs on lower tier entities with which the data traffic is communicated. The master switch enforces priority-based flow control (PFC) on data traffic of a given virtual port by transmitting, to a lower tier entity on which a corresponding RPI resides, a PFC data frame specifying priorities for at least two different classes of data traffic communicated by the particular RPI. | 2012-11-15 |
20120287788 | COMMUNICATION APPARATUS AND COMMUNICATION METHOD - A setting unit sets a communication mode for different one or more counterpart communication apparatuses to a non-spatial multiplexing mode or a spatial multiplexing mode. Setting unit switches the setting of the communication mode for the different one or more counterpart communication apparatuses from the non-spatial multiplexing mode to the spatial multiplexing mode, on the basis of a capability of a communication system having an own apparatus and the different one or more counterpart communication apparatuses. A transmitting unit processes a transmitting signal to the different one or more counterpart communication apparatuses to output the processed signal to a plurality of antennas, on the basis of the set communication mode. | 2012-11-15 |
20120287789 | FLOW CONSISTENT DYNAMIC LOAD BALANCING - A device provides a flow table. The device receives a data unit, determines a data flow associated with the data unit, determines whether the flow table includes an entry corresponding to the data flow, determines a current utilization of a group of output ports of the device, selects an output port, of the group of output ports, for the data flow based on the current utilization of the group of output ports when the flow table does not store an entry corresponding to the data flow, and stores the data unit in a queue associated with the selected output port. | 2012-11-15 |
20120287790 | Method and Apparatus - A method including determining traffic adjustment information for traffic from a base station to a relay node in dependence on a quantity of data intended for each user equipment at a first quality of service level on a first radio bearer; and causing said traffic adjustment information to be sent to a network element. | 2012-11-15 |
20120287791 | BALANCING LOAD IN A NETWORK, SUCH AS A DATA CENTER NETWORK, USING FLOW BASED ROUTING - Load balancing is performed in a network using flow-based routing. For example, upon detection of a big flow, one or more alternative paths from a source host to a destination host in the network may be discovered by probing the network and generating, for each of the one or more alternative paths, an association of the packet header information of the big flow to an alternative path discovered using results of probing the network. Upon congestion in a path currently being used by the big flow, an alternative path that is not congested is selected from the one or more discovered alternative paths. The packet header information of the big flow is altered using the generated association of the packet header information to the selected alternative path such that the big flow will be transmitted using the selected alternative path. | 2012-11-15 |
20120287792 | BIDIRECTIONAL RADIO-FREQUENCY PROBING - Wireless electronic devices may include wireless communications circuitry such as a transceiver, antenna, and other wireless circuitry. The transceiver may be coupled to the antenna through a bidirectional switch connector. The switch connector may mate with a corresponding radio-frequency test probe that is connected to radio-frequency test equipment. When the test probe is mated with the switch connector, the transceiver may be decoupled from the antenna. During transceiver testing, radio-frequency test signals may be conveyed between the test unit and the transceiver using the test probe. During antenna testing, radio-frequency test signals may be conveyed between the test unit and the antenna using the test probe. Transceiver testing and antenna testing may, if desired, be conducted in parallel using the test probe. | 2012-11-15 |
20120287793 | METHOD AND APPARATUS FOR DISTINGUISHING AND SAMPLING BI-DIRECTIONAL NETWORK TRAFFIC AT A CONVERSATION LEVEL - Network traffic is distinguished at a conversation level, providing sampling decision capability. A hash value is determined based on IP addresses and protocol type, giving unique identifiers for individual conversations. | 2012-11-15 |