47th week of 2020 patent applcation highlights part 60 |
Patent application number | Title | Published |
20200365447 | FILLING OPENINGS BY COMBINING NON-FLOWABLE AND FLOWABLE PROCESSES | 2020-11-19 |
20200365448 | DIELECTRIC GAP-FILLING PROCESS FOR SEMICONDUCTOR DEVICE | 2020-11-19 |
20200365449 | Metal Routing with Flexible Space Formed Using Self-Aligned Spacer Patterning | 2020-11-19 |
20200365450 | Low-Resistance Contact Plugs and Method Forming Same | 2020-11-19 |
20200365451 | METHODS OF FORMING INTERCONNECT STRUCTURES USING VIA HOLES FILLED WITH DIELECTRIC FILM FIRST AND STRUCTURES FORMED THEREBY | 2020-11-19 |
20200365452 | DEVICES INCLUDING STAIR STEP STRUCTURES, AND RELATED APPARATUSES AND MEMORY DEVICES | 2020-11-19 |
20200365453 | METAL LINER PASSIVATION AND ADHESION ENHANCEMENT BY ZINC DOPING | 2020-11-19 |
20200365454 | GAP-FILL METHOD HAVING IMPROVED GAP-FILL CAPABILITY | 2020-11-19 |
20200365455 | SEMICONDUCTOR PACKAGE DEVICE WITH INTEGRATED ANTENNA AND MANUFACTURING METHOD THEREOF | 2020-11-19 |
20200365456 | LOW RESISTIVITY FILMS CONTAINING MOLYBDENUM | 2020-11-19 |
20200365457 | SEMICONDUCTOR CHIP INCLUDING BACK-SIDE CONDUCTIVE LAYER | 2020-11-19 |
20200365458 | ARRAY SUBSTRATE, DISPLAY DEVICE AND METHOD FOR REPAIRING WIRE BREAK OF ARRAY SUBSTRATE | 2020-11-19 |
20200365459 | THROUGH SILICON VIA FABRICATION | 2020-11-19 |
20200365460 | CUTTING METHOD | 2020-11-19 |
20200365461 | CUTTING METHOD | 2020-11-19 |
20200365462 | METHOD OF MANUFACTURE OF GROUP III NITRIDE SEMICONDUCTOR | 2020-11-19 |
20200365463 | 3D SEMICONDUCTOR DEVICE AND STRUCTURE | 2020-11-19 |
20200365464 | CATALYST INFLUENCED CHEMICAL ETCHING FOR FABRICATING THREE-DIMENSIONAL SRAM ARCHITECTURES AND OPTICAL WAVEGUIDES | 2020-11-19 |
20200365465 | METHOD FOR FORMING SEMICONDUCTOR DEVICE | 2020-11-19 |
20200365466 | SEMICONDUCTOR DEVICE | 2020-11-19 |
20200365467 | TRANSISTOR HAVING STRAIN-INDUCING ANCHORS AND A STRAIN-ENHANCING SUSPENDED CHANNEL | 2020-11-19 |
20200365468 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE | 2020-11-19 |
20200365469 | HYBRID GATE STACK INTEGRATION FOR STACKED VERTICAL TRANSPORT FIELD-EFFECT TRANSISTORS | 2020-11-19 |
20200365470 | Electrically Testable Integrated Circuit Packaging | 2020-11-19 |
20200365471 | METHOD FOR TESTING BRIDGING IN ADJACENT SEMICONDUCTOR DEVICES AND TEST STRUCTURE | 2020-11-19 |
20200365472 | METHOD OF EVALUATING SILICON WAFER MANUFACTURING PROCESS AND METHOD OF MANUFACTURING SILICON WAFER | 2020-11-19 |
20200365473 | SUBSTRATE BONDING STRUCTURE AND SUBSTRATE BONDING METHOD | 2020-11-19 |
20200365474 | SEALING LID FORMED FROM TRANSLUCENT MATERIAL | 2020-11-19 |
20200365475 | BONDED BODY OF COPPER AND CERAMIC, INSULATING CIRCUIT SUBSTRATE, BONDED BODY OF COPPER AND CERAMIC PRODUCTION METHOD, AND INSULATING CIRCUIT SUBSTRATE PRODUCTION METHOD | 2020-11-19 |
20200365476 | RADIO FREQUENCY MODULE | 2020-11-19 |
20200365477 | Component Carrier With Surface-Contactable Component Embedded in Laminated Stack | 2020-11-19 |
20200365478 | SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME | 2020-11-19 |
20200365479 | Package with Tilted Interface Between Device Die and Encapsulating Material | 2020-11-19 |
20200365480 | PACKAGING FOR FINGERPRINT SENSORS AND METHODS OF MANUFACTURE | 2020-11-19 |
20200365481 | STACKED SEMICONDUCTOR DEVICES HAVING DISSIMILAR-SIZED DIES | 2020-11-19 |
20200365482 | ELECTRONIC MODULE FOR POWER CONTROL | 2020-11-19 |
20200365483 | PLATING FOR THERMAL MANAGEMENT | 2020-11-19 |
20200365484 | FASTENING UNIT FOR CONNECTING THERMALLY STRESSED COMPONENTS TO EACH OTHER | 2020-11-19 |
20200365485 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD FOR MANUFACTURING THE SAME | 2020-11-19 |
20200365486 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF | 2020-11-19 |
20200365487 | COOLER AND SEMICONDUCTOR MODULE | 2020-11-19 |
20200365488 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF | 2020-11-19 |
20200365489 | ELECTRONIC PACKAGE AND METHOD OF FABRICATING THE SAME | 2020-11-19 |
20200365490 | SEMICONDUCTOR DEVICE | 2020-11-19 |
20200365491 | SEMICONDUCTOR DEVICE | 2020-11-19 |
20200365492 | PACKAGE WITH LEAD FRAME WITH IMPROVED LEAD DESIGN FOR DISCRETE ELECTRICAL COMPONENTS AND MANUFACTURING THE SAME | 2020-11-19 |
20200365493 | LEADFRAME WITH SOCKETS FOR SOLDERLESS PINS | 2020-11-19 |
20200365494 | LEADLESS SEMICONDUCTOR PACKAGES, LEADFRAMES THEREFOR, AND METHODS OF MAKING | 2020-11-19 |
20200365495 | SEMICONDUCTOR DEVICE | 2020-11-19 |
20200365496 | SEMICONDUCTOR DEVICE | 2020-11-19 |
20200365497 | SEMICONDUCTOR DEVICE | 2020-11-19 |
20200365498 | SEMICONDUCTOR DEVICE | 2020-11-19 |
20200365499 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME | 2020-11-19 |
20200365500 | WIRING STRUCTURE AND METHOD FOR MANUFACTURING THE SAME | 2020-11-19 |
20200365501 | ORGANIC INTERPOSER AND METHOD FOR MANUFACTURING ORGANIC INTERPOSER | 2020-11-19 |
20200365502 | NANOSTRUCTURE ENERGY STORAGE AND ELECTRONIC DEVICE | 2020-11-19 |
20200365503 | WIRING BOARD, ELECTRONIC DEVICE, AND METHOD FOR DESIGNING WIRING BOARD | 2020-11-19 |
20200365504 | SEMICONDUCTOR DEVICE WITH REDISTRIBUTION LAYERS ON PARTIAL ENCAPSULATION AND NON-PHOTOSENSITIVE PASSIVATION LAYERS | 2020-11-19 |
20200365505 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND MODULE | 2020-11-19 |
20200365506 | MULTI-DIMENSIONAL VERTICAL SWITCHING CONNECTIONS FOR CONNECTING CIRCUIT ELEMENTS | 2020-11-19 |
20200365507 | HORIZONTAL PROGRAMMABLE CONDUCTING BRIDGES BETWEEN CONDUCTIVE LINES | 2020-11-19 |
20200365508 | SEMICONDUCTOR DEVICE | 2020-11-19 |
20200365509 | SEMICONDUCTOR DEVICE | 2020-11-19 |
20200365510 | PERIPHERAL INDUCTORS | 2020-11-19 |
20200365511 | PROGRAMMABLE CONNECTION SEGMENT AND METHOD OF FORMING THE SAME | 2020-11-19 |
20200365512 | Wafer-Scale Satellite With Integrated Propulsion And Attitude Control | 2020-11-19 |
20200365513 | METHOD OF FORMING STACKED TRENCH CONTACTS AND STRUCTURES FORMED THEREBY | 2020-11-19 |
20200365514 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF | 2020-11-19 |
20200365515 | ELECTRONIC PACKAGE WITH ROTATED SEMICONDUCTOR DIE | 2020-11-19 |
20200365516 | WIRING SUBSTRATE AND ELECTRONIC DEVICE | 2020-11-19 |
20200365517 | PACKAGE STRUCTURE | 2020-11-19 |
20200365518 | ADVANCED WAFER SECURITY METHOD INCLUDING PATTERN AND WAFER VERIFICATIONS | 2020-11-19 |
20200365519 | EMBEDDED CHIP IDENTIFICATION FORMED BY DIRECTED SELF-ASSEMBLY | 2020-11-19 |
20200365520 | METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE WITH OVERLAY GRATING | 2020-11-19 |
20200365521 | MARK PATTERN IN SEMICONDUCTOR DEVICE | 2020-11-19 |
20200365522 | DEVICE THERMAL MANAGEMENT | 2020-11-19 |
20200365523 | Electrical Component, Device and Package | 2020-11-19 |
20200365524 | Multitier Arrangements of Integrated Devices, and Methods of Protecting Memory Cells During Polishing | 2020-11-19 |
20200365525 | Dummy Die Placement Without Backside Chipping | 2020-11-19 |
20200365526 | SEMICONDUCTOR PACKAGE STRUCTURE | 2020-11-19 |
20200365527 | SEMICONDUCTOR PACKAGE | 2020-11-19 |
20200365528 | METHOD FOR DETECTING AN ATTEMPT TO BREACH THE INTEGRITY OF A SEMICONDUCTOR SUBSTRATE OF AN INTEGRATED CIRCUIT FROM ITS BACK FACE, AND CORRESPONDING INTEGRATED CIRCUIT | 2020-11-19 |
20200365529 | Semiconductor Devices Having an Electro-static Discharge Protection Structure | 2020-11-19 |
20200365530 | GROUNDING TECHNIQUES FOR BACKSIDE-BIASED SEMICONDUCTOR DICE AND RELATED DEVICES, SYSTEMS AND METHODS | 2020-11-19 |
20200365531 | Semiconductor Devices Having an Electro-static Discharge Protection Structure | 2020-11-19 |
20200365532 | INTEGRATED CIRCUIT WITH AN EMBEDDED INDUCTOR OR TRANSFORMER | 2020-11-19 |
20200365533 | DENSITY-GRADED ADHESION LAYER FOR CONDUCTORS | 2020-11-19 |
20200365534 | ETCH BARRIER FOR MICROELECTRONIC PACKAGING CONDUCTIVE STRUCTURES | 2020-11-19 |
20200365535 | APPARATUSES AND METHODS FOR COUPLING A WAVEGUIDE STRUCTURE TO AN INTEGRATED CIRCUIT PACKAGE | 2020-11-19 |
20200365536 | ANTENNA MODULE | 2020-11-19 |
20200365537 | SEMICONDUCTOR DEVICES HAVING LANDING PADS | 2020-11-19 |
20200365538 | SEMICONDUCTOR MODULE AND METHOD OF MANUFACTURING SEMICONDUCTOR MODULE | 2020-11-19 |
20200365539 | Bonding Structure And Method For Manufacturing The Same | 2020-11-19 |
20200365540 | METHOD OF SELF-ASSEMBLY WITH A HYBRID MOLECULAR BONDING | 2020-11-19 |
20200365541 | Via Structure for Packaging and a Method of Forming | 2020-11-19 |
20200365542 | DEVICES THREE-DIMENSIONAL STRUCTURES TO SUBSTRATES | 2020-11-19 |
20200365543 | SEMICONDUCTOR CHIP WITH REDUCED PITCH CONDUCTIVE PILLARS | 2020-11-19 |
20200365544 | SEMICONDUCTOR PACKAGE STRUCTURE | 2020-11-19 |
20200365545 | SEMICONDUCTOR PACKAGE | 2020-11-19 |
20200365546 | SEMICONDUCTOR DEVICE | 2020-11-19 |